Update INTEGRATOR_BACK

Fix [Issues #4](#4)
AUDIY · May 3, 2024 · 36f995c · 36f995c
1 parent 210227f
commit 36f995c
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diff --git a/03_INTEGRATOR/02_INTEGRATOR_BACK/INTEGRATOR_BACK.v b/03_INTEGRATOR/02_INTEGRATOR_BACK/INTEGRATOR_BACK.v
@@ -8,9 +8,9 @@
 * ------------ or -------
 *  1 - z^(-1)      z - 1 
 *
-* Version: 1.01
+* Version: 1.02
 * Author : AUDIY
-* Date   : 2024/05/02
+* Date   : 2024/05/03
 * 
 * Port
 *   Input
@@ -69,16 +69,18 @@ module INTEGRATOR_BACK #(
     reg CLKO_REG = 1'b0;
     reg signed [DATA_BIT_WIDTH-1:0] DATA_REG_POS = {(DATA_BIT_WIDTH){1'b0}};
     reg signed [DATA_BIT_WIDTH-1:0] DATA_REG_NEG = {(DATA_BIT_WIDTH){1'b0}};
+    reg signed [DATA_BIT_WIDTH-1:0] DATAI_REG    = {(DATA_BIT_WIDTH){1'b0}}; 
     wire signed [DATA_BIT_WIDTH:0] SUM_DATA;
 
-    assign SUM_DATA = (NRST_I == 1'b0) ? {(DATA_BIT_WIDTH+1){1'b0}} : ({DATA_I[DATA_BIT_WIDTH-1], DATA_I} + {DATA_REG_NEG[DATA_BIT_WIDTH-1], DATA_REG_NEG});
+    assign SUM_DATA = (NRST_I == 1'b0) ? {(DATA_BIT_WIDTH+1){1'b0}} : ({DATAI_REG[DATA_BIT_WIDTH-1], DATAI_REG} + {DATA_REG_NEG[DATA_BIT_WIDTH-1], DATA_REG_NEG});
 
     always @(posedge MCLK_I ) begin
         if (NRST_I == 1'b0) begin
             CLKI_REG     <=                   1'b0;
             CLKO_REG     <=                   1'b0;
             DATA_REG_POS <= {(DATA_BIT_WIDTH){1'b0}};
             DATA_REG_NEG <= {(DATA_BIT_WIDTH){1'b0}};
+            DATAI_REG    <= {(DATA_BIT_WIDTH){1'b0}};
         end else begin
             CLKI_REG <= CLK_I;
 
@@ -91,6 +93,7 @@ module INTEGRATOR_BACK #(
             /* Negative Edge of Data Clock (CLK_I) */
             if ((CLKI_REG == 1'b1) && (CLK_I == 1'b0)) begin
                 CLKO_REG     <= CLK_I       ;
+                DATAI_REG    <= DATA_I      ;
                 DATA_REG_NEG <= DATA_REG_POS;
             end
         end

diff --git a/03_INTEGRATOR/02_INTEGRATOR_BACK/INTEGRATOR_BACK_tb.v b/03_INTEGRATOR/02_INTEGRATOR_BACK/INTEGRATOR_BACK_tb.v
@@ -3,9 +3,9 @@
 *
 * Test bench for INTEGRATOR_BACK.v
 *
-* Version: 1.01
+* Version: 1.02
 * Author : AUDIY
-* Date   : 2024/05/02
+* Date   : 2024/05/03
 * 
 * License under CERN-OHL-P v2
 --------------------------------------------------------------------------------