Support for NXP QorIQ Layerscape Platform ls1043 #1871

ruchi393 · 2019-03-08T08:27:06Z

The patch series adds basic support for NXP QorIQ Layerscape Platforms. ls1043 platform support has been re-written to start the flow from BL2 binary instead of BL31. Additional boot sources like SD, NAND, QSPI have been added along with TRUSTED BOARD BOOT support.

ssg-bot · 2019-03-08T08:29:40Z

Can one of the admins verify this patch?

arm-tf-bot · 2019-03-08T08:33:03Z

This pull request modifies subsystem(s) maintained by @qoriq-open-source. Can you please review the changes?

drivers/nxp/ifc/nand/ifc.h

drivers/nxp/sfp/sfp_error_codes.h

plat/nxp/common/layerscape/README.TRUSTED_BOOT

plat/nxp/common/layerscape/tbbr.mk

plat/nxp/psci/aarch64/psci_utils.S

plat/nxp/sip_svc/aarch64/sipsvc.S

plat/nxp/soc-ls1043/aarch64/ls1043.S

plat/nxp/soc-ls1043/ls1043aqds/platform_def.h

plat/nxp/soc-ls1043/ls1043ardb/platform_def.h

ghost · 2019-03-08T10:31:02Z

You need to modify maintainers.rst to point at your documentation files/folders and update the maintainer if needed.

Also, you need to be able to build your platform with ERROR_DEPRECATED=1. You'll need to do some minor changes for that.

Add hooks for initialization of NOR and NAND flash attached to IFC controller.NAND driver provided init and read functionality. NOR is XIP memory. The driver provides placeholder for initialization. Signed-off-by: Ruchika Gupta <[email protected]>

Init function is added for QSPI NOR flash. The default configuration of the controller allows XIP read of the flash. The driver adds init function to take care of endianness of read transactions Signed-off-by: Ruchika Gupta <[email protected]>

Signed-off-by: York Sun <[email protected]> Signed-off-by: Ruchika Gupta <[email protected]>

Signed-off-by: Ruchika Gupta <[email protected]>

NXP QorIQ platforms require the bl2.bin to be combined with certain commands and RCW. This tool converts the bl2.bin to the required bl2.pbl format. Signed-off-by: Pankaj Gupta <[email protected]> Signed-off-by: Ruchika Gupta <[email protected]>

QorIQ series have a builtin BL1 or ROM which transfers control to the external bootloader in EL3 mode. The patch series establishes common bootflow across NXP QorIQ Layerscape ARMv8 platforms where ROM loads BL2 in SoC Internal Memory. BL2 binary runs in EL3 mode and further loads BL31, BL32 and BL33. The earlier support added in plat/layerscape is now moved to a common plat/nxp folder removing the BL1 binary. Following feature set are supported: - LS1043 RDB and QDS board - Boot from NOR, QSPI, SD, NAND flash - Support for complete PSCI functionality - OPTEE Boot Signed-off-by: rocket <[email protected]> Signed-off-by: York Sun <[email protected]> Signed-off-by: Pankaj Gupta <[email protected]> Signed-off-by: Ruchika Gupta <[email protected]>

CAAM is the cryptographic accelerator present on QorIQ Layerscape Platforms. Functionality has been added for generating random number, platform specific key and do RSA verification and hash using this accelerator. Signed-off-by: Pankaj Gupta <[email protected]> Signed-off-by: Ruchika Gupta <[email protected]>

On NXP QorIQ devices, for establishing chain of trust a header called CSF header is created for each image. This driver is a parser for the CSF header used in CoT Signed-off-by: Ruchika Gupta <[email protected]>

Platforms Signed-off-by: Ruchika Gupta <[email protected]>

Two flows are supported for TRUSTED BOOT. One is the ARM TBBR flow which uses MBED TLS and other is traditional QorIQ Secure boot methodology using CSF Headers. README.TRUSED_BOOT provides more details on the TRUSTED BOOT supported. Signed-off-by: Ruchika Gupta <[email protected]>

Signed-off-by: Ruchika Gupta <[email protected]>

ghost · 2019-03-12T12:40:11Z

docs/plat/nxp-layerscape.rst

@@ -0,0 +1,175 @@
+NXP SoCs - Overview


This file doesn't render correctly in rst (check http://rst.ninjs.org).

If you don't really want the rst formatting capabilities maybe you could just save it as txt. If you want to use rst, please make sure that it renders properly.

The file has to be rst formatted as it will enable auto-generation of HTML and other formats easily. This will enable easier migration to trustedfirmware.org later.

ghost · 2019-03-12T12:42:30Z

plat/nxp/common/aarch64/nxp_helpers.S

+	 * ---------------------------------------------
+	 */
+
+#if MULTI_CONSOLE_API


We are only going to keep the multi console. You shouldn't check for MULTI_CONSOLE_API in your code, you should assume it is going to be 1 and force it to 1 in the makefile.

ghost · 2019-03-12T12:42:56Z

plat/nxp/common/aarch64/nxp_helpers.S

+     /* generate a lsb-based mask for the core
+      * SoC core = ((cluster * cpu_per_cluster) + core)
+      * mask = (1 << SoC core)
+      */


Please, fix the coding style.

ghost · 2019-03-12T12:44:03Z

plat/nxp/common/include/lsch2.h

+#ifndef __ASSEMBLER__
+#include <endian.h>
+
+#define FETCH_SOC_ID(x) (((x & DCFG_ENDIANNESS_MASK) == NXP_MANUFACTURER_ID) ?\


Add parentheses to x.

ghost · 2019-03-12T12:47:56Z

plat/nxp/psci/include/plat_psci.h

+#define  SCR_FIQ_MASK           0x4
+
+#define CPUECTLR_EL1  S3_1_C15_C2_1
+#define CPUACTLR_EL1  S3_1_C15_C2_0


All definitions between lines 46 and 62 look to me like they should be in common files (either lib/cpu headers or arch.h/arch_helpers.h).

ghost · 2019-03-12T12:54:59Z

drivers/nxp/sfp/sfp.h

+int sfp_check_its(void);
+int sfp_check_oem_wp(void);
+
+#ifdef NXP_SFP_BE


Add parentheses to a.

ghost · 2019-03-12T12:57:31Z

tools/nxp/byte_swap.c

+		return -1;
+	}
+
+	fp = fopen(argv[1], "rwb+");


This should be just rb+ or wb+ depending on what you need. rwb+ doesn't look like it's allowed to me.

ghost · 2019-03-12T12:59:05Z

drivers/nxp/sd/sd_mmc.c

+	/* high voltage bits 2.7 - 3.6 */
+	mmc->voltages_caps = MMC_OCR_VDD_FF8;
+
+#ifdef SD_DMA_CAPABILITY


All the options of this driver should probably be prefixed by NXP_ and documented (at least in the header of the driver).

ghost · 2019-03-12T12:59:33Z

drivers/nxp/sd/sd_mmc.h

+#define esdhc_out32(a, v)       mmio_write_32((uintptr_t)a, bswap32(v))
+#elif defined(NXP_ESDHC_LE)
+#define esdhc_in32(a)           mmio_read_32((uintptr_t)a)
+#define esdhc_out32(a, v)       mmio_write_32((uintptr_t)a, v)


Add parentheses to a.

ghost · 2019-03-12T13:02:12Z

drivers/nxp/ddr/nxp-ddr/ddr.c

+#if defined(PHY_GEN2_FW_IMAGE_BUFFER) && !defined(NXP_DDR_PHY_GEN2)
+#error Missing NXP_DDR_PHY_GEN2
+#endif
+#ifdef NXP_DDR_PHY_GEN2


The options should be documented somewhere. At least create a list of the available options, even if they don't describe much of what they do. I understand that most DDR drivers are mostly magic code with magic constants.

ghost · 2019-04-05T08:42:05Z

As part of the migration to trustedfirmware.org ARM-software/tf-issues#681 we have switched the main development repository to Gerrit (https://review.trustedfirmware.org/). It is unfortunate that the switch has happened while your PR was being reviewed, but we don't intend to merge more patches through GitHub to avoid confusion.

Could you please follow the instructions in https://github.com/ARM-software/arm-trusted-firmware/blob/master/contributing.rst to continue with the review? We're sorry for the inconvenience.

sandrine-bailleux-arm · 2019-04-05T08:56:28Z

In addition to the contribution guidelines, the following Getting starting guide might help in this process.

ruchi393 changed the title ~~Nxp qoriq~~ Support for NXP QorIQ Layerscape Platform ls1043 Mar 8, 2019

ghost reviewed Mar 8, 2019

View reviewed changes

Ruchika Gupta and others added 7 commits March 11, 2019 09:32

nxp: Add driver for DDR Controller QorIQ Layerscape platforms

78a2482

Signed-off-by: York Sun <[email protected]> Signed-off-by: Ruchika Gupta <[email protected]>

nxp: Add i2c controller driver for QorIQ Layerscape platforms

9bc47cc

Signed-off-by: York Sun <[email protected]> Signed-off-by: Ruchika Gupta <[email protected]>

nxp: Add SD controller driver for QorIQ Layerscape Platforms

87ce326

Signed-off-by: Ruchika Gupta <[email protected]>

nxp: Add SFP controller driver for QorIQ Layerscape Platforms

aebd07e

Signed-off-by: Ruchika Gupta <[email protected]>

ruchi393 force-pushed the nxp_qoriq branch from ef082b1 to c5bb11d Compare March 11, 2019 10:53

Ruchika Gupta added 6 commits March 12, 2019 14:23

nxp: Add driver for CSF header parsing

6eebd82

On NXP QorIQ devices, for establishing chain of trust a header called CSF header is created for each image. This driver is a parser for the CSF header used in CoT Signed-off-by: Ruchika Gupta <[email protected]>

nxp: Add driver for Security Monitor Block for QorIQ Layerscape

3e2ea58

Platforms Signed-off-by: Ruchika Gupta <[email protected]>

nxp: Update Maintainer for QorIQ layerscape Platforms

b146b69

Signed-off-by: Ruchika Gupta <[email protected]>

ruchi393 force-pushed the nxp_qoriq branch from c5bb11d to b146b69 Compare March 12, 2019 09:06

ghost reviewed Mar 12, 2019

View reviewed changes

joannafarley-arm closed this May 15, 2019

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Support for NXP QorIQ Layerscape Platform ls1043 #1871

Support for NXP QorIQ Layerscape Platform ls1043 #1871

ruchi393 commented Mar 8, 2019 •

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ghost commented Apr 5, 2019

sandrine-bailleux-arm commented Apr 5, 2019

Support for NXP QorIQ Layerscape Platform ls1043 #1871

Support for NXP QorIQ Layerscape Platform ls1043 #1871

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ruchi393 commented Mar 8, 2019 • edited Loading

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ghost commented Apr 5, 2019

sandrine-bailleux-arm commented Apr 5, 2019

ruchi393 commented Mar 8, 2019 •

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