MESSAGES FROM THE VIVADO GUI: Message Box






[DRC LUTLP-1] Combinatorial Loop Alert: 22 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[0].i_axi_serializer/i_rd_id_fifo/status_cnt_q_reg[1]_0. Please evaluate your design. The cells in the loop are: i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_rd_id_fifo/FSM_onehot_wr_state_q[2]_i_5, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_rd_id_fifo/FSM_onehot_wr_state_q[2]_i_7, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[2].i_axi_serializer/i_wr_id_fifo/FSM_onehot_wr_state_q[2]_i_8, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[1].i_axi_serializer/i_rd_id_fifo/FSM_onehot_wr_state_q[2]_i_9, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_rr_arb_tree/gen_arbiter.gen_int_rr.gen_lock.lock_q_i_2__7, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_axi_shim/gen_arbiter.gen_int_rr.gen_lock.lock_q_i_3__1, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_wr_id_fifo/gen_spill_reg.a_data_q[id][0]_i_2__13, i_cheshire_soc/i_axi_xbar/i_xbar_unmuxed/gen_slv_port_demux[0].i_axi_demux/i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_data_q[id][0]_i_5__3, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[2].i_axi_serializer/i_wr_id_fifo/gen_spill_reg.a_data_q[id][1]_i_3__6, i_cheshire_soc/i_axi_xbar/i_xbar_unmuxed/gen_slv_port_demux[0].i_axi_demux/i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_data_q[id][1]_i_5__7, i_cheshire_soc/i_axi_xbar/i_xbar_unmuxed/gen_slv_port_demux[0].i_axi_demux/i_r_spill_reg/spill_register_flushable_i/state_q[1]_i_3__4, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_dcache_data_fifo/status_cnt_q[2]_i_4__3, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_dcache_data_fifo/write_pointer_q[1]_i_3__1, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_wr_id_fifo/write_pointer_q[1]_i_4__3, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_wr_id_fifo/write_pointer_q[1]_i_4__4... and (the first 15 of 22 listed).




[DRC LUTLP-1] Combinatorial Loop Alert: 22 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[0].i_axi_serializer/i_rd_id_fifo/status_cnt_q_reg[1]_0. Please evaluate your design. The cells in the loop are: i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_rd_id_fifo/FSM_onehot_wr_state_q[2]_i_5, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_rd_id_fifo/FSM_onehot_wr_state_q[2]_i_7, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[2].i_axi_serializer/i_wr_id_fifo/FSM_onehot_wr_state_q[2]_i_8, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[1].i_axi_serializer/i_rd_id_fifo/FSM_onehot_wr_state_q[2]_i_9, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_rr_arb_tree/gen_arbiter.gen_int_rr.gen_lock.lock_q_i_2__7, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_axi_shim/gen_arbiter.gen_int_rr.gen_lock.lock_q_i_3__1, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_wr_id_fifo/gen_spill_reg.a_data_q[id][0]_i_2__13, i_cheshire_soc/i_axi_xbar/i_xbar_unmuxed/gen_slv_port_demux[0].i_axi_demux/i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_data_q[id][0]_i_5__3, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[2].i_axi_serializer/i_wr_id_fifo/gen_spill_reg.a_data_q[id][1]_i_3__6, i_cheshire_soc/i_axi_xbar/i_xbar_unmuxed/gen_slv_port_demux[0].i_axi_demux/i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_data_q[id][1]_i_5__7, i_cheshire_soc/i_axi_xbar/i_xbar_unmuxed/gen_slv_port_demux[0].i_axi_demux/i_r_spill_reg/spill_register_flushable_i/state_q[1]_i_3__4, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_dcache_data_fifo/status_cnt_q[2]_i_4__3, i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/gen_cache_wt.i_cache_subsystem/i_adapter/i_dcache_data_fifo/write_pointer_q[1]_i_3__1, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_wr_id_fifo/write_pointer_q[1]_i_4__3, i_cheshire_soc/gen_cva6_cores[0].i_axi_id_serialize/gen_serializers[3].i_axi_serializer/i_wr_id_fifo/write_pointer_q[1]_i_4__4... and (the first 15 of 22 listed).