From 0a35232c8523968444bc8f86ed630d886cfe6525 Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Tue, 7 Nov 2023 09:42:01 +0000
Subject: [PATCH] Implement all vendor intrinsics used by the httparse crate

---
 src/intrinsics/llvm_x86.rs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/intrinsics/llvm_x86.rs b/src/intrinsics/llvm_x86.rs
index 622688fb82c16..6a91ce42fdf6b 100644
--- a/src/intrinsics/llvm_x86.rs
+++ b/src/intrinsics/llvm_x86.rs
@@ -27,6 +27,16 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
             crate::inline_asm::codegen_xgetbv(fx, xcr_no, ret);
         }
 
+        "llvm.x86.sse3.ldu.dq" | "llvm.x86.avx.ldu.dq.256" => {
+            // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lddqu_si128&ig_expand=4009
+            // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lddqu_si256&ig_expand=4010
+            intrinsic_args!(fx, args => (ptr); intrinsic);
+
+            // FIXME correctly handle unalignedness
+            let val = CValue::by_ref(Pointer::new(ptr.load_scalar(fx)), ret.layout());
+            ret.write_cvalue(fx, val);
+        }
+
         "llvm.x86.sse.cmp.ps" | "llvm.x86.sse2.cmp.pd" => {
             let (x, y, kind) = match args {
                 [x, y, kind] => (x, y, kind),