rggen_bus_if.veryl

import  rggen_rtl_pkg::*;

pub interface rggen_bus_if #(
  param ADDRESS_WIDTH:  u32 = 16,
  param BUS_WIDTH:      u32 = 32,
  param STROBE_WIDTH:   u32 = BUS_WIDTH / 8
) {
  var valid:      logic;
  var access:     rggen_access;
  var address:    logic<ADDRESS_WIDTH>;
  var write_data: logic<BUS_WIDTH>;
  var strobe:     logic<STROBE_WIDTH>;
  var ready:      logic;
  var status:     rggen_status;
  var read_data:  logic<BUS_WIDTH>;

  function ack() -> logic {
    return valid && ready;
  }

  modport master {
    valid:      output,
    access:     output,
    address:    output,
    write_data: output,
    strobe:     output,
    ready:      input,
    status:     input,
    read_data:  input,
    ack:        import
  }

  modport slave {
    valid:      input,
    access:     input,
    address:    input,
    write_data: input,
    strobe:     input,
    ready:      output,
    status:     output,
    read_data:  output,
    ack:        import
  }

  modport monitor {
    valid:      input,
    access:     input,
    address:    input,
    write_data: input,
    strobe:     input,
    ready:      input,
    status:     input,
    read_data:  input,
    ack:        import
  }
}