We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Hi, beginner here I'm trying to generate the bitstreams for a nexysA7-100T,, but when I run make i get this error
ERROR: [Vivado 12-172] File or Directory '/home/user/Desktop/pulpissimo/target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/xilinx_clk_mngr.srcs/sources_1/ip/xilinx_clk_mngr/xilinx_clk_mngr.xci' does not exist INFO: [Common 17-206] Exiting Vivado at Mon Nov 25 15:57:52 2024... make[1]: *** [Makefile:14: all] Error 1 make[1]: Leaving directory '/home/user/Desktop/pulpissimo/target/fpga/pulpissimo-nexys' make: *** [target/fpga/Makefile:73: nexys] Error 2
Is there any fix for this? Where can I get these files?
The text was updated successfully, but these errors were encountered:
No branches or pull requests
Hi, beginner here
I'm trying to generate the bitstreams for a nexysA7-100T,, but when I run make i get this error
ERROR: [Vivado 12-172] File or Directory '/home/user/Desktop/pulpissimo/target/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/xilinx_clk_mngr.srcs/sources_1/ip/xilinx_clk_mngr/xilinx_clk_mngr.xci' does not exist
INFO: [Common 17-206] Exiting Vivado at Mon Nov 25 15:57:52 2024...
make[1]: *** [Makefile:14: all] Error 1
make[1]: Leaving directory '/home/user/Desktop/pulpissimo/target/fpga/pulpissimo-nexys'
make: *** [target/fpga/Makefile:73: nexys] Error 2
Is there any fix for this? Where can I get these files?
The text was updated successfully, but these errors were encountered: