From d897c0067dc187505a917f03c10d67c7978028ed Mon Sep 17 00:00:00 2001
From: Philippe Sauter <phsauter@iis.ee.ethz.ch>
Date: Fri, 27 Sep 2024 18:33:38 +0200
Subject: [PATCH] test: optimize testbench for Verilator

---
 Makefile           | 10 ++++++----
 rtl/tb_croc_soc.sv | 23 ++++++++++++++++++-----
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index eb1fab7..34f6d2b 100644
--- a/Makefile
+++ b/Makefile
@@ -11,7 +11,7 @@ MORTY 	  ?= morty
 SVASE 	  ?= svase
 SV2V  	  ?= sv2v
 PYTHON3   ?= python3
-VERILATOR ?= verilator
+VERILATOR ?= /foss/tools/bin/verilator
 VSIM      ?= vsim
 REGGEN    ?= $(PYTHON3) $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 
@@ -89,9 +89,11 @@ verilator/croc.f: Bender.lock Bender.yml
 	$(BENDER) script verilator -t rtl -t verilator -DSYNTHESIS -DVERILATOR > $@
 
 ## Simulate RTL using Verilator
-verilator: verilator/croc.f $(SW)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) --top tb_croc_soc -f croc.f
-	cd verilator; ./obj_dir/Vtb_croc_soc
+verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW)
+	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -CFLAGS "-O0" --top tb_croc_soc -f croc.f
+
+verilator: verilator/obj_dir/Vtb_croc_soc
+	cd verilator; obj_dir/Vtb_croc_soc
 
 .PHONY: verilator vsim vsim-yosys verilator-yosys
 
diff --git a/rtl/tb_croc_soc.sv b/rtl/tb_croc_soc.sv
index 3d331ab..53ffedf 100644
--- a/rtl/tb_croc_soc.sv
+++ b/rtl/tb_croc_soc.sv
@@ -5,6 +5,8 @@
 // Authors:
 // - Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
+//`define TRACE_WAVE
+
 module tb_croc_soc #(
     parameter time         ClkPeriod     = 100ns,
     parameter time         ClkPeriodJtag = 100ns,
@@ -180,6 +182,7 @@ module tb_croc_soc #(
         bit [31:0] data;
         bit [7:0] byte_data;
         int byte_count;
+        dm::sbcs_t sbcs = dm::sbcs_t'{sbautoincrement: 1'b1, sbaccess: 2, default: '0};
 
         file = $fopen(filename, "r");
         if (file == 0) begin
@@ -188,6 +191,9 @@ module tb_croc_soc #(
         end
         end
 
+        $display("@%t | [JTAG] Loading binary from %s", $time, filename);
+        jtag_dbg.write_dmi(dm::SBCS, sbcs);
+
         // line by line
         while (!$feof(file)) begin
             if ($fgets(line, file) == 0) begin
@@ -200,6 +206,8 @@ module tb_croc_soc #(
                 if (status != 1) begin
                     $fatal(1, "Error: Incorrect address line format in file %s", filename);
                 end
+                $display("@%t | [JTAG] Writing to memory @%08x ", $time, addr);
+                jtag_dbg.write_dmi(dm::SBAddress0, addr);
                 continue;
             end
 
@@ -214,7 +222,7 @@ module tb_croc_soc #(
                 end
 
                 // Shift in the byte to the correct position in the data word
-                data = {data[23:0], byte_data}; // Combine bytes into a 32-bit word
+                data = {byte_data, data[31:8]}; // Combine bytes into a 32-bit word
                 byte_count++;
 
                 // remove the byte from the line (2 numbers + 1 space)
@@ -222,13 +230,14 @@ module tb_croc_soc #(
 
                 // write a complete word via jtag
                 if (byte_count == 4) begin
-                    jtag_write_reg32(addr, data, 1'b0);
+                    jtag_write(dm::SBData0, data);
                     addr += 4;
                     data = 32'h0;
                     byte_count = 0;
                 end
             end
         end
+        jtag_dbg.write_dmi(dm::SBCS, JtagInitSbcs);
         $fclose(file);
     endtask
 
@@ -279,8 +288,10 @@ module tb_croc_soc #(
     initial begin
         $timeformat(-9, 0, "ns", 12); // 1: scale (ns=-9), 2: decimals, 3: suffix, 4: print-field width
         // configure VCD dump
-        // $dumpfile("croc.vcd");
-        // $dumpvars(1,i_croc_soc);
+        `ifdef TRACE_WAVE
+        $dumpfile("croc.vcd");
+        $dumpvars(1,i_croc_soc);
+        `endif
 
         uart_rx_i = 1'b0;
         irq0_i    = 1'b0;
@@ -305,7 +316,9 @@ module tb_croc_soc #(
 
         // finish simulation
         repeat(50) @(posedge clk);
-        // $dumpflush;
+        `ifdef TRACE
+        $dumpflush;
+        `endif
         $finish();
     end