From 4e3acb4858bb7b364aeb5b4080b908e7cd449c3a Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 2 Oct 2024 09:59:48 +0200 Subject: [PATCH] ibex: move includes to separate dir --- rtl/ibex/Bender.yml | 8 +- rtl/ibex/ibex_branch_predict.sv | 2 +- rtl/ibex/ibex_compressed_decoder.sv | 2 +- rtl/ibex/ibex_controller.sv | 2 +- rtl/ibex/ibex_core.sv | 2 +- rtl/ibex/ibex_cs_registers.sv | 2 +- rtl/ibex/ibex_csr.sv | 2 +- rtl/ibex/ibex_decoder.sv | 2 +- rtl/ibex/ibex_fetch_fifo.sv | 2 +- rtl/ibex/ibex_icache.sv | 2 +- rtl/ibex/ibex_id_stage.sv | 2 +- rtl/ibex/ibex_if_stage.sv | 2 +- rtl/ibex/ibex_load_store_unit.sv | 2 +- rtl/ibex/ibex_multdiv_fast.sv | 2 +- rtl/ibex/ibex_multdiv_slow.sv | 2 +- rtl/ibex/ibex_wb_stage.sv | 2 +- .../lowrisc_prim/prim_assert.svh} | 4 +- .../lowrisc_prim/prim_assert_dummy_macros.svh | 4 +- .../prim_assert_standard_macros.svh | 4 +- .../lowrisc_prim/prim_assert_yosys_macros.svh | 2 +- rtl/ibex/lowrisc_prim/prim_alert_receiver.sv | 2 +- rtl/ibex/lowrisc_prim/prim_alert_sender.sv | 2 +- rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv | 2 +- rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv | 2 +- rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv | 2 +- rtl/ibex/lowrisc_prim/prim_clock_div.sv | 2 +- rtl/ibex/lowrisc_prim/prim_diff_decode.sv | 2 +- rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv | 2 +- rtl/ibex/lowrisc_prim/prim_edn_req.sv | 2 +- rtl/ibex/lowrisc_prim/prim_esc_receiver.sv | 2 +- rtl/ibex/lowrisc_prim/prim_esc_sender.sv | 2 +- rtl/ibex/lowrisc_prim/prim_fifo_async.sv | 2 +- rtl/ibex/lowrisc_prim/prim_fifo_sync.sv | 2 +- rtl/ibex/lowrisc_prim/prim_gate_gen.sv | 2 +- rtl/ibex/lowrisc_prim/prim_gf_mult.sv | 2 +- rtl/ibex/lowrisc_prim/prim_keccak.sv | 2 +- rtl/ibex/lowrisc_prim/prim_lc_sender.sv | 2 +- rtl/ibex/lowrisc_prim/prim_lc_sync.sv | 2 +- rtl/ibex/lowrisc_prim/prim_lfsr.sv | 2 +- rtl/ibex/lowrisc_prim/prim_multibit_sync.sv | 2 +- rtl/ibex/lowrisc_prim/prim_packer.sv | 2 +- rtl/ibex/lowrisc_prim/prim_packer_fifo.sv | 2 +- rtl/ibex/lowrisc_prim/prim_present.sv | 2 +- rtl/ibex/lowrisc_prim/prim_prince.sv | 2 +- rtl/ibex/lowrisc_prim/prim_ram_1p_adv.sv | 2 +- rtl/ibex/lowrisc_prim/prim_ram_1p_scr.sv | 2 +- rtl/ibex/lowrisc_prim/prim_ram_2p_adv.sv | 2 +- .../lowrisc_prim/prim_ram_2p_async_adv.sv | 2 +- rtl/ibex/lowrisc_prim/prim_rom_adv.sv | 2 +- rtl/ibex/lowrisc_prim/prim_slicer.sv | 2 +- rtl/ibex/lowrisc_prim/prim_sram_arbiter.sv | 2 +- rtl/ibex/lowrisc_prim/prim_sync_reqack.sv | 2 +- .../lowrisc_prim/prim_sync_reqack_data.sv | 2 +- ...3-ibex-move-includes-to-separate-dir.patch | 51 ++ ...1-ibex-move-includes-to-separate-dir.patch | 757 ++++++++++++++++++ ...2-ibex-move-includes-to-separate-dir.patch | 505 ++++++++++++ 56 files changed, 1370 insertions(+), 61 deletions(-) rename rtl/ibex/{lowrisc_prim/prim_assert.sv => include/lowrisc_prim/prim_assert.svh} (99%) rename rtl/ibex/{ => include}/lowrisc_prim/prim_assert_dummy_macros.svh (83%) rename rtl/ibex/{ => include}/lowrisc_prim/prim_assert_standard_macros.svh (93%) rename rtl/ibex/{ => include}/lowrisc_prim/prim_assert_yosys_macros.svh (95%) create mode 100644 rtl/patches/ibex/0003-ibex-move-includes-to-separate-dir.patch create mode 100644 rtl/patches/ibex/lowrisc_prim/0001-ibex-move-includes-to-separate-dir.patch create mode 100644 rtl/patches/ibex/rtl/0002-ibex-move-includes-to-separate-dir.patch diff --git a/rtl/ibex/Bender.yml b/rtl/ibex/Bender.yml index 7155f17..8e923aa 100644 --- a/rtl/ibex/Bender.yml +++ b/rtl/ibex/Bender.yml @@ -13,8 +13,7 @@ sources: - target: not(all(any(test, ibex_include_tracer), not(ibex_exclude_tracer))) include_dirs: - - ./ - - lowrisc_prim + - include/lowrisc_prim files: # Source files grouped in levels. Files in level 0 have no dependencies on files in this @@ -22,7 +21,6 @@ sources: # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 - ibex_pkg.sv - - lowrisc_prim/prim_assert.sv # Level 1 - ibex_alu.sv - ibex_compressed_decoder.sv @@ -50,15 +48,13 @@ sources: # formal interface so the tracer module works (`define RVFI). - target: all(any(test, ibex_include_tracer), not(ibex_exclude_tracer)) include_dirs: - - ./ - - lowrisc_prim + - include/lowrisc_prim defines: RVFI: true files: # Level 0 - ibex_pkg.sv - ibex_register_file_ff.sv - - lowrisc_prim/prim_assert.sv # Level 1 - ibex_alu.sv - ibex_compressed_decoder.sv diff --git a/rtl/ibex/ibex_branch_predict.sv b/rtl/ibex/ibex_branch_predict.sv index 87f8383..3b1387f 100644 --- a/rtl/ibex/ibex_branch_predict.sv +++ b/rtl/ibex/ibex_branch_predict.sv @@ -15,7 +15,7 @@ * The predictor is entirely combinational but takes clk/rst_n signals for use by assertions. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_branch_predict ( input logic clk_i, diff --git a/rtl/ibex/ibex_compressed_decoder.sv b/rtl/ibex/ibex_compressed_decoder.sv index 12a487f..ff7d8a4 100644 --- a/rtl/ibex/ibex_compressed_decoder.sv +++ b/rtl/ibex/ibex_compressed_decoder.sv @@ -11,7 +11,7 @@ * assertions only. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_compressed_decoder ( input logic clk_i, diff --git a/rtl/ibex/ibex_controller.sv b/rtl/ibex/ibex_controller.sv index 77869e9..9a170d7 100644 --- a/rtl/ibex/ibex_controller.sv +++ b/rtl/ibex/ibex_controller.sv @@ -7,7 +7,7 @@ * Main controller of the processor */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_controller #( parameter bit WritebackStage = 0, diff --git a/rtl/ibex/ibex_core.sv b/rtl/ibex/ibex_core.sv index 2858a66..b46e95a 100644 --- a/rtl/ibex/ibex_core.sv +++ b/rtl/ibex/ibex_core.sv @@ -7,7 +7,7 @@ `define RVFI `endif -`include "prim_assert.sv" +`include "prim_assert.svh" /** * Top level module of the ibex RISC-V core diff --git a/rtl/ibex/ibex_cs_registers.sv b/rtl/ibex/ibex_cs_registers.sv index 5c84ef0..10086ff 100644 --- a/rtl/ibex/ibex_cs_registers.sv +++ b/rtl/ibex/ibex_cs_registers.sv @@ -10,7 +10,7 @@ * Specification, draft version 1.11 */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_cs_registers #( parameter bit DbgTriggerEn = 0, diff --git a/rtl/ibex/ibex_csr.sv b/rtl/ibex/ibex_csr.sv index 8623fa5..483e79c 100644 --- a/rtl/ibex/ibex_csr.sv +++ b/rtl/ibex/ibex_csr.sv @@ -6,7 +6,7 @@ * Control / status register primitive */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_csr #( parameter int unsigned Width = 32, diff --git a/rtl/ibex/ibex_decoder.sv b/rtl/ibex/ibex_decoder.sv index b61520e..31490a5 100644 --- a/rtl/ibex/ibex_decoder.sv +++ b/rtl/ibex/ibex_decoder.sv @@ -11,7 +11,7 @@ * assertions only. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_decoder #( parameter bit RV32E = 0, diff --git a/rtl/ibex/ibex_fetch_fifo.sv b/rtl/ibex/ibex_fetch_fifo.sv index 52fcc8e..c914e29 100644 --- a/rtl/ibex/ibex_fetch_fifo.sv +++ b/rtl/ibex/ibex_fetch_fifo.sv @@ -10,7 +10,7 @@ * clear_i clears the FIFO for the following cycle, including any new request */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_fetch_fifo #( parameter int unsigned NUM_REQS = 2 diff --git a/rtl/ibex/ibex_icache.sv b/rtl/ibex/ibex_icache.sv index 346e6a2..7514622 100644 --- a/rtl/ibex/ibex_icache.sv +++ b/rtl/ibex/ibex_icache.sv @@ -8,7 +8,7 @@ * Provides an instruction cache along with cache management, instruction buffering and prefetching */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_icache #( parameter bit BranchPredictor = 1'b0, diff --git a/rtl/ibex/ibex_id_stage.sv b/rtl/ibex/ibex_id_stage.sv index 162ecdf..6a6a7e5 100644 --- a/rtl/ibex/ibex_id_stage.sv +++ b/rtl/ibex/ibex_id_stage.sv @@ -14,7 +14,7 @@ * file. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_id_stage #( parameter bit RV32E = 0, diff --git a/rtl/ibex/ibex_if_stage.sv b/rtl/ibex/ibex_if_stage.sv index 201fb88..cb375f9 100644 --- a/rtl/ibex/ibex_if_stage.sv +++ b/rtl/ibex/ibex_if_stage.sv @@ -10,7 +10,7 @@ * the read instruction. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_if_stage #( parameter int unsigned DmHaltAddr = 32'h1A110800, diff --git a/rtl/ibex/ibex_load_store_unit.sv b/rtl/ibex/ibex_load_store_unit.sv index 4d89b25..c1814be 100644 --- a/rtl/ibex/ibex_load_store_unit.sv +++ b/rtl/ibex/ibex_load_store_unit.sv @@ -11,7 +11,7 @@ * and to align bytes and halfwords. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_load_store_unit ( diff --git a/rtl/ibex/ibex_multdiv_fast.sv b/rtl/ibex/ibex_multdiv_fast.sv index cf69f00..5c1e739 100644 --- a/rtl/ibex/ibex_multdiv_fast.sv +++ b/rtl/ibex/ibex_multdiv_fast.sv @@ -12,7 +12,7 @@ * 16x16 kernel multiplier and Long Division */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_multdiv_fast #( parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast diff --git a/rtl/ibex/ibex_multdiv_slow.sv b/rtl/ibex/ibex_multdiv_slow.sv index a8d60b4..366f11a 100644 --- a/rtl/ibex/ibex_multdiv_slow.sv +++ b/rtl/ibex/ibex_multdiv_slow.sv @@ -9,7 +9,7 @@ * Baugh-Wooley multiplier and Long Division */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_multdiv_slow ( diff --git a/rtl/ibex/ibex_wb_stage.sv b/rtl/ibex/ibex_wb_stage.sv index 7299ad1..b51923a 100644 --- a/rtl/ibex/ibex_wb_stage.sv +++ b/rtl/ibex/ibex_wb_stage.sv @@ -11,7 +11,7 @@ * a simple passthrough to write data direct to the register file. */ -`include "prim_assert.sv" +`include "prim_assert.svh" module ibex_wb_stage #( parameter bit WritebackStage = 1'b0 diff --git a/rtl/ibex/lowrisc_prim/prim_assert.sv b/rtl/ibex/include/lowrisc_prim/prim_assert.svh similarity index 99% rename from rtl/ibex/lowrisc_prim/prim_assert.sv rename to rtl/ibex/include/lowrisc_prim/prim_assert.svh index 1e484e5..8b945c3 100644 --- a/rtl/ibex/lowrisc_prim/prim_assert.sv +++ b/rtl/ibex/include/lowrisc_prim/prim_assert.svh @@ -6,8 +6,8 @@ // - Provides default clk and rst options to simplify code // - Provides boiler plate template for common assertions -`ifndef PRIM_ASSERT_SV -`define PRIM_ASSERT_SV +`ifndef PRIM_ASSERT_SVH +`define PRIM_ASSERT_SVH /////////////////// // Helper macros // diff --git a/rtl/ibex/lowrisc_prim/prim_assert_dummy_macros.svh b/rtl/ibex/include/lowrisc_prim/prim_assert_dummy_macros.svh similarity index 83% rename from rtl/ibex/lowrisc_prim/prim_assert_dummy_macros.svh rename to rtl/ibex/include/lowrisc_prim/prim_assert_dummy_macros.svh index 4a0da70..6479abf 100644 --- a/rtl/ibex/lowrisc_prim/prim_assert_dummy_macros.svh +++ b/rtl/ibex/include/lowrisc_prim/prim_assert_dummy_macros.svh @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Macro bodies included by prim_assert.sv for tools that don't support assertions. See -// prim_assert.sv for documentation for each of the macros. +// Macro bodies included by prim_assert.svhh for tools that don't support assertions. See +// prim_assert.svh for documentation for each of the macros. `define ASSERT_I(__name, __prop) `define ASSERT_INIT(__name, __prop) diff --git a/rtl/ibex/lowrisc_prim/prim_assert_standard_macros.svh b/rtl/ibex/include/lowrisc_prim/prim_assert_standard_macros.svh similarity index 93% rename from rtl/ibex/lowrisc_prim/prim_assert_standard_macros.svh rename to rtl/ibex/include/lowrisc_prim/prim_assert_standard_macros.svh index b6f3e98..6a2d297 100644 --- a/rtl/ibex/lowrisc_prim/prim_assert_standard_macros.svh +++ b/rtl/ibex/include/lowrisc_prim/prim_assert_standard_macros.svh @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Macro bodies included by prim_assert.sv for tools that support full SystemVerilog and SVA syntax. -// See prim_assert.sv for documentation for each of the macros. +// Macro bodies included by prim_assert.svhh for tools that support full SystemVerilog and SVA syntax. +// See prim_assert.svh for documentation for each of the macros. `define ASSERT_I(__name, __prop) \ __name: assert (__prop) \ diff --git a/rtl/ibex/lowrisc_prim/prim_assert_yosys_macros.svh b/rtl/ibex/include/lowrisc_prim/prim_assert_yosys_macros.svh similarity index 95% rename from rtl/ibex/lowrisc_prim/prim_assert_yosys_macros.svh rename to rtl/ibex/include/lowrisc_prim/prim_assert_yosys_macros.svh index f007e70..e943a1d 100644 --- a/rtl/ibex/lowrisc_prim/prim_assert_yosys_macros.svh +++ b/rtl/ibex/include/lowrisc_prim/prim_assert_yosys_macros.svh @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Macro bodies included by prim_assert.sv for formal verification with Yosys. See prim_assert.sv +// Macro bodies included by prim_assert.svhh for formal verification with Yosys. See prim_assert.svh // for documentation for each of the macros. `define ASSERT_I(__name, __prop) \ diff --git a/rtl/ibex/lowrisc_prim/prim_alert_receiver.sv b/rtl/ibex/lowrisc_prim/prim_alert_receiver.sv index bfc1baf..6aa6137 100644 --- a/rtl/ibex/lowrisc_prim/prim_alert_receiver.sv +++ b/rtl/ibex/lowrisc_prim/prim_alert_receiver.sv @@ -27,7 +27,7 @@ // // See also: prim_alert_sender, prim_diff_decode, alert_handler -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_alert_receiver import prim_alert_pkg::*; diff --git a/rtl/ibex/lowrisc_prim/prim_alert_sender.sv b/rtl/ibex/lowrisc_prim/prim_alert_sender.sv index 9898ff6..d5cfc02 100644 --- a/rtl/ibex/lowrisc_prim/prim_alert_sender.sv +++ b/rtl/ibex/lowrisc_prim/prim_alert_sender.sv @@ -28,7 +28,7 @@ // // See also: prim_alert_receiver, prim_diff_decode, alert_handler -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_alert_sender import prim_alert_pkg::*; diff --git a/rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv b/rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv index d9677dd..c853949 100644 --- a/rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv +++ b/rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv @@ -11,7 +11,7 @@ // // See also: prim_arbiter_ppc, prim_arbiter_tree -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_arbiter_fixed #( parameter int N = 8, diff --git a/rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv b/rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv index 152015e..6afc9c3 100644 --- a/rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv +++ b/rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv @@ -23,7 +23,7 @@ // // See also: prim_arbiter_tree -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_arbiter_ppc #( parameter int unsigned N = 8, diff --git a/rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv b/rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv index 992bc2f..7eb554d 100644 --- a/rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv +++ b/rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv @@ -30,7 +30,7 @@ // // See also: prim_arbiter_ppc -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_arbiter_tree #( parameter int N = 8, diff --git a/rtl/ibex/lowrisc_prim/prim_clock_div.sv b/rtl/ibex/lowrisc_prim/prim_clock_div.sv index 35dbbba..af0384e 100644 --- a/rtl/ibex/lowrisc_prim/prim_clock_div.sv +++ b/rtl/ibex/lowrisc_prim/prim_clock_div.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_clock_div #( parameter int Divisor = 2, diff --git a/rtl/ibex/lowrisc_prim/prim_diff_decode.sv b/rtl/ibex/lowrisc_prim/prim_diff_decode.sv index c06a77d..dba5e23 100644 --- a/rtl/ibex/lowrisc_prim/prim_diff_decode.sv +++ b/rtl/ibex/lowrisc_prim/prim_diff_decode.sv @@ -15,7 +15,7 @@ // // See also: prim_alert_sender, prim_alert_receiver, alert_handler -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_diff_decode #( // enables additional synchronization logic diff --git a/rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv b/rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv index ec2f001..8879550 100644 --- a/rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv +++ b/rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv @@ -23,7 +23,7 @@ // Q1 = t{1,1} + sig(j>1,1)(...) + sig(j<1,1)(t{1,j} + Z{j}) // = a1&b1 + (0 + a1&b0 + z0) -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_dom_and_2share #( parameter int DW = 64, // Input width diff --git a/rtl/ibex/lowrisc_prim/prim_edn_req.sv b/rtl/ibex/lowrisc_prim/prim_edn_req.sv index 75cae9d..1bb36be 100644 --- a/rtl/ibex/lowrisc_prim/prim_edn_req.sv +++ b/rtl/ibex/lowrisc_prim/prim_edn_req.sv @@ -11,7 +11,7 @@ // requests. // -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_edn_req import prim_alert_pkg::*; diff --git a/rtl/ibex/lowrisc_prim/prim_esc_receiver.sv b/rtl/ibex/lowrisc_prim/prim_esc_receiver.sv index 2ffe702..7421c2f 100644 --- a/rtl/ibex/lowrisc_prim/prim_esc_receiver.sv +++ b/rtl/ibex/lowrisc_prim/prim_esc_receiver.sv @@ -16,7 +16,7 @@ // // See also: prim_esc_sender, prim_diff_decode, alert_handler -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_esc_receiver import prim_esc_pkg::*; diff --git a/rtl/ibex/lowrisc_prim/prim_esc_sender.sv b/rtl/ibex/lowrisc_prim/prim_esc_sender.sv index a738420..c6d31bf 100644 --- a/rtl/ibex/lowrisc_prim/prim_esc_sender.sv +++ b/rtl/ibex/lowrisc_prim/prim_esc_sender.sv @@ -19,7 +19,7 @@ // // See also: prim_esc_receiver, prim_diff_decode, alert_handler -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_esc_sender import prim_esc_pkg::*; diff --git a/rtl/ibex/lowrisc_prim/prim_fifo_async.sv b/rtl/ibex/lowrisc_prim/prim_fifo_async.sv index 3a7e8c1..c292fac 100644 --- a/rtl/ibex/lowrisc_prim/prim_fifo_async.sv +++ b/rtl/ibex/lowrisc_prim/prim_fifo_async.sv @@ -4,7 +4,7 @@ // // Generic asynchronous fifo for use in a variety of devices. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_fifo_async #( parameter int unsigned Width = 16, diff --git a/rtl/ibex/lowrisc_prim/prim_fifo_sync.sv b/rtl/ibex/lowrisc_prim/prim_fifo_sync.sv index af559ac..26f5739 100644 --- a/rtl/ibex/lowrisc_prim/prim_fifo_sync.sv +++ b/rtl/ibex/lowrisc_prim/prim_fifo_sync.sv @@ -4,7 +4,7 @@ // // Generic synchronous fifo for use in a variety of devices. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_fifo_sync #( parameter int unsigned Width = 16, diff --git a/rtl/ibex/lowrisc_prim/prim_gate_gen.sv b/rtl/ibex/lowrisc_prim/prim_gate_gen.sv index dac761f..1f2889d 100644 --- a/rtl/ibex/lowrisc_prim/prim_gate_gen.sv +++ b/rtl/ibex/lowrisc_prim/prim_gate_gen.sv @@ -31,7 +31,7 @@ // If valid_i constantly set to 1'b1, the gate generator produces around 2.5% smaller designs for // the configurations listed in the table above. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_gate_gen #( parameter int DataWidth = 32, parameter int NumGates = 1000 diff --git a/rtl/ibex/lowrisc_prim/prim_gf_mult.sv b/rtl/ibex/lowrisc_prim/prim_gf_mult.sv index 61e7594..83adb8c 100644 --- a/rtl/ibex/lowrisc_prim/prim_gf_mult.sv +++ b/rtl/ibex/lowrisc_prim/prim_gf_mult.sv @@ -24,7 +24,7 @@ // https://ieeexplore.ieee.org/document/542803 -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_gf_mult #( parameter int Width = 32, diff --git a/rtl/ibex/lowrisc_prim/prim_keccak.sv b/rtl/ibex/lowrisc_prim/prim_keccak.sv index 7d4e0ae..8b134ea 100644 --- a/rtl/ibex/lowrisc_prim/prim_keccak.sv +++ b/rtl/ibex/lowrisc_prim/prim_keccak.sv @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 // // prim_keccak is single round permutation module -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_keccak #( parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} diff --git a/rtl/ibex/lowrisc_prim/prim_lc_sender.sv b/rtl/ibex/lowrisc_prim/prim_lc_sender.sv index d8e5a02..f594f6c 100644 --- a/rtl/ibex/lowrisc_prim/prim_lc_sender.sv +++ b/rtl/ibex/lowrisc_prim/prim_lc_sender.sv @@ -8,7 +8,7 @@ // for each bit in the life cycle control signal such that tools do not // optimize the multibit encoding. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_lc_sender ( input clk_i, diff --git a/rtl/ibex/lowrisc_prim/prim_lc_sync.sv b/rtl/ibex/lowrisc_prim/prim_lc_sync.sv index 951a130..f019adb 100644 --- a/rtl/ibex/lowrisc_prim/prim_lc_sync.sv +++ b/rtl/ibex/lowrisc_prim/prim_lc_sync.sv @@ -8,7 +8,7 @@ // Should be used exactly as recommended in the life cycle controller spec: // https://docs.opentitan.org/hw/ip/lc_ctrl/doc/index.html#control-signal-propagation -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_lc_sync #( // Number of separately buffered output signals. diff --git a/rtl/ibex/lowrisc_prim/prim_lfsr.sv b/rtl/ibex/lowrisc_prim/prim_lfsr.sv index b78f4b8..dc42fd7 100644 --- a/rtl/ibex/lowrisc_prim/prim_lfsr.sv +++ b/rtl/ibex/lowrisc_prim/prim_lfsr.sv @@ -24,7 +24,7 @@ // [2] https://users.ece.cmu.edu/~koopman/lfsr/ // [3] https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_lfsr #( // Lfsr Type, can be FIB_XNOR or GAL_XOR diff --git a/rtl/ibex/lowrisc_prim/prim_multibit_sync.sv b/rtl/ibex/lowrisc_prim/prim_multibit_sync.sv index e9addde..1b79d82 100644 --- a/rtl/ibex/lowrisc_prim/prim_multibit_sync.sv +++ b/rtl/ibex/lowrisc_prim/prim_multibit_sync.sv @@ -35,7 +35,7 @@ // Note: CDC tools will likely flag this module due to re-convergent logic. // -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_multibit_sync #( // Width of the multibit signal. diff --git a/rtl/ibex/lowrisc_prim/prim_packer.sv b/rtl/ibex/lowrisc_prim/prim_packer.sv index 4fd2628..25e8bf0 100644 --- a/rtl/ibex/lowrisc_prim/prim_packer.sv +++ b/rtl/ibex/lowrisc_prim/prim_packer.sv @@ -4,7 +4,7 @@ // // Combine InW data and write to OutW data if packed to full word or stop signal -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_packer #( parameter int InW = 32, diff --git a/rtl/ibex/lowrisc_prim/prim_packer_fifo.sv b/rtl/ibex/lowrisc_prim/prim_packer_fifo.sv index f76f779..e1cda8c 100755 --- a/rtl/ibex/lowrisc_prim/prim_packer_fifo.sv +++ b/rtl/ibex/lowrisc_prim/prim_packer_fifo.sv @@ -39,7 +39,7 @@ // depth_o 0000000000|1111111111|00000000000000000000000000000000000000000 -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_packer_fifo #( parameter int InW = 32, diff --git a/rtl/ibex/lowrisc_prim/prim_present.sv b/rtl/ibex/lowrisc_prim/prim_present.sv index 52adb3b..1b8f0d3 100644 --- a/rtl/ibex/lowrisc_prim/prim_present.sv +++ b/rtl/ibex/lowrisc_prim/prim_present.sv @@ -21,7 +21,7 @@ // - https://csrc.nist.gov/csrc/media/events/lightweight-cryptography-workshop-2015/ // documents/papers/session7-maene-paper.pdf -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_present #( parameter int DataWidth = 64, // {32, 64} parameter int KeyWidth = 128, // {64, 80, 128} diff --git a/rtl/ibex/lowrisc_prim/prim_prince.sv b/rtl/ibex/lowrisc_prim/prim_prince.sv index 97b075d..b2d400e 100644 --- a/rtl/ibex/lowrisc_prim/prim_prince.sv +++ b/rtl/ibex/lowrisc_prim/prim_prince.sv @@ -22,7 +22,7 @@ // - https://eprint.iacr.org/2015/372.pdf // - https://eprint.iacr.org/2014/656.pdf -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_prince #( parameter int DataWidth = 64, parameter int KeyWidth = 128, diff --git a/rtl/ibex/lowrisc_prim/prim_ram_1p_adv.sv b/rtl/ibex/lowrisc_prim/prim_ram_1p_adv.sv index 072cfb1..2109678 100644 --- a/rtl/ibex/lowrisc_prim/prim_ram_1p_adv.sv +++ b/rtl/ibex/lowrisc_prim/prim_ram_1p_adv.sv @@ -13,7 +13,7 @@ // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write // mask cannot be used and has to be tied to {Width{1'b1}}. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_ram_1p_adv #( parameter int Depth = 512, diff --git a/rtl/ibex/lowrisc_prim/prim_ram_1p_scr.sv b/rtl/ibex/lowrisc_prim/prim_ram_1p_scr.sv index 57ce7e8..4a7e149 100644 --- a/rtl/ibex/lowrisc_prim/prim_ram_1p_scr.sv +++ b/rtl/ibex/lowrisc_prim/prim_ram_1p_scr.sv @@ -21,7 +21,7 @@ // // See also: prim_cipher_pkg, prim_prince -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_ram_1p_scr #( parameter int Depth = 16*1024, // Needs to be a power of 2 if NumAddrScrRounds > 0. diff --git a/rtl/ibex/lowrisc_prim/prim_ram_2p_adv.sv b/rtl/ibex/lowrisc_prim/prim_ram_2p_adv.sv index 278a7a8..d1e2144 100644 --- a/rtl/ibex/lowrisc_prim/prim_ram_2p_adv.sv +++ b/rtl/ibex/lowrisc_prim/prim_ram_2p_adv.sv @@ -13,7 +13,7 @@ // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write // mask cannot be used and has to be tied to {Width{1'b1}}. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_ram_2p_adv #( parameter int Depth = 512, diff --git a/rtl/ibex/lowrisc_prim/prim_ram_2p_async_adv.sv b/rtl/ibex/lowrisc_prim/prim_ram_2p_async_adv.sv index 3c8721a..78e1a28 100644 --- a/rtl/ibex/lowrisc_prim/prim_ram_2p_async_adv.sv +++ b/rtl/ibex/lowrisc_prim/prim_ram_2p_async_adv.sv @@ -13,7 +13,7 @@ // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write // mask cannot be used and has to be tied to {Width{1'b1}}. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_ram_2p_async_adv #( parameter int Depth = 512, diff --git a/rtl/ibex/lowrisc_prim/prim_rom_adv.sv b/rtl/ibex/lowrisc_prim/prim_rom_adv.sv index b0c26ce..cfcdc96 100644 --- a/rtl/ibex/lowrisc_prim/prim_rom_adv.sv +++ b/rtl/ibex/lowrisc_prim/prim_rom_adv.sv @@ -4,7 +4,7 @@ // // ROM wrapper with rvalid register -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_rom_adv #( // Parameters passed on the the ROM primitive. diff --git a/rtl/ibex/lowrisc_prim/prim_slicer.sv b/rtl/ibex/lowrisc_prim/prim_slicer.sv index 3c61669..5ac0246 100644 --- a/rtl/ibex/lowrisc_prim/prim_slicer.sv +++ b/rtl/ibex/lowrisc_prim/prim_slicer.sv @@ -5,7 +5,7 @@ // Slicer chops the incoming bitstring into OutW granularity. // It supports fractional InW/OutW which fills 0 at the end of message. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_slicer #( parameter int InW = 64, diff --git a/rtl/ibex/lowrisc_prim/prim_sram_arbiter.sv b/rtl/ibex/lowrisc_prim/prim_sram_arbiter.sv index bd80349..cfaae98 100644 --- a/rtl/ibex/lowrisc_prim/prim_sram_arbiter.sv +++ b/rtl/ibex/lowrisc_prim/prim_sram_arbiter.sv @@ -9,7 +9,7 @@ // DW: Data width (SECDED is not included) // Aw: Address width // ArbiterImpl: can be either PPC or BINTREE. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_sram_arbiter #( parameter int N = 4, diff --git a/rtl/ibex/lowrisc_prim/prim_sync_reqack.sv b/rtl/ibex/lowrisc_prim/prim_sync_reqack.sv index 808630b..c24801f 100644 --- a/rtl/ibex/lowrisc_prim/prim_sync_reqack.sv +++ b/rtl/ibex/lowrisc_prim/prim_sync_reqack.sv @@ -22,7 +22,7 @@ // REQ is starting to be propagated to the destination side. The module is thus not suitable // for high-bandwidth communication. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_sync_reqack ( input clk_src_i, // REQ side, SRC domain diff --git a/rtl/ibex/lowrisc_prim/prim_sync_reqack_data.sv b/rtl/ibex/lowrisc_prim/prim_sync_reqack_data.sv index 9919d51..e417038 100644 --- a/rtl/ibex/lowrisc_prim/prim_sync_reqack_data.sv +++ b/rtl/ibex/lowrisc_prim/prim_sync_reqack_data.sv @@ -14,7 +14,7 @@ // Under the hood, this module uses a prim_sync_reqack primitive for synchronizing the // REQ/ACK handshake. See prim_sync_reqack.sv for more details. -`include "prim_assert.sv" +`include "prim_assert.svh" module prim_sync_reqack_data #( parameter int unsigned Width = 1, diff --git a/rtl/patches/ibex/0003-ibex-move-includes-to-separate-dir.patch b/rtl/patches/ibex/0003-ibex-move-includes-to-separate-dir.patch new file mode 100644 index 0000000..349c36a --- /dev/null +++ b/rtl/patches/ibex/0003-ibex-move-includes-to-separate-dir.patch @@ -0,0 +1,51 @@ +From 07de45efb7e6fcbd20b943da6453bfe67ef51516 Mon Sep 17 00:00:00 2001 +From: Philippe Sauter +Date: Wed, 2 Oct 2024 09:58:32 +0200 +Subject: [PATCH] ibex: move includes to separate dir + +--- + Bender.yml | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/Bender.yml b/Bender.yml +index 7155f17d..8e923aad 100644 +--- a/Bender.yml ++++ b/Bender.yml +@@ -13,8 +13,7 @@ sources: + + - target: not(all(any(test, ibex_include_tracer), not(ibex_exclude_tracer))) + include_dirs: +- - ./ +- - lowrisc_prim ++ - include/lowrisc_prim + + files: + # Source files grouped in levels. Files in level 0 have no dependencies on files in this +@@ -22,7 +21,6 @@ sources: + # levels 1 and 0, etc. Files within a level are ordered alphabetically. + # Level 0 + - ibex_pkg.sv +- - lowrisc_prim/prim_assert.sv + # Level 1 + - ibex_alu.sv + - ibex_compressed_decoder.sv +@@ -50,15 +48,13 @@ sources: + # formal interface so the tracer module works (`define RVFI). + - target: all(any(test, ibex_include_tracer), not(ibex_exclude_tracer)) + include_dirs: +- - ./ +- - lowrisc_prim ++ - include/lowrisc_prim + defines: + RVFI: true + files: + # Level 0 + - ibex_pkg.sv + - ibex_register_file_ff.sv +- - lowrisc_prim/prim_assert.sv + # Level 1 + - ibex_alu.sv + - ibex_compressed_decoder.sv +-- +2.25.1 + diff --git a/rtl/patches/ibex/lowrisc_prim/0001-ibex-move-includes-to-separate-dir.patch b/rtl/patches/ibex/lowrisc_prim/0001-ibex-move-includes-to-separate-dir.patch new file mode 100644 index 0000000..7bc785e --- /dev/null +++ b/rtl/patches/ibex/lowrisc_prim/0001-ibex-move-includes-to-separate-dir.patch @@ -0,0 +1,757 @@ +From 2611c0d2fd4430d554303d6eba752aa6d0f0cd18 Mon Sep 17 00:00:00 2001 +From: Philippe Sauter +Date: Wed, 2 Oct 2024 09:58:46 +0200 +Subject: [PATCH] ibex: move includes to separate dir + +--- + prim_alert_receiver.sv | 2 +- + prim_alert_sender.sv | 2 +- + prim_arbiter_fixed.sv | 2 +- + prim_arbiter_ppc.sv | 2 +- + prim_arbiter_tree.sv | 2 +- + prim_assert.sv | 131 -------------------------------- + prim_assert_dummy_macros.svh | 16 ---- + prim_assert_standard_macros.svh | 58 -------------- + prim_assert_yosys_macros.svh | 47 ------------ + prim_clock_div.sv | 2 +- + prim_diff_decode.sv | 2 +- + prim_dom_and_2share.sv | 2 +- + prim_edn_req.sv | 2 +- + prim_esc_receiver.sv | 2 +- + prim_esc_sender.sv | 2 +- + prim_fifo_async.sv | 2 +- + prim_fifo_sync.sv | 2 +- + prim_gate_gen.sv | 2 +- + prim_gf_mult.sv | 2 +- + prim_keccak.sv | 2 +- + prim_lc_sender.sv | 2 +- + prim_lc_sync.sv | 2 +- + prim_lfsr.sv | 2 +- + prim_multibit_sync.sv | 2 +- + prim_packer.sv | 2 +- + prim_packer_fifo.sv | 2 +- + prim_present.sv | 2 +- + prim_prince.sv | 2 +- + prim_ram_1p_adv.sv | 2 +- + prim_ram_1p_scr.sv | 2 +- + prim_ram_2p_adv.sv | 2 +- + prim_ram_2p_async_adv.sv | 2 +- + prim_rom_adv.sv | 2 +- + prim_slicer.sv | 2 +- + prim_sram_arbiter.sv | 2 +- + prim_sync_reqack.sv | 2 +- + prim_sync_reqack_data.sv | 2 +- + 37 files changed, 33 insertions(+), 285 deletions(-) + delete mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv + delete mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_assert_dummy_macros.svh + delete mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_assert_standard_macros.svh + delete mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_assert_yosys_macros.svh + +diff --git a/prim_alert_receiver.sv b/prim_alert_receiver.sv +index bfc1baf0..6aa61377 100644 +--- a/prim_alert_receiver.sv ++++ b/prim_alert_receiver.sv +@@ -27,7 +27,7 @@ + // + // See also: prim_alert_sender, prim_diff_decode, alert_handler + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_alert_receiver + import prim_alert_pkg::*; +diff --git a/prim_alert_sender.sv b/prim_alert_sender.sv +index 9898ff6e..d5cfc02c 100644 +--- a/prim_alert_sender.sv ++++ b/prim_alert_sender.sv +@@ -28,7 +28,7 @@ + // + // See also: prim_alert_receiver, prim_diff_decode, alert_handler + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_alert_sender + import prim_alert_pkg::*; +diff --git a/prim_arbiter_fixed.sv b/prim_arbiter_fixed.sv +index d9677dd2..c853949e 100644 +--- a/prim_arbiter_fixed.sv ++++ b/prim_arbiter_fixed.sv +@@ -11,7 +11,7 @@ + // + // See also: prim_arbiter_ppc, prim_arbiter_tree + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_arbiter_fixed #( + parameter int N = 8, +diff --git a/prim_arbiter_ppc.sv b/prim_arbiter_ppc.sv +index 152015eb..6afc9c31 100644 +--- a/prim_arbiter_ppc.sv ++++ b/prim_arbiter_ppc.sv +@@ -23,7 +23,7 @@ + // + // See also: prim_arbiter_tree + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_arbiter_ppc #( + parameter int unsigned N = 8, +diff --git a/prim_arbiter_tree.sv b/prim_arbiter_tree.sv +index 992bc2ff..7eb554d2 100644 +--- a/prim_arbiter_tree.sv ++++ b/prim_arbiter_tree.sv +@@ -30,7 +30,7 @@ + // + // See also: prim_arbiter_ppc + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_arbiter_tree #( + parameter int N = 8, +diff --git a/prim_assert.sv b/prim_assert.sv +deleted file mode 100644 +index 1e484e50..00000000 +--- a/prim_assert.sv ++++ /dev/null +@@ -1,131 +0,0 @@ +-// Copyright lowRISC contributors. +-// Licensed under the Apache License, Version 2.0, see LICENSE for details. +-// SPDX-License-Identifier: Apache-2.0 +- +-// Macros and helper code for using assertions. +-// - Provides default clk and rst options to simplify code +-// - Provides boiler plate template for common assertions +- +-`ifndef PRIM_ASSERT_SV +-`define PRIM_ASSERT_SV +- +-/////////////////// +-// Helper macros // +-/////////////////// +- +-// Default clk and reset signals used by assertion macros below. +-`define ASSERT_DEFAULT_CLK clk_i +-`define ASSERT_DEFAULT_RST !rst_ni +- +-// Converts an arbitrary block of code into a Verilog string +-`define PRIM_STRINGIFY(__x) `"__x`" +- +-// ASSERT_ERROR logs an error message with either `uvm_error or with $error. +-// +-// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason +-// for redefining it here is to avoid creating a dependency. +-`define ASSERT_ERROR(__name) \ +-`ifdef UVM \ +- uvm_pkg::uvm_report_error("ASSERT FAILED", `PRIM_STRINGIFY(__name), uvm_pkg::UVM_NONE, \ +- `__FILE__, `__LINE__, "", 1); \ +-`else \ +- $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, \ +- `PRIM_STRINGIFY(__name)); \ +-`endif +- +-// The basic helper macros are actually defined in "implementation headers". The macros should do +-// the same thing in each case (except for the dummy flavour), but in a way that the respective +-// tools support. +-// +-// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to +-// hide signal definitions that are only used for assertions). +-// +-// The list of basic macros supported is: +-// +-// ASSERT_I: Immediate assertion. Note that immediate assertions are sensitive to simulation +-// glitches. +-// +-// ASSERT_INIT: Assertion in initial block. Can be used for things like parameter checking. +-// +-// ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of +-// sim, all credits returned at end of sim, state machines in idle at end of sim. +-// +-// ASSERT: Assert a concurrent property directly. It can be called as a module (or +-// interface) body item. +-// +-// Note: We use (__rst !== '0) in the disable iff statements instead of (__rst == +-// '1). This properly disables the assertion in cases when reset is X at the +-// beginning of a simulation. For that case, (reset == '1) does not disable the +-// assertion. +-// +-// ASSERT_NEVER: Assert a concurrent property NEVER happens +-// +-// ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset. +-// It can be called as a module (or interface) body item. +-// +-// COVER: Cover a concurrent property +-// +-// ASSUME: Assume a concurrent property +-// +-// ASSUME_I: Assume an immediate property +- +-`ifdef VERILATOR +- `include "prim_assert_dummy_macros.svh" +-`elsif SYNTHESIS +- `include "prim_assert_dummy_macros.svh" +-`elsif YOSYS +- `include "prim_assert_yosys_macros.svh" +- `define INC_ASSERT +-`else +- `include "prim_assert_standard_macros.svh" +- `define INC_ASSERT +-`endif +- +-////////////////////////////// +-// Complex assertion macros // +-////////////////////////////// +- +-// Assert that signal is an active-high pulse with pulse length of 1 clock cycle +-`define ASSERT_PULSE(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- `ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst) +- +-// Assert that a property is true only when an enable signal is set. It can be called as a module +-// (or interface) body item. +-`define ASSERT_IF(__name, __prop, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- `ASSERT(__name, (__enable) |-> (__prop), __clk, __rst) +- +-// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is +-// set. It can be called as a module (or interface) body item. +-`define ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- `ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst) \ +- `ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst) +- +-////////////////////////////////// +-// For formal verification only // +-////////////////////////////////// +- +-// Note that the existing set of ASSERT macros specified above shall be used for FPV, +-// thereby ensuring that the assertions are evaluated during DV simulations as well. +- +-// ASSUME_FPV +-// Assume a concurrent property during formal verification only. +-`define ASSUME_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +-`ifdef FPV_ON \ +- `ASSUME(__name, __prop, __clk, __rst) \ +-`endif +- +-// ASSUME_I_FPV +-// Assume a concurrent property during formal verification only. +-`define ASSUME_I_FPV(__name, __prop) \ +-`ifdef FPV_ON \ +- `ASSUME_I(__name, __prop) \ +-`endif +- +-// COVER_FPV +-// Cover a concurrent property during formal verification +-`define COVER_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +-`ifdef FPV_ON \ +- `COVER(__name, __prop, __clk, __rst) \ +-`endif +- +-`endif // PRIM_ASSERT_SV +diff --git a/prim_assert_dummy_macros.svh b/prim_assert_dummy_macros.svh +deleted file mode 100644 +index 4a0da703..00000000 +--- a/prim_assert_dummy_macros.svh ++++ /dev/null +@@ -1,16 +0,0 @@ +-// Copyright lowRISC contributors. +-// Licensed under the Apache License, Version 2.0, see LICENSE for details. +-// SPDX-License-Identifier: Apache-2.0 +- +-// Macro bodies included by prim_assert.sv for tools that don't support assertions. See +-// prim_assert.sv for documentation for each of the macros. +- +-`define ASSERT_I(__name, __prop) +-`define ASSERT_INIT(__name, __prop) +-`define ASSERT_FINAL(__name, __prop) +-`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +-`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +-`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +-`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +-`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +-`define ASSUME_I(__name, __prop) +diff --git a/prim_assert_standard_macros.svh b/prim_assert_standard_macros.svh +deleted file mode 100644 +index b6f3e980..00000000 +--- a/prim_assert_standard_macros.svh ++++ /dev/null +@@ -1,58 +0,0 @@ +-// Copyright lowRISC contributors. +-// Licensed under the Apache License, Version 2.0, see LICENSE for details. +-// SPDX-License-Identifier: Apache-2.0 +- +-// Macro bodies included by prim_assert.sv for tools that support full SystemVerilog and SVA syntax. +-// See prim_assert.sv for documentation for each of the macros. +- +-`define ASSERT_I(__name, __prop) \ +- __name: assert (__prop) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end +- +-`define ASSERT_INIT(__name, __prop) \ +- initial begin \ +- __name: assert (__prop) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end \ +- end +- +-`define ASSERT_FINAL(__name, __prop) \ +- final begin \ +- __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end \ +- end +- +-`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end +- +-`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop)) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end +- +-`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- `ASSERT(__name, !$isunknown(__sig), __clk, __rst) +- +-`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- __name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)); +- +-`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- __name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end +- +-`define ASSUME_I(__name, __prop) \ +- __name: assume (__prop) \ +- else begin \ +- `ASSERT_ERROR(__name) \ +- end +diff --git a/prim_assert_yosys_macros.svh b/prim_assert_yosys_macros.svh +deleted file mode 100644 +index f007e702..00000000 +--- a/prim_assert_yosys_macros.svh ++++ /dev/null +@@ -1,47 +0,0 @@ +-// Copyright lowRISC contributors. +-// Licensed under the Apache License, Version 2.0, see LICENSE for details. +-// SPDX-License-Identifier: Apache-2.0 +- +-// Macro bodies included by prim_assert.sv for formal verification with Yosys. See prim_assert.sv +-// for documentation for each of the macros. +- +-`define ASSERT_I(__name, __prop) \ +- always_comb begin : __name \ +- assert (__prop); \ +- end +- +-`define ASSERT_INIT(__name, __prop) \ +- initial begin : __name \ +- assert (__prop); \ +- end +- +-// This doesn't make much sense for a formal tool (we never get to the final block!) +-`define ASSERT_FINAL(__name, __prop) +- +-`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- always_ff @(posedge __clk) begin \ +- if (! (__rst !== '0)) __name: assert (__prop); \ +- end +- +-`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- always_ff @(posedge __clk) begin \ +- if (! (__rst !== '0)) __name: assert (! (__prop)); \ +- end +- +-// Yosys uses 2-state logic, so this doesn't make sense here +-`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +- +-`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- always_ff @(posedge __clk) begin : __name \ +- cover ((! (__rst !== '0)) && (__prop)); \ +- end +- +-`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +- always_ff @(posedge __clk) begin \ +- if (! (__rst !== '0)) __name: assume (__prop); \ +- end +- +-`define ASSUME_I(__name, __prop) \ +- always_comb begin : __name \ +- assume (__prop); \ +- end +diff --git a/prim_clock_div.sv b/prim_clock_div.sv +index 35dbbba7..af0384e1 100644 +--- a/prim_clock_div.sv ++++ b/prim_clock_div.sv +@@ -2,7 +2,7 @@ + // Licensed under the Apache License, Version 2.0, see LICENSE for details. + // SPDX-License-Identifier: Apache-2.0 + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_clock_div #( + parameter int Divisor = 2, +diff --git a/prim_diff_decode.sv b/prim_diff_decode.sv +index c06a77d7..dba5e236 100644 +--- a/prim_diff_decode.sv ++++ b/prim_diff_decode.sv +@@ -15,7 +15,7 @@ + // + // See also: prim_alert_sender, prim_alert_receiver, alert_handler + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_diff_decode #( + // enables additional synchronization logic +diff --git a/prim_dom_and_2share.sv b/prim_dom_and_2share.sv +index ec2f0019..88795506 100644 +--- a/prim_dom_and_2share.sv ++++ b/prim_dom_and_2share.sv +@@ -23,7 +23,7 @@ + // Q1 = t{1,1} + sig(j>1,1)(...) + sig(j<1,1)(t{1,j} + Z{j}) + // = a1&b1 + (0 + a1&b0 + z0) + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_dom_and_2share #( + parameter int DW = 64, // Input width +diff --git a/prim_edn_req.sv b/prim_edn_req.sv +index 75cae9d0..1bb36be7 100644 +--- a/prim_edn_req.sv ++++ b/prim_edn_req.sv +@@ -11,7 +11,7 @@ + // requests. + // + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_edn_req + import prim_alert_pkg::*; +diff --git a/prim_esc_receiver.sv b/prim_esc_receiver.sv +index 2ffe702c..7421c2ff 100644 +--- a/prim_esc_receiver.sv ++++ b/prim_esc_receiver.sv +@@ -16,7 +16,7 @@ + // + // See also: prim_esc_sender, prim_diff_decode, alert_handler + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_esc_receiver + import prim_esc_pkg::*; +diff --git a/prim_esc_sender.sv b/prim_esc_sender.sv +index a7384206..c6d31bf8 100644 +--- a/prim_esc_sender.sv ++++ b/prim_esc_sender.sv +@@ -19,7 +19,7 @@ + // + // See also: prim_esc_receiver, prim_diff_decode, alert_handler + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_esc_sender + import prim_esc_pkg::*; +diff --git a/prim_fifo_async.sv b/prim_fifo_async.sv +index 3a7e8c15..c292facc 100644 +--- a/prim_fifo_async.sv ++++ b/prim_fifo_async.sv +@@ -4,7 +4,7 @@ + // + // Generic asynchronous fifo for use in a variety of devices. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_fifo_async #( + parameter int unsigned Width = 16, +diff --git a/prim_fifo_sync.sv b/prim_fifo_sync.sv +index af559ace..26f57392 100644 +--- a/prim_fifo_sync.sv ++++ b/prim_fifo_sync.sv +@@ -4,7 +4,7 @@ + // + // Generic synchronous fifo for use in a variety of devices. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_fifo_sync #( + parameter int unsigned Width = 16, +diff --git a/prim_gate_gen.sv b/prim_gate_gen.sv +index dac761fd..1f2889d0 100644 +--- a/prim_gate_gen.sv ++++ b/prim_gate_gen.sv +@@ -31,7 +31,7 @@ + // If valid_i constantly set to 1'b1, the gate generator produces around 2.5% smaller designs for + // the configurations listed in the table above. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + module prim_gate_gen #( + parameter int DataWidth = 32, + parameter int NumGates = 1000 +diff --git a/prim_gf_mult.sv b/prim_gf_mult.sv +index 61e75949..83adb8c4 100644 +--- a/prim_gf_mult.sv ++++ b/prim_gf_mult.sv +@@ -24,7 +24,7 @@ + // https://ieeexplore.ieee.org/document/542803 + + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_gf_mult #( + parameter int Width = 32, +diff --git a/prim_keccak.sv b/prim_keccak.sv +index 7d4e0ae7..8b134ea0 100644 +--- a/prim_keccak.sv ++++ b/prim_keccak.sv +@@ -3,7 +3,7 @@ + // SPDX-License-Identifier: Apache-2.0 + // + // prim_keccak is single round permutation module +-`include "prim_assert.sv" ++`include "prim_assert.svh" + module prim_keccak #( + parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} + +diff --git a/prim_lc_sender.sv b/prim_lc_sender.sv +index d8e5a02b..f594f6cf 100644 +--- a/prim_lc_sender.sv ++++ b/prim_lc_sender.sv +@@ -8,7 +8,7 @@ + // for each bit in the life cycle control signal such that tools do not + // optimize the multibit encoding. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_lc_sender ( + input clk_i, +diff --git a/prim_lc_sync.sv b/prim_lc_sync.sv +index 951a130f..f019adb8 100644 +--- a/prim_lc_sync.sv ++++ b/prim_lc_sync.sv +@@ -8,7 +8,7 @@ + // Should be used exactly as recommended in the life cycle controller spec: + // https://docs.opentitan.org/hw/ip/lc_ctrl/doc/index.html#control-signal-propagation + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_lc_sync #( + // Number of separately buffered output signals. +diff --git a/prim_lfsr.sv b/prim_lfsr.sv +index b78f4b8c..dc42fd71 100644 +--- a/prim_lfsr.sv ++++ b/prim_lfsr.sv +@@ -24,7 +24,7 @@ + // [2] https://users.ece.cmu.edu/~koopman/lfsr/ + // [3] https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_lfsr #( + // Lfsr Type, can be FIB_XNOR or GAL_XOR +diff --git a/prim_multibit_sync.sv b/prim_multibit_sync.sv +index e9adddea..1b79d82c 100644 +--- a/prim_multibit_sync.sv ++++ b/prim_multibit_sync.sv +@@ -35,7 +35,7 @@ + // Note: CDC tools will likely flag this module due to re-convergent logic. + // + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_multibit_sync #( + // Width of the multibit signal. +diff --git a/prim_packer.sv b/prim_packer.sv +index 4fd26289..25e8bf09 100644 +--- a/prim_packer.sv ++++ b/prim_packer.sv +@@ -4,7 +4,7 @@ + // + // Combine InW data and write to OutW data if packed to full word or stop signal + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_packer #( + parameter int InW = 32, +diff --git a/prim_packer_fifo.sv b/prim_packer_fifo.sv +index f76f779e..e1cda8c9 100755 +--- a/prim_packer_fifo.sv ++++ b/prim_packer_fifo.sv +@@ -39,7 +39,7 @@ + // depth_o 0000000000|1111111111|00000000000000000000000000000000000000000 + + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_packer_fifo #( + parameter int InW = 32, +diff --git a/prim_present.sv b/prim_present.sv +index 52adb3b8..1b8f0d3a 100644 +--- a/prim_present.sv ++++ b/prim_present.sv +@@ -21,7 +21,7 @@ + // - https://csrc.nist.gov/csrc/media/events/lightweight-cryptography-workshop-2015/ + // documents/papers/session7-maene-paper.pdf + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + module prim_present #( + parameter int DataWidth = 64, // {32, 64} + parameter int KeyWidth = 128, // {64, 80, 128} +diff --git a/prim_prince.sv b/prim_prince.sv +index 97b075d5..b2d400ec 100644 +--- a/prim_prince.sv ++++ b/prim_prince.sv +@@ -22,7 +22,7 @@ + // - https://eprint.iacr.org/2015/372.pdf + // - https://eprint.iacr.org/2014/656.pdf + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + module prim_prince #( + parameter int DataWidth = 64, + parameter int KeyWidth = 128, +diff --git a/prim_ram_1p_adv.sv b/prim_ram_1p_adv.sv +index 072cfb10..21096783 100644 +--- a/prim_ram_1p_adv.sv ++++ b/prim_ram_1p_adv.sv +@@ -13,7 +13,7 @@ + // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write + // mask cannot be used and has to be tied to {Width{1'b1}}. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_ram_1p_adv #( + parameter int Depth = 512, +diff --git a/prim_ram_1p_scr.sv b/prim_ram_1p_scr.sv +index 57ce7e8b..4a7e1490 100644 +--- a/prim_ram_1p_scr.sv ++++ b/prim_ram_1p_scr.sv +@@ -21,7 +21,7 @@ + // + // See also: prim_cipher_pkg, prim_prince + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_ram_1p_scr #( + parameter int Depth = 16*1024, // Needs to be a power of 2 if NumAddrScrRounds > 0. +diff --git a/prim_ram_2p_adv.sv b/prim_ram_2p_adv.sv +index 278a7a8f..d1e21443 100644 +--- a/prim_ram_2p_adv.sv ++++ b/prim_ram_2p_adv.sv +@@ -13,7 +13,7 @@ + // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write + // mask cannot be used and has to be tied to {Width{1'b1}}. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_ram_2p_adv #( + parameter int Depth = 512, +diff --git a/prim_ram_2p_async_adv.sv b/prim_ram_2p_async_adv.sv +index 3c8721ac..78e1a280 100644 +--- a/prim_ram_2p_async_adv.sv ++++ b/prim_ram_2p_async_adv.sv +@@ -13,7 +13,7 @@ + // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write + // mask cannot be used and has to be tied to {Width{1'b1}}. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_ram_2p_async_adv #( + parameter int Depth = 512, +diff --git a/prim_rom_adv.sv b/prim_rom_adv.sv +index b0c26ce1..cfcdc961 100644 +--- a/prim_rom_adv.sv ++++ b/prim_rom_adv.sv +@@ -4,7 +4,7 @@ + // + // ROM wrapper with rvalid register + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_rom_adv #( + // Parameters passed on the the ROM primitive. +diff --git a/prim_slicer.sv b/prim_slicer.sv +index 3c61669e..5ac02461 100644 +--- a/prim_slicer.sv ++++ b/prim_slicer.sv +@@ -5,7 +5,7 @@ + // Slicer chops the incoming bitstring into OutW granularity. + // It supports fractional InW/OutW which fills 0 at the end of message. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_slicer #( + parameter int InW = 64, +diff --git a/prim_sram_arbiter.sv b/prim_sram_arbiter.sv +index bd803496..cfaae983 100644 +--- a/prim_sram_arbiter.sv ++++ b/prim_sram_arbiter.sv +@@ -9,7 +9,7 @@ + // DW: Data width (SECDED is not included) + // Aw: Address width + // ArbiterImpl: can be either PPC or BINTREE. +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_sram_arbiter #( + parameter int N = 4, +diff --git a/prim_sync_reqack.sv b/prim_sync_reqack.sv +index 808630b4..c24801f8 100644 +--- a/prim_sync_reqack.sv ++++ b/prim_sync_reqack.sv +@@ -22,7 +22,7 @@ + // REQ is starting to be propagated to the destination side. The module is thus not suitable + // for high-bandwidth communication. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_sync_reqack ( + input clk_src_i, // REQ side, SRC domain +diff --git a/prim_sync_reqack_data.sv b/prim_sync_reqack_data.sv +index 9919d519..e4170381 100644 +--- a/prim_sync_reqack_data.sv ++++ b/prim_sync_reqack_data.sv +@@ -14,7 +14,7 @@ + // Under the hood, this module uses a prim_sync_reqack primitive for synchronizing the + // REQ/ACK handshake. See prim_sync_reqack.sv for more details. + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module prim_sync_reqack_data #( + parameter int unsigned Width = 1, +-- +2.25.1 + diff --git a/rtl/patches/ibex/rtl/0002-ibex-move-includes-to-separate-dir.patch b/rtl/patches/ibex/rtl/0002-ibex-move-includes-to-separate-dir.patch new file mode 100644 index 0000000..c31cc7c --- /dev/null +++ b/rtl/patches/ibex/rtl/0002-ibex-move-includes-to-separate-dir.patch @@ -0,0 +1,505 @@ +From 125f0399684dd78950ee062016451afb4aff837a Mon Sep 17 00:00:00 2001 +From: Philippe Sauter +Date: Wed, 2 Oct 2024 09:59:04 +0200 +Subject: [PATCH] ibex: move includes to separate dir + +--- + ibex_branch_predict.sv | 2 +- + ibex_compressed_decoder.sv | 2 +- + ibex_controller.sv | 2 +- + ibex_core.sv | 2 +- + ibex_cs_registers.sv | 2 +- + ibex_csr.sv | 2 +- + ibex_decoder.sv | 2 +- + ibex_fetch_fifo.sv | 2 +- + ibex_icache.sv | 2 +- + ibex_id_stage.sv | 2 +- + ibex_if_stage.sv | 2 +- + ibex_load_store_unit.sv | 2 +- + ibex_multdiv_fast.sv | 2 +- + ibex_multdiv_slow.sv | 2 +- + ibex_wb_stage.sv | 2 +- + include/lowrisc_prim/prim_assert.svh | 131 ++++++++++++++++++ + .../lowrisc_prim/prim_assert_dummy_macros.svh | 16 +++ + .../prim_assert_standard_macros.svh | 58 ++++++++ + .../lowrisc_prim/prim_assert_yosys_macros.svh | 47 +++++++ + 19 files changed, 267 insertions(+), 15 deletions(-) + create mode 100644 rtl/include/lowrisc_prim/prim_assert.svh + create mode 100644 rtl/include/lowrisc_prim/prim_assert_dummy_macros.svh + create mode 100644 rtl/include/lowrisc_prim/prim_assert_standard_macros.svh + create mode 100644 rtl/include/lowrisc_prim/prim_assert_yosys_macros.svh + +diff --git a/ibex_branch_predict.sv b/ibex_branch_predict.sv +index 87f83836..3b1387fb 100644 +--- a/ibex_branch_predict.sv ++++ b/ibex_branch_predict.sv +@@ -15,7 +15,7 @@ + * The predictor is entirely combinational but takes clk/rst_n signals for use by assertions. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_branch_predict ( + input logic clk_i, +diff --git a/ibex_compressed_decoder.sv b/ibex_compressed_decoder.sv +index 12a487fe..ff7d8a41 100644 +--- a/ibex_compressed_decoder.sv ++++ b/ibex_compressed_decoder.sv +@@ -11,7 +11,7 @@ + * assertions only. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_compressed_decoder ( + input logic clk_i, +diff --git a/ibex_controller.sv b/ibex_controller.sv +index 77869e98..9a170d70 100644 +--- a/ibex_controller.sv ++++ b/ibex_controller.sv +@@ -7,7 +7,7 @@ + * Main controller of the processor + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_controller #( + parameter bit WritebackStage = 0, +diff --git a/ibex_core.sv b/ibex_core.sv +index 2858a66c..b46e95a6 100644 +--- a/ibex_core.sv ++++ b/ibex_core.sv +@@ -7,7 +7,7 @@ + `define RVFI + `endif + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + /** + * Top level module of the ibex RISC-V core +diff --git a/ibex_cs_registers.sv b/ibex_cs_registers.sv +index 5c84ef03..10086ff9 100644 +--- a/ibex_cs_registers.sv ++++ b/ibex_cs_registers.sv +@@ -10,7 +10,7 @@ + * Specification, draft version 1.11 + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_cs_registers #( + parameter bit DbgTriggerEn = 0, +diff --git a/ibex_csr.sv b/ibex_csr.sv +index 8623fa55..483e79c1 100644 +--- a/ibex_csr.sv ++++ b/ibex_csr.sv +@@ -6,7 +6,7 @@ + * Control / status register primitive + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_csr #( + parameter int unsigned Width = 32, +diff --git a/ibex_decoder.sv b/ibex_decoder.sv +index b61520ed..31490a5c 100644 +--- a/ibex_decoder.sv ++++ b/ibex_decoder.sv +@@ -11,7 +11,7 @@ + * assertions only. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_decoder #( + parameter bit RV32E = 0, +diff --git a/ibex_fetch_fifo.sv b/ibex_fetch_fifo.sv +index 52fcc8ea..c914e29c 100644 +--- a/ibex_fetch_fifo.sv ++++ b/ibex_fetch_fifo.sv +@@ -10,7 +10,7 @@ + * clear_i clears the FIFO for the following cycle, including any new request + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_fetch_fifo #( + parameter int unsigned NUM_REQS = 2 +diff --git a/ibex_icache.sv b/ibex_icache.sv +index 346e6a28..75146228 100644 +--- a/ibex_icache.sv ++++ b/ibex_icache.sv +@@ -8,7 +8,7 @@ + * Provides an instruction cache along with cache management, instruction buffering and prefetching + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_icache #( + parameter bit BranchPredictor = 1'b0, +diff --git a/ibex_id_stage.sv b/ibex_id_stage.sv +index 162ecdf3..6a6a7e5a 100644 +--- a/ibex_id_stage.sv ++++ b/ibex_id_stage.sv +@@ -14,7 +14,7 @@ + * file. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_id_stage #( + parameter bit RV32E = 0, +diff --git a/ibex_if_stage.sv b/ibex_if_stage.sv +index 201fb884..cb375f9e 100644 +--- a/ibex_if_stage.sv ++++ b/ibex_if_stage.sv +@@ -10,7 +10,7 @@ + * the read instruction. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_if_stage #( + parameter int unsigned DmHaltAddr = 32'h1A110800, +diff --git a/ibex_load_store_unit.sv b/ibex_load_store_unit.sv +index 4d89b257..c1814be8 100644 +--- a/ibex_load_store_unit.sv ++++ b/ibex_load_store_unit.sv +@@ -11,7 +11,7 @@ + * and to align bytes and halfwords. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_load_store_unit + ( +diff --git a/ibex_multdiv_fast.sv b/ibex_multdiv_fast.sv +index cf69f005..5c1e7398 100644 +--- a/ibex_multdiv_fast.sv ++++ b/ibex_multdiv_fast.sv +@@ -12,7 +12,7 @@ + * 16x16 kernel multiplier and Long Division + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_multdiv_fast #( + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast +diff --git a/ibex_multdiv_slow.sv b/ibex_multdiv_slow.sv +index a8d60b4e..366f11a6 100644 +--- a/ibex_multdiv_slow.sv ++++ b/ibex_multdiv_slow.sv +@@ -9,7 +9,7 @@ + * Baugh-Wooley multiplier and Long Division + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_multdiv_slow + ( +diff --git a/ibex_wb_stage.sv b/ibex_wb_stage.sv +index 7299ad11..b51923a5 100644 +--- a/ibex_wb_stage.sv ++++ b/ibex_wb_stage.sv +@@ -11,7 +11,7 @@ + * a simple passthrough to write data direct to the register file. + */ + +-`include "prim_assert.sv" ++`include "prim_assert.svh" + + module ibex_wb_stage #( + parameter bit WritebackStage = 1'b0 +diff --git a/include/lowrisc_prim/prim_assert.svh b/include/lowrisc_prim/prim_assert.svh +new file mode 100644 +index 00000000..8b945c34 +--- /dev/null ++++ b/include/lowrisc_prim/prim_assert.svh +@@ -0,0 +1,131 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// Macros and helper code for using assertions. ++// - Provides default clk and rst options to simplify code ++// - Provides boiler plate template for common assertions ++ ++`ifndef PRIM_ASSERT_SVH ++`define PRIM_ASSERT_SVH ++ ++/////////////////// ++// Helper macros // ++/////////////////// ++ ++// Default clk and reset signals used by assertion macros below. ++`define ASSERT_DEFAULT_CLK clk_i ++`define ASSERT_DEFAULT_RST !rst_ni ++ ++// Converts an arbitrary block of code into a Verilog string ++`define PRIM_STRINGIFY(__x) `"__x`" ++ ++// ASSERT_ERROR logs an error message with either `uvm_error or with $error. ++// ++// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason ++// for redefining it here is to avoid creating a dependency. ++`define ASSERT_ERROR(__name) \ ++`ifdef UVM \ ++ uvm_pkg::uvm_report_error("ASSERT FAILED", `PRIM_STRINGIFY(__name), uvm_pkg::UVM_NONE, \ ++ `__FILE__, `__LINE__, "", 1); \ ++`else \ ++ $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, \ ++ `PRIM_STRINGIFY(__name)); \ ++`endif ++ ++// The basic helper macros are actually defined in "implementation headers". The macros should do ++// the same thing in each case (except for the dummy flavour), but in a way that the respective ++// tools support. ++// ++// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to ++// hide signal definitions that are only used for assertions). ++// ++// The list of basic macros supported is: ++// ++// ASSERT_I: Immediate assertion. Note that immediate assertions are sensitive to simulation ++// glitches. ++// ++// ASSERT_INIT: Assertion in initial block. Can be used for things like parameter checking. ++// ++// ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of ++// sim, all credits returned at end of sim, state machines in idle at end of sim. ++// ++// ASSERT: Assert a concurrent property directly. It can be called as a module (or ++// interface) body item. ++// ++// Note: We use (__rst !== '0) in the disable iff statements instead of (__rst == ++// '1). This properly disables the assertion in cases when reset is X at the ++// beginning of a simulation. For that case, (reset == '1) does not disable the ++// assertion. ++// ++// ASSERT_NEVER: Assert a concurrent property NEVER happens ++// ++// ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset. ++// It can be called as a module (or interface) body item. ++// ++// COVER: Cover a concurrent property ++// ++// ASSUME: Assume a concurrent property ++// ++// ASSUME_I: Assume an immediate property ++ ++`ifdef VERILATOR ++ `include "prim_assert_dummy_macros.svh" ++`elsif SYNTHESIS ++ `include "prim_assert_dummy_macros.svh" ++`elsif YOSYS ++ `include "prim_assert_yosys_macros.svh" ++ `define INC_ASSERT ++`else ++ `include "prim_assert_standard_macros.svh" ++ `define INC_ASSERT ++`endif ++ ++////////////////////////////// ++// Complex assertion macros // ++////////////////////////////// ++ ++// Assert that signal is an active-high pulse with pulse length of 1 clock cycle ++`define ASSERT_PULSE(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ `ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst) ++ ++// Assert that a property is true only when an enable signal is set. It can be called as a module ++// (or interface) body item. ++`define ASSERT_IF(__name, __prop, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ `ASSERT(__name, (__enable) |-> (__prop), __clk, __rst) ++ ++// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is ++// set. It can be called as a module (or interface) body item. ++`define ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ `ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst) \ ++ `ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst) ++ ++////////////////////////////////// ++// For formal verification only // ++////////////////////////////////// ++ ++// Note that the existing set of ASSERT macros specified above shall be used for FPV, ++// thereby ensuring that the assertions are evaluated during DV simulations as well. ++ ++// ASSUME_FPV ++// Assume a concurrent property during formal verification only. ++`define ASSUME_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++`ifdef FPV_ON \ ++ `ASSUME(__name, __prop, __clk, __rst) \ ++`endif ++ ++// ASSUME_I_FPV ++// Assume a concurrent property during formal verification only. ++`define ASSUME_I_FPV(__name, __prop) \ ++`ifdef FPV_ON \ ++ `ASSUME_I(__name, __prop) \ ++`endif ++ ++// COVER_FPV ++// Cover a concurrent property during formal verification ++`define COVER_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++`ifdef FPV_ON \ ++ `COVER(__name, __prop, __clk, __rst) \ ++`endif ++ ++`endif // PRIM_ASSERT_SV +diff --git a/include/lowrisc_prim/prim_assert_dummy_macros.svh b/include/lowrisc_prim/prim_assert_dummy_macros.svh +new file mode 100644 +index 00000000..6479abf8 +--- /dev/null ++++ b/include/lowrisc_prim/prim_assert_dummy_macros.svh +@@ -0,0 +1,16 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// Macro bodies included by prim_assert.svhh for tools that don't support assertions. See ++// prim_assert.svh for documentation for each of the macros. ++ ++`define ASSERT_I(__name, __prop) ++`define ASSERT_INIT(__name, __prop) ++`define ASSERT_FINAL(__name, __prop) ++`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) ++`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) ++`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) ++`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) ++`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) ++`define ASSUME_I(__name, __prop) +diff --git a/include/lowrisc_prim/prim_assert_standard_macros.svh b/include/lowrisc_prim/prim_assert_standard_macros.svh +new file mode 100644 +index 00000000..6a2d2977 +--- /dev/null ++++ b/include/lowrisc_prim/prim_assert_standard_macros.svh +@@ -0,0 +1,58 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// Macro bodies included by prim_assert.svhh for tools that support full SystemVerilog and SVA syntax. ++// See prim_assert.svh for documentation for each of the macros. ++ ++`define ASSERT_I(__name, __prop) \ ++ __name: assert (__prop) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end ++ ++`define ASSERT_INIT(__name, __prop) \ ++ initial begin \ ++ __name: assert (__prop) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end \ ++ end ++ ++`define ASSERT_FINAL(__name, __prop) \ ++ final begin \ ++ __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end \ ++ end ++ ++`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end ++ ++`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop)) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end ++ ++`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ `ASSERT(__name, !$isunknown(__sig), __clk, __rst) ++ ++`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ __name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)); ++ ++`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ __name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end ++ ++`define ASSUME_I(__name, __prop) \ ++ __name: assume (__prop) \ ++ else begin \ ++ `ASSERT_ERROR(__name) \ ++ end +diff --git a/include/lowrisc_prim/prim_assert_yosys_macros.svh b/include/lowrisc_prim/prim_assert_yosys_macros.svh +new file mode 100644 +index 00000000..e943a1de +--- /dev/null ++++ b/include/lowrisc_prim/prim_assert_yosys_macros.svh +@@ -0,0 +1,47 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// Macro bodies included by prim_assert.svhh for formal verification with Yosys. See prim_assert.svh ++// for documentation for each of the macros. ++ ++`define ASSERT_I(__name, __prop) \ ++ always_comb begin : __name \ ++ assert (__prop); \ ++ end ++ ++`define ASSERT_INIT(__name, __prop) \ ++ initial begin : __name \ ++ assert (__prop); \ ++ end ++ ++// This doesn't make much sense for a formal tool (we never get to the final block!) ++`define ASSERT_FINAL(__name, __prop) ++ ++`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ always_ff @(posedge __clk) begin \ ++ if (! (__rst !== '0)) __name: assert (__prop); \ ++ end ++ ++`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ always_ff @(posedge __clk) begin \ ++ if (! (__rst !== '0)) __name: assert (! (__prop)); \ ++ end ++ ++// Yosys uses 2-state logic, so this doesn't make sense here ++`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) ++ ++`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ always_ff @(posedge __clk) begin : __name \ ++ cover ((! (__rst !== '0)) && (__prop)); \ ++ end ++ ++`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ ++ always_ff @(posedge __clk) begin \ ++ if (! (__rst !== '0)) __name: assume (__prop); \ ++ end ++ ++`define ASSUME_I(__name, __prop) \ ++ always_comb begin : __name \ ++ assume (__prop); \ ++ end +-- +2.25.1 +