From 79e1419e0f0f39ac89d7c44f61bc4a13f1a9260d Mon Sep 17 00:00:00 2001 From: Alessandro Ottaviano Date: Tue, 5 Mar 2024 14:27:37 +0100 Subject: [PATCH] target/sim: Add JTAG tasks for reg access and preloading (#103) * target/sim: Add JTAG tasks to read/write 32b registers * target/sim: Add JTAG task to halt and load binary Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. * target/sim: Clean up added tasks --------- Co-authored-by: Paul Scheffler --- target/sim/src/vip_cheshire_soc.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index c5cfab20..cfdc05f4 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -261,7 +261,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #( input doub_bt addr, output word_bt data, input int unsigned idle_cycles = 20 - ); automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0}; jtag_write(dm::SBCS, sbcs, 0, 1);