From 4635eb4f2dbeb38dcfa4a868b758ffb8701940df Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 28 Feb 2024 16:36:04 +0100 Subject: [PATCH] deps: Update `cva6` to pulp-v1.0.0 (#99) * deps: Update `cva6` to pulp-v1.0.0 Signed-off-by: Nils Wistoff * Bender.yml: Point to new release tag Signed-off-by: Nils Wistoff * cheshire_pkg: Make CVA6 CLIC support optional Signed-off-by: Nils Wistoff * cheshire_pkg: Remap CVA6 accelerator to free AXI ID Signed-off-by: Nils Wistoff --------- Signed-off-by: Nils Wistoff --- Bender.lock | 2 +- Bender.yml | 2 +- hw/cheshire_pkg.sv | 84 ++++++++++++++++++------ hw/cheshire_soc.sv | 21 +++--- target/xilinx/src/cheshire_top_xilinx.sv | 6 +- 5 files changed, 78 insertions(+), 37 deletions(-) diff --git a/Bender.lock b/Bender.lock index b418983c..3166ff8d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -92,7 +92,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: a34c7aa3fa0e02f0fc3578558df71b2992ad0bb1 + revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5 version: null source: Git: https://github.com/pulp-platform/cva6.git diff --git a/Bender.yml b/Bender.yml index 71ca4a1d..c460f28f 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,7 +22,7 @@ dependencies: clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v0.4.3 } + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 } iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index bf052dba..867bf981 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -430,9 +430,9 @@ package cheshire_pkg; // CVA6 // //////////// - // CVA6 imposes an ID width of 4, but only 6 of 16 IDs are ever used + // CVA6 imposes an ID width of 4, but only 7 of 16 IDs are ever used localparam int unsigned Cva6IdWidth = 4; - localparam int unsigned Cva6IdsUsed = 6; + localparam int unsigned Cva6IdsUsed = 7; typedef logic [Cva6IdWidth-1:0] cva6_id_t; typedef int unsigned cva6_id_map_t [Cva6IdsUsed-1:0][0:1]; @@ -440,38 +440,84 @@ package cheshire_pkg; typedef enum cva6_id_t { Cva6IdBypMmu = 'b1000, Cva6IdBypLoad = 'b1001, - Cva6IdBypStore = 'b1010, - Cva6IdBypAmo = 'b1011, + Cva6IdBypAccel = 'b1010, + Cva6IdBypStore = 'b1011, + Cva6IdBypAmo = 'b1100, Cva6IdICache = 'b0000, - Cva6IdDCache = 'b1100 + Cva6IdDCache = 'b0111 } cva6_id_e; // Choose static colocation of IDs based on how heavily used and/or critical they are function automatic cva6_id_map_t gen_cva6_id_map(cheshire_cfg_t cfg); case (cfg.AxiMstIdWidth) // Provide exclusive ID to I-cache to prevent fetch blocking - 1: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 0}, '{Cva6IdBypStore, 0}, + 1: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 0}, '{Cva6IdBypAccel, 0}, '{Cva6IdBypStore, 0}, '{Cva6IdBypAmo, 0}, '{Cva6IdICache, 1}, '{Cva6IdDCache, 0}}; // Colocate Load/Store and MMU/AMO bypasses, respectively - 2: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 1}, '{Cva6IdBypStore, 1}, + 2: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 1}, '{Cva6IdBypAccel, 1}, '{Cva6IdBypStore, 1}, '{Cva6IdBypAmo, 0}, '{Cva6IdICache, 2}, '{Cva6IdDCache, 3}}; // Compress output ID space without any serialization - 3: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 1}, '{Cva6IdBypStore, 2}, + 3: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 1}, '{Cva6IdBypAccel, 6}, '{Cva6IdBypStore, 2}, '{Cva6IdBypAmo, 3}, '{Cva6IdICache, 4}, '{Cva6IdDCache, 5}}; // With 4b of ID or more, no remapping is necessary default: return '{default: '{0, 0}}; endcase endfunction - function automatic ariane_pkg::ariane_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg); + function automatic config_pkg::cva6_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg); doub_bt SizeSpm = get_llc_size(cfg); doub_bt SizeLlcOut = cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart; doub_bt CieBase = cfg.Cva6ExtCieOnTop ? 64'h8000_0000 - cfg.Cva6ExtCieLength : 64'h2000_0000; doub_bt NoCieBase = cfg.Cva6ExtCieOnTop ? 64'h2000_0000 : 64'h2000_0000 + cfg.Cva6ExtCieLength; - return ariane_pkg::ariane_cfg_t'{ + return config_pkg::cva6_cfg_t'{ + NrCommitPorts : 2, + AxiAddrWidth : cfg.AddrWidth, + AxiDataWidth : cfg.AxiDataWidth, + AxiIdWidth : Cva6IdWidth, + AxiUserWidth : cfg.AxiUserWidth, + NrLoadBufEntries : 2, + FpuEn : 1, + XF16 : 0, + XF16ALT : 0, + XF8 : 0, + XF8ALT : 1, + RVA : 1, + RVB : 0, + RVV : 0, + RVC : 1, + RVH : 1, + RVZCB : 1, + XFVec : 0, + CvxifEn : 0, + ZiCondExtEn : 1, + RVSCLIC : cfg.Clic, + RVF : 1, + RVD : 1, + FpPresent : 1, + NSX : 0, + FLen : 64, + RVFVec : 0, + XF16Vec : 0, + XF16ALTVec : 0, + XF8Vec : 0, + NrRgprPorts : 0, + NrWbPorts : 0, + EnableAccelerator : 0, + RVS : 1, + RVU : 1, + HaltAddress : AmDbg + 'h800, + ExceptionAddress : AmDbg + 'h808, RASDepth : cfg.Cva6RASDepth, BTBEntries : cfg.Cva6BTBEntries, BHTEntries : cfg.Cva6BHTEntries, + DmBaseAddress : AmDbg, + TvalEn : 1, + NrPMPEntries : cfg.Cva6NrPMPEntries, + PMPCfgRstVal : {16{64'h0}}, + PMPAddrRstVal : {16{64'h0}}, + PMPEntryReadOnly : 16'd0, + NOCType : config_pkg::NOC_TYPE_AXI4_ATOP, + CLICNumInterruptSrc : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs, NrNonIdempotentRules : 2, // Periphs, ExtNonCIE NonIdempotentAddrBase : {64'h0000_0000, NoCieBase}, NonIdempotentLength : {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength}, @@ -481,12 +527,10 @@ package cheshire_pkg; NrCachedRegionRules : 3, // CachedSPM, LLCOut, ExtCIE CachedRegionAddrBase : {AmSpm, cfg.LlcOutRegionStart, CieBase}, CachedRegionLength : {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength}, - AxiCompliant : 1, - SwapEndianess : 0, - CLICNumInterruptSrc : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs, - CLICIntCtlBits : cfg.ClicIntCtlBits, - DmBaseAddress : AmDbg, - NrPMPEntries : cfg.Cva6NrPMPEntries + MaxOutstandingStores : 7, + DebugEn : 1, + NonIdemPotenceEn : 0, + AxiBurstWriteEn : 0 }; endfunction @@ -501,9 +545,9 @@ package cheshire_pkg; localparam cheshire_cfg_t DefaultCfg = '{ // CVA6 parameters - Cva6RASDepth : ariane_pkg::ArianeDefaultConfig.RASDepth, - Cva6BTBEntries : ariane_pkg::ArianeDefaultConfig.BTBEntries, - Cva6BHTEntries : ariane_pkg::ArianeDefaultConfig.BHTEntries, + Cva6RASDepth : 2, + Cva6BTBEntries : 32, + Cva6BHTEntries : 128, Cva6NrPMPEntries : 0, Cva6ExtCieLength : 'h2000_0000, // [0x2.., 0x4..) is CIE, [0x4.., 0x8..) is non-CIE Cva6ExtCieOnTop : 0, @@ -517,7 +561,7 @@ package cheshire_pkg; NumExtClicIntrs : NumExtPlicIntrs, NumExtOutIntrTgts : 0, NumExtOutIntrs : 0, - ClicIntCtlBits : ariane_pkg::ArianeDefaultConfig.CLICIntCtlBits, + ClicIntCtlBits : 8, NumExtIntrSyncs : 2, // Interconnect AddrWidth : 48, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 807d524d..f6ba75ee 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -548,7 +548,7 @@ module cheshire_soc import cheshire_pkg::*; #( `CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t) - localparam ariane_pkg::ariane_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg); + localparam config_pkg::cva6_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg); // Boot from boot ROM only if available, otherwise from platform ROM localparam logic [63:0] BootAddr = 64'(Cfg.Bootrom ? AmBrom : Cfg.PlatformRom); @@ -590,15 +590,14 @@ module cheshire_soc import cheshire_pkg::*; #( riscv::priv_lvl_t clic_irq_priv; cva6 #( - .ArianeCfg ( Cva6Cfg ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( Cva6IdWidth ), + .CVA6Cfg ( Cva6Cfg ), .axi_ar_chan_t ( axi_cva6_ar_chan_t ), .axi_aw_chan_t ( axi_cva6_aw_chan_t ), .axi_w_chan_t ( axi_cva6_w_chan_t ), - .axi_req_t ( axi_cva6_req_t ), - .axi_rsp_t ( axi_cva6_rsp_t ) + .b_chan_t ( axi_cva6_b_chan_t ), + .r_chan_t ( axi_cva6_r_chan_t ), + .noc_req_t ( axi_cva6_req_t ), + .noc_resp_t ( axi_cva6_rsp_t ) ) i_core_cva6 ( .clk_i, .rst_ni, @@ -616,13 +615,11 @@ module cheshire_soc import cheshire_pkg::*; #( .clic_irq_ready_o ( clic_irq_ready ), .clic_kill_req_i ( clic_irq_kill_req ), .clic_kill_ack_o ( clic_irq_kill_ack ), - .rvfi_o ( ), + .rvfi_probes_o ( ), .cvxif_req_o ( ), .cvxif_resp_i ( '0 ), - .l15_req_o ( ), - .l15_rtrn_i ( '0 ), - .axi_req_o ( core_out_req ), - .axi_resp_i ( core_out_rsp ) + .noc_req_o ( core_out_req ), + .noc_resp_i ( core_out_rsp ) ); if (Cfg.BusErr) begin : gen_cva6_bus_err diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 188e0ce3..aad319b8 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -69,9 +69,9 @@ module cheshire_top_xilinx // Configure cheshire for FPGA mapping localparam cheshire_cfg_t FPGACfg = '{ // CVA6 parameters - Cva6RASDepth : ariane_pkg::ArianeDefaultConfig.RASDepth, - Cva6BTBEntries : ariane_pkg::ArianeDefaultConfig.BTBEntries, - Cva6BHTEntries : ariane_pkg::ArianeDefaultConfig.BHTEntries, + Cva6RASDepth : 2, + Cva6BTBEntries : 32, + Cva6BHTEntries : 128, Cva6NrPMPEntries : 0, Cva6ExtCieLength : 'h2000_0000, // Harts