diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 5beb5096..ce59b9cf 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -289,9 +289,7 @@ package cheshire_pkg; localparam doub_bt AmLlc = 'h0300_1000; localparam doub_bt AmSlink = 'h0300_6000; localparam doub_bt AmBusErr = 'h0300_8000; - // Address 0x0300_A000 is occupied by the tagger in Carfield. - // Removed for the moment to isolate the contribution of this PR. - // Leaving this comment and the free scope to keep track. + localparam doub_bt AmTagger = 'h0300_A000; localparam doub_bt AmHmrUnit = 'h0300_B000; localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top localparam doub_bt AmClic = 'h0800_0000; @@ -409,6 +407,7 @@ package cheshire_pkg; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; aw_bt [2**MaxCoresWidth-1:0] clic; + aw_bt [2**MaxCoresWidth-1:0] tagger; aw_bt hmr_unit; aw_bt ext_base; aw_bt num_out; @@ -438,6 +437,9 @@ package cheshire_pkg; if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40}; end + if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin + i++; ret.tagger[j] = i; r++; ret.map[r] = '{i, AmTagger + j*'h100, AmTagger + (j+1)*'h100}; + end if (cfg.HmrUnit) begin i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400}; end diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index d16ad627..80fd2ad2 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -791,8 +791,8 @@ module cheshire_soc import cheshire_pkg::*; #( .rst_ni, .slv_req_i ( core_ur_req[i] ), .slv_resp_o ( core_ur_rsp[i] ), - .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), - .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) + .mst_req_o ( tagger_req[i] ), + .mst_resp_i ( tagger_rsp[i] ) ); if (Cfg.LlcCachePartition) begin : gen_tagger diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index cfdc05f4..c5cfab20 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -261,6 +261,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( input doub_bt addr, output word_bt data, input int unsigned idle_cycles = 20 + ); automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0}; jtag_write(dm::SBCS, sbcs, 0, 1);