From 33ad6a779936a322934066baa608254a822c763a Mon Sep 17 00:00:00 2001 From: aottaviano Date: Wed, 14 Feb 2024 11:31:14 +0100 Subject: [PATCH] target/sim: Add JTAG task to halt and load binary * Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. --- target/sim/src/vip_cheshire_soc.sv | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index a40f04d2..d8f70e5b 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -256,6 +256,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #( $display("[JTAG] Initialization success"); endtask + // Halt the core and preload a binary + task automatic jtag_elf_halt_load(input string binary, output doub_bt entry ); + dm::dmstatus_t status; + // Wait until bootrom initialized LLC + if (DutCfg.LlcNotBypass) begin + word_bt regval; + $display("[JTAG] Wait for LLC configuration"); + jtag_poll_bit0(AmLlc + axi_llc_reg_pkg::AXI_LLC_CFG_SPM_LOW_OFFSET, regval, 20); + end + // Halt hart 0 + jtag_write(dm::DMControl, dm::dmcontrol_t'{haltreq: 1, dmactive: 1, default: '0}); + do jtag_dbg.read_dmi_exp_backoff(dm::DMStatus, status); + while (~status.allhalted); + $display("[JTAG] Halted hart 0"); + // Preload binary + jtag_elf_preload(binary, entry); + endtask + task automatic jtag_write_reg32(input logic [31:0] start_addr, logic [63:0] value); logic [31:0] rdata;