From abe9d6825cf4119aea55d663e9159b36e3292f17 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Dec 2024 12:07:21 +0100 Subject: [PATCH] tmpl: Fix prefix for synopsys include paths --- src/script_fmt/synopsys_tcl.tera | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/script_fmt/synopsys_tcl.tera b/src/script_fmt/synopsys_tcl.tera index e001b17d..394c9e7d 100644 --- a/src/script_fmt/synopsys_tcl.tera +++ b/src/script_fmt/synopsys_tcl.tera @@ -5,7 +5,7 @@ set search_path_initial $search_path #}{% for group in srcs %} set search_path $search_path_initial {% for incdir in group.incdirs %}{# Add group's include directories -#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}" +#}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}" {% endfor %} {% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately #}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{# Analyze command for SystemVerilog or VHDL #} @@ -24,7 +24,7 @@ set search_path $search_path_initial #}{% for file in all_verilog %}{# Loop over verilog files #}{% if loop.first %}set search_path $search_path_initial {% for incdir in all_incdirs %}{# Add all include directories -#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}" +#}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}" {% endfor %} {% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately #}analyze -format sv \{# Analyze command for SystemVerilog #}