How to use parameter from my IP

[gkamendje73]

I have some parameters (bit width, initial values etc) defined in a Systemverilog package and I was wondering how I could use those values while specifiying my registers. I see that there is an entry called parametrized values in the WiKi page but I am not sure I fully see how to use it.

[taichi-ishitani]

RgGen supports parameterized initial value only.
RgGen will define parameters for bit field of which initial value has default keyword.
https://github.com/rggen/rggen-sample/blob/b0439abf7d5fa6086c4d0aef0ffcdc6836506f06/block_0.yml#L117

For the above example, RgGen will generate RTL code including the REGISTER_10_BIT_FIELD_1_INITIAL_VALUE parameter. You can override this parameter to propagate your IP parameter.
https://github.com/rggen/rggen-sample/blob/b0439abf7d5fa6086c4d0aef0ffcdc6836506f06/block_0.sv#L31

[taichi-ishitani]

What fields do you want to parameterize?

[gkamendje73]

Thanks for your answer.
I would like to parametrize both the width of a bit field and of course the initial value.

[taichi-ishitani]

During loading register map specifications, RgGen checks if two bit fields in the same register do not overwrap.
Therefore, RgGen needs static maximum bit width.
Do you accept static range parameterization like bwloe?

- bit_fields
  - { name: foo, bit_assignment: { lsb: 0, max_width: 8 }, type: rw, initial_value 0 }

For this case, you can change width of foo bit field when you instantiate the generated CSR module and its range is from 1 to 8.

[taichi-ishitani]

I've open an issue for paraemterized bit field width.
#201 (comment)