From 281dd3bd38049f70da38d8b9d485c39ae80be78a Mon Sep 17 00:00:00 2001
From: "Chereshnev, Eugene" <eugene.chereshnev@intel.com>
Date: Thu, 1 Aug 2024 11:40:33 -0700
Subject: [PATCH] xe: jit: codegen: allow scalar-based reduce for incompatible
 layouts

---
 src/gpu/intel/jit/codegen/reduce.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gpu/intel/jit/codegen/reduce.hpp b/src/gpu/intel/jit/codegen/reduce.hpp
index 2fffff0c950..72d2db33ca1 100644
--- a/src/gpu/intel/jit/codegen/reduce.hpp
+++ b/src/gpu/intel/jit/codegen/reduce.hpp
@@ -135,9 +135,9 @@ class reduce_impl_t {
                 a = layout_t(a.type(), a.ndims(), 0, a_blocks);
                 return find_1d_tile(a, b);
             }
+            return tensor_t(std::vector<dim_t>(b.ndims(), 1));
         }
 
-        ir_assert(ok) << "Incompatible layouts for reduction.";
         ir_assert(dim_t(b0.stride) == 1)
                 << "Reduction is not supported for non-unit dst stride.";