From bd96a2d4d5f352059e7c1636617482533042ec20 Mon Sep 17 00:00:00 2001 From: Mcu_sdk Ci Date: Tue, 2 Apr 2024 11:01:00 +0200 Subject: [PATCH] Add SVD files for K32W1 and update SVD for RW61x Merge in MCUCORE/mcux-soc-svd from release/2.15.000_connectivity_gh_review to release/2.15.000_connectivity_gh --- K32W1480/K32W1480.xml | 206950 +++++++++++++++++++++++++++++++++++++++ RW610/RW610.xml | 315 +- RW612/RW612.xml | 315 +- 3 files changed, 207498 insertions(+), 82 deletions(-) create mode 100644 K32W1480/K32W1480.xml diff --git a/K32W1480/K32W1480.xml b/K32W1480/K32W1480.xml new file mode 100644 index 0000000..69787ef --- /dev/null +++ b/K32W1480/K32W1480.xml @@ -0,0 +1,206950 @@ + + + nxp.com + K32W1480 + 1.0 + K32W1480VFTA + +Copyright 2016-2024 NXP +SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r2p0 + little + true + true + true + 3 + false + + 8 + 32 + + + AXBS0 + AXBS + AXBS + 0x40000000 + + 0 + 0xD04 + registers + + + + PRS0 + Priority Slave Registers + 0 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS0 + Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS1 + Priority Slave Registers + 0x100 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS1 + Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS2 + Priority Slave Registers + 0x200 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS2 + Control Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS3 + Priority Slave Registers + 0x300 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS3 + Control Register + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS4 + Priority Slave Registers + 0x400 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS4 + Control Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS5 + Priority Slave Registers + 0x500 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS5 + Control Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS6 + Priority Slave Registers + 0x600 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS6 + Control Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + PRS7 + Priority Slave Registers + 0x700 + 32 + read-write + 0x543210 + 0xFFFFFFFF + + + M0 + Master 0 Priority + 0 + 3 + read-write + + + M0_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M0_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M0_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M0_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M0_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M0_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M0_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M0_7 + This master has level 8 or the lowest priority when accessing the slave port. + 0x7 + + + + + M1 + Master 1 Priority + 4 + 3 + read-write + + + M1_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M1_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M1_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M1_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M1_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M1_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M1_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M1_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M2 + Master 2 Priority + 8 + 3 + read-write + + + M2_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M2_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M2_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M2_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M2_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M2_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M2_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M2_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M3 + Master 3 Priority + 12 + 3 + read-write + + + M3_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M3_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M3_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M3_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M3_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M3_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M3_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M3_7 + This master has level 8the or lowest priority when accessing the slave port. + 0x7 + + + + + M4 + Master 4 Priority + 16 + 3 + read-write + + + M4_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M4_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M4_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M4_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M4_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M4_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M4_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M4_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + M5 + Master 5 Priority + 20 + 3 + read-write + + + M5_0 + This master has level 1 or highest priority when accessing the slave port. + 0 + + + M5_1 + This master has level 2 priority when accessing the slave port. + 0x1 + + + M5_2 + This master has level 3 priority when accessing the slave port. + 0x2 + + + M5_3 + This master has level 4 priority when accessing the slave port. + 0x3 + + + M5_4 + This master has level 5 priority when accessing the slave port. + 0x4 + + + M5_5 + This master has level 6 priority when accessing the slave port. + 0x5 + + + M5_6 + This master has level 7 priority when accessing the slave port. + 0x6 + + + M5_7 + This master has level 8 or lowest priority when accessing the slave port. + 0x7 + + + + + + + CRS7 + Control Register + 0x710 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARK + Park + 0 + 3 + read-write + + + PARK_1 + Park on master port M1. + 0x1 + + + PARK_2 + Park on master port M2. + 0x2 + + + PARK_3 + Park on master port M3. + 0x3 + + + PARK_4 + Park on master port M4. + 0x4 + + + PARK_5 + Park on master port M5. + 0x5 + + + PARK_6 + Park on master port M6. + 0x6 + + + PARK_7 + Park on master port M0. + 0x7 + + + + + PCTL + Parking Control + 4 + 2 + read-write + + + PCTL_0 + When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. + 0 + + + PCTL_1 + When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + 0x1 + + + PCTL_2 + When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + 0x2 + + + + + ARB + Arbitration Mode + 8 + 2 + read-write + + + ARB_0 + Fixed priority + 0 + + + ARB_1 + Round-robin(RR) or rotating priority + 0x1 + + + + + HLP + Halt Low Priority + 30 + 1 + read-write + + + HLP_0 + The low-power mode request has the highest priority for arbitration on this slave port. + 0 + + + HLP_1 + The low-power mode request has the lowest initial priority for arbitration on this slave port. + 0x1 + + + + + RO + Read Only + 31 + 1 + read-write + + + RO_0 + The slave port's registers are writeable. + 0 + + + RO_1 + The slave port's registers are read-only and cannot be written. Attempted writes do not affect the registers and result in a bus error response. + 0x1 + + + + + + + MGPCR0 + Master General Purpose Control Register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + AULB + Arbitrates On Undefined Length Bursts + 0 + 3 + read-write + + + AULB_0 + No arbitration is allowed during an undefined length burst. + 0 + + + AULB_1 + Arbitration is allowed at any time during an undefined length burst. + 0x1 + + + AULB_2 + Arbitration is allowed after four beats of an undefined length burst. + 0x2 + + + AULB_3 + Arbitration is allowed after eight beats of an undefined length burst. + 0x3 + + + AULB_4 + Arbitration is allowed after 16 beats of an undefined length burst. + 0x4 + + + + + + + MGPCR1 + Master General Purpose Control Register + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + AULB + Arbitrates On Undefined Length Bursts + 0 + 3 + read-write + + + AULB_0 + No arbitration is allowed during an undefined length burst. + 0 + + + AULB_1 + Arbitration is allowed at any time during an undefined length burst. + 0x1 + + + AULB_2 + Arbitration is allowed after four beats of an undefined length burst. + 0x2 + + + AULB_3 + Arbitration is allowed after eight beats of an undefined length burst. + 0x3 + + + AULB_4 + Arbitration is allowed after 16 beats of an undefined length burst. + 0x4 + + + + + + + MGPCR2 + Master General Purpose Control Register + 0xA00 + 32 + read-write + 0 + 0xFFFFFFFF + + + AULB + Arbitrates On Undefined Length Bursts + 0 + 3 + read-write + + + AULB_0 + No arbitration is allowed during an undefined length burst. + 0 + + + AULB_1 + Arbitration is allowed at any time during an undefined length burst. + 0x1 + + + AULB_2 + Arbitration is allowed after four beats of an undefined length burst. + 0x2 + + + AULB_3 + Arbitration is allowed after eight beats of an undefined length burst. + 0x3 + + + AULB_4 + Arbitration is allowed after 16 beats of an undefined length burst. + 0x4 + + + + + + + MGPCR3 + Master General Purpose Control Register + 0xB00 + 32 + read-write + 0 + 0xFFFFFFFF + + + AULB + Arbitrates On Undefined Length Bursts + 0 + 3 + read-write + + + AULB_0 + No arbitration is allowed during an undefined length burst. + 0 + + + AULB_1 + Arbitration is allowed at any time during an undefined length burst. + 0x1 + + + AULB_2 + Arbitration is allowed after four beats of an undefined length burst. + 0x2 + + + AULB_3 + Arbitration is allowed after eight beats of an undefined length burst. + 0x3 + + + AULB_4 + Arbitration is allowed after 16 beats of an undefined length burst. + 0x4 + + + + + + + MGPCR4 + Master General Purpose Control Register + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + AULB + Arbitrates On Undefined Length Bursts + 0 + 3 + read-write + + + AULB_0 + No arbitration is allowed during an undefined length burst. + 0 + + + AULB_1 + Arbitration is allowed at any time during an undefined length burst. + 0x1 + + + AULB_2 + Arbitration is allowed after four beats of an undefined length burst. + 0x2 + + + AULB_3 + Arbitration is allowed after eight beats of an undefined length burst. + 0x3 + + + AULB_4 + Arbitration is allowed after 16 beats of an undefined length burst. + 0x4 + + + + + + + MGPCR5 + Master General Purpose Control Register + 0xD00 + 32 + read-write + 0 + 0xFFFFFFFF + + + AULB + Arbitrates On Undefined Length Bursts + 0 + 3 + read-write + + + AULB_0 + No arbitration is allowed during an undefined length burst. + 0 + + + AULB_1 + Arbitration is allowed at any time during an undefined length burst. + 0x1 + + + AULB_2 + Arbitration is allowed after four beats of an undefined length burst. + 0x2 + + + AULB_3 + Arbitration is allowed after eight beats of an undefined length burst. + 0x3 + + + AULB_4 + Arbitration is allowed after 16 beats of an undefined length burst. + 0x4 + + + + + + + + + CMC0 + CMC + CMC + 0x40001000 + + 0 + 0x124 + registers + + + CMC0 + 1 + + + + VERID + Version ID + 0 + 32 + read-only + 0x3010000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + CKCTRL + Clock Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CKMODE + Clocking Mode + 0 + 4 + read-write + + + CKMODE0000 + No clock gating + 0 + + + CKMODE0001 + Core clock is gated + 0x1 + + + CKMODE0011 + Core and platform clocks are gated + 0x3 + + + CKMODE0111 + Core, platform, and peripheral clocks are gated, but no change in Low-Power mode + 0x7 + + + CKMODE1111 + Core, platform, and peripheral clocks are gated, and core enters Low-Power mode + 0xF + + + + + LOCK + Lock + 31 + 1 + read-write + + + DISABLED + Allowed + 0 + + + ENABLED + Blocked + 0x1 + + + + + + + CKSTAT + Clock Status + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CKMODE + Low Power Status + 0 + 4 + read-only + + + CKMODE0000 + Core clock not gated + 0 + + + CKMODE0001 + Core clock was gated + 0x1 + + + CKMODE0011 + Core and platform clocks were gated + 0x3 + + + CKMODE0111 + Core, platform, and peripheral clocks were gated + 0x7 + + + CKMODE1111 + Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode + 0xF + + + + + WAKEUP + Wake-up Source + 8 + 7 + read-only + + + VALID + Clock Status Valid + 31 + 1 + read-write + oneToClear + + + DISABLED + Core clock not gated + 0 + + + ENABLED + Core clock was gated due to Low-Power mode entry + 0x1 + + + + + + + PMPROT + Power Mode Protection + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPMODE + Low-Power Mode + 0 + 4 + read-write + + + DISABLED + Not allowed + 0 + + + ENABLED + Allowed + 0x1 + + + + + LOCK + Lock Register + 31 + 1 + read-write + + + DISABLED + Allowed + 0 + + + ENABLED + Blocked + 0x1 + + + + + + + GPMCTRL + Global Power Mode Control + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LPMODE + Low-Power Mode + 0 + 4 + read-write + + + + + PMCTRLMAIN + Power Mode Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPMODE + Low-Power Mode + 0 + 4 + read-write + + + LPMODE0000 + Active + 0 + + + LPMODE0001 + Sleep + 0x1 + + + LPMODE0011 + Deep Sleep + 0x3 + + + LPMODE0111 + Power Down + 0x7 + + + LPMODE1111 + Deep-Power Down + 0xF + + + + + + + PMCTRLWAKE + Power Mode Control + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPMODE + Low-Power Mode + 0 + 4 + read-write + + + LPMODE0000 + Active + 0 + + + LPMODE0001 + Sleep + 0x1 + + + LPMODE0011 + Deep Sleep + 0x3 + + + LPMODE0111 + Power Down + 0x7 + + + LPMODE1111 + Deep-Power Down + 0xF + + + + + + + SRS + System Reset Status + 0x80 + 32 + read-only + 0 + 0 + + + WAKEUP + Wake-up Reset + 0 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + POR + Power-on Reset + 1 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + LVD + Low Voltage Detect Reset + 2 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + HVD + High Voltage Detect Reset + 3 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + WARM + Warm Reset + 4 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + FATAL + Fatal Reset + 5 + 1 + read-only + + + DISABLED + Reset was not generated + 0 + + + ENABLED + Reset was generated + 0x1 + + + + + PIN + Pin Reset + 8 + 1 + read-only + + + DISABLED + Reset was not generated + 0 + + + ENABLED + Reset was generated + 0x1 + + + + + DAP + Debug Access Port Reset + 9 + 1 + read-only + + + DISABLED + Reset was not generated + 0 + + + ENABLED + Reset was generated + 0x1 + + + + + RSTACK + Reset Timeout + 10 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + LPACK + Low Power Acknowledge Timeout Reset + 11 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + SCG + System Clock Generation Reset + 12 + 1 + read-only + + + DISABLED + Reset is not generated + 0 + + + ENABLED + Reset is generated + 0x1 + + + + + WDOG0 + Watchdog 0 Reset + 13 + 1 + read-only + + + DISABLED + Reset is not generated + 0 + + + ENABLED + Reset is generated + 0x1 + + + + + SW + Software Reset + 14 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + LOCKUP + Lockup Reset + 15 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + WDOG1 + Watchdog 1 Reset + 25 + 1 + read-only + + + DISABLED + Reset is not generated + 0 + + + ENABLED + Reset is generated + 0x1 + + + + + SECVIO + Security Violation Reset + 30 + 1 + read-only + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + + + RPC + Reset Pin Control + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILTCFG + Reset Filter Configuration + 0 + 5 + read-write + + + FILTEN + Filter Enable + 8 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + LPFEN + Low-Power Filter Enable + 9 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + + + SSRS + Sticky System Reset Status + 0x88 + 32 + read-write + 0x6 + 0xFFFFFFFF + oneToClear + + + WAKEUP + Wake-up Reset + 0 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + POR + Power-on Reset + 1 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + LVD + Low Voltage Detect Reset + 2 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + HVD + High Voltage Detect Reset + 3 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + WARM + Warm Reset + 4 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + FATAL + Fatal Reset + 5 + 1 + read-write + oneToClear + + + DISABLED + Reset was not generated + 0 + + + ENABLED + Reset was generated + 0x1 + + + + + PIN + Pin Reset + 8 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + DAP + DAP Reset + 9 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + RSTACK + Reset Timeout + 10 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + LPACK + Low Power Acknowledge Timeout Reset + 11 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + SCG + System Clock Generation Reset + 12 + 1 + read-write + oneToClear + + + DISABLED + Reset is not generated + 0 + + + ENABLED + Reset is generated + 0x1 + + + + + WDOG0 + Watchdog 0 Reset + 13 + 1 + read-write + oneToClear + + + DISABLED + Reset is not generated + 0 + + + ENABLED + Reset is generated + 0x1 + + + + + SW + Software Reset + 14 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + LOCKUP + Lockup Reset + 15 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + WDOG1 + Watchdog 1 Reset + 25 + 1 + read-write + oneToClear + + + DISABLED + Reset is not generated + 0 + + + ENABLED + Reset is generated + 0x1 + + + + + SECVIO + Security Violation Reset + 30 + 1 + read-write + oneToClear + + + DISABLED + Reset not generated + 0 + + + ENABLED + Reset generated + 0x1 + + + + + + + SRIE + System Reset Interrupt Enable + 0x8C + 32 + read-write + 0x8800 + 0xFFFFFFFF + + + PIN + Pin Reset + 8 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + DAP + DAP Reset + 9 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + LPACK + Low Power Acknowledge Timeout Reset + 11 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + WDOG0 + Watchdog 0 Reset + 13 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + SW + Software Reset + 14 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + LOCKUP + Lockup Reset + 15 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + WDOG1 + Watchdog 1 Reset + 25 + 1 + read-write + + + DISABLED + Interrupt disabled + 0 + + + ENABLED + Interrupt enabled + 0x1 + + + + + + + SRIF + System Reset Interrupt Flag + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + PIN + Pin Reset + 8 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + DAP + DAP Reset + 9 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + LPACK + Low Power Acknowledge Timeout Reset + 11 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + WDOG0 + Watchdog 0 Reset + 13 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + SW + Software Reset + 14 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + LOCKUP + Lockup Reset + 15 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + WDOG1 + Watchdog 1 Reset + 25 + 1 + read-write + oneToClear + + + DISABLED + Reset source not pending + 0 + + + ENABLED + Reset source pending + 0x1 + + + + + + + RSTCNT + Reset Count Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Count + 0 + 8 + read-only + + + + + MR0 + Mode + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + ISPMODE_n + Boot Configuration + 0 + 1 + read-write + oneToClear + + + + + FM0 + Force Mode + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORCECFG + Boot Configuration + 0 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + Asserts + 0x1 + + + + + + + SRAMDIS0 + SRAM Shut Down Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIS + Shut Down Enable + 0 + 8 + read-write + + + + + SRAMRET0 + SRAM Deep Sleep Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RET + Deep Sleep Enable + 0 + 8 + read-write + + + + + FLASHCR + Flash Control + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASHDIS + Flash Disable + 0 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + Flash memory is disabled + 0x1 + + + + + FLASHDOZE + Flash Doze + 1 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + Flash memory is disabled when core is sleeping (CKMODE > 0) + 0x1 + + + + + FLASHWAKE + Flash Wake + 2 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + Flash memory is not disabled during flash memory accesses + 0x1 + + + + + + + BSR + BootROM Status + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + STAT + Provides status information written by the BootROM. + 0 + 32 + read-write + + + + + BLR + BootROM Lock Register + 0x10C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Lock + 0 + 3 + read-write + + + LOCK010 + BootROM Status and Lock Registers can be written + 0x2 + + + LOCK101 + BootROM Status and Lock Registers cannot be written + 0x5 + + + + + + + CORECTL + Core Control + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + NPIE + Non-maskable Pin Interrupt Enable + 0 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + + + DBGCTL + Debug Control + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOD + Sleep Or Debug + 0 + 1 + read-write + + + DISABLED + Remains enabled + 0 + + + ENABLED + Disabled + 0x1 + + + + + + + + + DMA0 + DMA MP + MP + 0x40002000 + + 0 + 0x140 + registers + + + DMA0_CH0 + 2 + + + DMA0_CH1 + 3 + + + DMA0_CH2 + 4 + + + DMA0_CH3 + 5 + + + DMA0_CH4 + 6 + + + DMA0_CH5 + 7 + + + DMA0_CH6 + 8 + + + DMA0_CH7 + 9 + + + DMA0_CH8 + 10 + + + DMA0_CH9 + 11 + + + DMA0_CH10 + 12 + + + DMA0_CH11 + 13 + + + DMA0_CH12 + 14 + + + DMA0_CH13 + 15 + + + DMA0_CH14 + 16 + + + DMA0_CH15 + 17 + + + + MP_CSR + Management Page Control + 0 + 32 + read-write + 0x310000 + 0xFFFFFFFF + + + EDBG + Enable Debug + 1 + 1 + read-write + + + DISABLE + Debug mode disabled + 0 + + + ENABLE + Debug mode is enabled. + 0x1 + + + + + ERCA + Enable Round Robin Channel Arbitration + 2 + 1 + read-write + + + DISABLE + Round-robin channel arbitration disabled + 0 + + + ENABLE + Round-robin channel arbitration enabled + 0x1 + + + + + HAE + Halt After Error + 4 + 1 + read-write + + + NORMAL_OPERATION + Normal operation + 0 + + + HALT + Any error causes the HALT field to be set to 1 + 0x1 + + + + + HALT + Halt DMA Operations + 5 + 1 + read-write + + + NORMAL_OPERATION + Normal operation + 0 + + + STALL + Stall the start of any new channels + 0x1 + + + + + GCLC + Global Channel Linking Control + 6 + 1 + read-write + + + DISABLE + Channel linking disabled for all channels + 0 + + + AVAILABLE + Channel linking available and controlled by each channel's link settings + 0x1 + + + + + GMRC + Global Master ID Replication Control + 7 + 1 + read-write + + + DISABLE + Master ID replication disabled for all channels + 0 + + + AVAILABLE + Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + 0x1 + + + + + ECX + Cancel Transfer With Error + 8 + 1 + read-write + + + NORMAL_OPERATION + Normal operation + 0 + + + CANCEL + Cancel the remaining data transfer + 0x1 + + + + + CX + Cancel Transfer + 9 + 1 + read-write + + + NORMAL_OPERATION + Normal operation + 0 + + + DATA_TRANSFER_CANCEL + Cancel the remaining data transfer + 0x1 + + + + + ACTIVE_ID + Active Channel ID + 24 + 4 + read-only + + + ACTIVE + DMA Active Status + 31 + 1 + read-only + + + IDLE + eDMA is idle + 0 + + + EXECUTION + eDMA is executing a channel + 0x1 + + + + + + + MP_ES + Management Page Error Status + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + NO_ERROR + No destination bus error + 0 + + + BUS_ERROR + Last recorded error was a bus error on a destination write + 0x1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + NO_ERROR + No source bus error + 0 + + + BUS_ERROR + Last recorded error was a bus error on a source read + 0x1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + NO_ERROR + No scatter/gather configuration error + 0 + + + CONFIGURATION_ERROR + Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + 0x1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + NO_ERROR + No NBYTES/CITER configuration error + 0 + + + CONFIGURATION_ERROR + The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + 0x1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + NO_ERROR + No destination offset configuration error + 0 + + + CONFIGURATION_ERROR + Last recorded error was a configuration error detected in the TCDn_DOFF field + 0x1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + NO_ERROR + No destination address configuration error + 0 + + + CONFIGURATION_ERROR + Last recorded error was a configuration error detected in the TCDn_DADDR field + 0x1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + NO_ERROR + No source offset configuration error + 0 + + + CONFIGURATION_ERROR + Last recorded error was a configuration error detected in the TCDn_SOFF field + 0x1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + NO_ERROR + No source address configuration error + 0 + + + CONFIGURATION_ERROR + Last recorded error was a configuration error detected in the TCDn_SADDR field + 0x1 + + + + + ECX + Transfer Canceled + 8 + 1 + read-only + + + NO_CANCELED_TRANSFERS + No canceled transfers + 0 + + + CANCELED_TRANSFER + Last recorded entry was a canceled transfer by the error cancel transfer input + 0x1 + + + + + ERRCHN + Error Channel Number or Canceled Channel Number + 24 + 4 + read-only + + + VLD + Valid + 31 + 1 + read-only + + + NO_FIELD_SET_ONE + No ERR fields are set to 1 + 0 + + + ATLEAST_ONE_FIELD + At least one ERR field is set to 1, indicating a valid error exists that software has not cleared + 0x1 + + + + + + + MP_INT + Management Page Interrupt Request Status + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + INT + Interrupt Request Status + 0 + 16 + read-only + + + + + MP_HRS + Management Page Hardware Request Status + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + HRS + Hardware Request Status + 0 + 32 + read-only + + + + + 16 + 0x4 + CH_GRPRI[%s] + Channel Arbitration Group + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GRPRI + Arbitration Group For Channel n + 0 + 5 + read-write + + + + + + + TCD + DMA TCD + TCD + 0x40003000 + + 0 + 0xF040 + registers + + + + 16 + 0x1000 + TCD[%s] + no description available + 0 + + CH_CSR + Channel Control and Status + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERQ + Enable DMA Request + 0 + 1 + read-write + + + DISABLE + DMA hardware request signal for corresponding channel disabled + 0 + + + ENABLE + DMA hardware request signal for corresponding channel enabled + 0x1 + + + + + EARQ + Enable Asynchronous DMA Request + 1 + 1 + read-write + + + DISABLE + Disable asynchronous DMA request for the channel + 0 + + + ENABLE + Enable asynchronous DMA request for the channel + 0x1 + + + + + EEI + Enable Error Interrupt + 2 + 1 + read-write + + + NO_ERROR + Error signal for corresponding channel does not generate error interrupt + 0 + + + ERROR + Assertion of error signal for corresponding channel generates error interrupt request + 0x1 + + + + + EBW + Enable Buffered Writes + 3 + 1 + read-write + + + DISABLE + Buffered writes on system bus disabled + 0 + + + ENABLE + Buffered writes on system bus enabled + 0x1 + + + + + DONE + Channel Done + 30 + 1 + read-write + oneToClear + + + ACTIVE + Channel Active + 31 + 1 + read-only + + + + + CH_ES + Channel Error Status + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + NO_ERROR + No destination bus error + 0 + + + ERROR + Last recorded error was bus error on destination write + 0x1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + NO_ERROR + No source bus error + 0 + + + ERROR + Last recorded error was bus error on source read + 0x1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + NO_ERROR + No scatter/gather configuration error + 0 + + + ERROR + Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + 0x1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + NO_ERROR + No NBYTES/CITER configuration error + 0 + + + ERROR + Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + 0x1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + NO_ERROR + No destination offset configuration error + 0 + + + ERROR + Last recorded error was a configuration error detected in the TCDn_DOFF field + 0x1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + NO_ERROR + No destination address configuration error + 0 + + + ERROR + Last recorded error was a configuration error detected in the TCDn_DADDR field + 0x1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + NO_ERROR + No source offset configuration error + 0 + + + ERROR + Last recorded error was a configuration error detected in the TCDn_SOFF field + 0x1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + NO_ERROR + No source address configuration error + 0 + + + ERROR + Last recorded error was a configuration error detected in the TCDn_SADDR field + 0x1 + + + + + ERR + Error In Channel + 31 + 1 + read-write + oneToClear + + + NO_ERROR + An error in this channel has not occurred + 0 + + + ERROR + An error in this channel has occurred + 0x1 + + + + + + + CH_INT + Channel Interrupt Status + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + INT + Interrupt Request + 0 + 1 + read-write + oneToClear + + + INTERRUPT_CLEARED + Interrupt request for corresponding channel cleared + 0 + + + INTERRUPT_ACTIVE + Interrupt request for corresponding channel active + 0x1 + + + + + + + CH_SBR + Channel System Bus + 0xC + 32 + read-write + 0x12 + 0xFFFFFFFF + + + MID + Master ID + 0 + 6 + read-only + + + SEC + Security Level + 14 + 1 + read-write + + + NONSECURE_PROTECTION + Nonsecure protection level for DMA transfers + 0 + + + SECURE_PROTECTION + Secure protection level for DMA transfers + 0x1 + + + + + PAL + Privileged Access Level + 15 + 1 + read-write + + + USER_PROTECTION + User protection level for DMA transfers + 0 + + + PRIVILEGED_PROTECTION + Privileged protection level for DMA transfers + 0x1 + + + + + EMI + Enable Master ID Replication + 16 + 1 + read-write + + + DISABLE + Master ID replication is disabled + 0 + + + ENABLE + Master ID replication is enabled + 0x1 + + + + + ATTR + Attribute Output + 17 + 4 + read-write + + + + + CH_PRI + Channel Priority + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + APL + Arbitration Priority Level + 0 + 3 + read-write + + + DPA + Disable Preempt Ability + 30 + 1 + read-write + + + SUSPEND + Channel can suspend a lower-priority channel + 0 + + + CANNOT_SUSPEND + Channel cannot suspend any other channel, regardless of channel priority + 0x1 + + + + + ECP + Enable Channel Preemption + 31 + 1 + read-write + + + CANNOT_SUSPEND + Channel cannot be suspended by a higher-priority channel's service request + 0 + + + SUSPEND + Channel can be temporarily suspended by a higher-priority channel's service request + 0x1 + + + + + + + CH_MUX + Channel Multiplexor Configuration + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRC + Service Request Source + 0 + 7 + read-write + + + + + TCD_SADDR + TCD Source Address + 0x20 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD_SOFF + TCD Signed Source Address Offset + 0x24 + 16 + read-write + 0 + 0 + + + SOFF + Source Address Signed Offset + 0 + 16 + read-write + + + + + TCD_ATTR + TCD Transfer Attributes + 0x26 + 16 + read-write + 0 + 0 + + + DSIZE + Destination Data Transfer Size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source Data Transfer Size + 8 + 3 + read-write + + + EIGHT_BIT + 8-bit + 0 + + + SIXTEEN_BIT + 16-bit + 0x1 + + + THIRTYTWO_BIT + 32-bit + 0x2 + + + SIXTYFOUR_BIT + 64-bit + 0x3 + + + SIXTEEN_BYTE + 16-byte + 0x4 + + + THIRTYTWO_BYTE + 32-byte + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + DISABLE + Source address modulo feature disabled + 0 + + + ENABLE + Source address modulo feature enabled for any non-zero value [1-31] + 0x1 + + + + + + + TCD_NBYTES_MLOFFNO + TCD Transfer Size Without Minor Loop Offsets + NBYTES + 0x28 + 32 + read-write + 0 + 0 + + + NBYTES + Number of Bytes To Transfer Per Service Request + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + OFFSET_NOT_APPLIED + Minor loop offset not applied to DADDR + 0 + + + OFFSET_APPLIED + Minor loop offset applied to DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + OFFSET_NOT_APPLIED + Minor loop offset not applied to SADDR + 0 + + + OFFSET_APPLIED + Minor loop offset applied to SADDR + 0x1 + + + + + + + TCD_NBYTES_MLOFFYES + TCD Transfer Size with Minor Loop Offsets + NBYTES + 0x28 + 32 + read-write + 0 + 0 + + + NBYTES + Number of Bytes To Transfer Per Service Request + 0 + 10 + read-write + + + MLOFF + Minor Loop Offset + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + OFFSET_NOT_APPLIED + Minor loop offset not applied to DADDR + 0 + + + OFFSET_APPLIED + Minor loop offset applied to DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + OFFSET_NOT_APPLIED + Minor loop offset not applied to SADDR + 0 + + + OFFSET_APPLIED + Minor loop offset applied to SADDR + 0x1 + + + + + + + TCD_SLAST_SDA + TCD Last Source Address Adjustment / Store DADDR Address + 0x2C + 32 + read-write + 0 + 0 + + + SLAST_SDA + Last Source Address Adjustment / Store DADDR Address + 0 + 32 + read-write + + + + + TCD_DADDR + TCD Destination Address + 0x30 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD_DOFF + TCD Signed Destination Address Offset + 0x34 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD_CITER_ELINKNO + TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) + CITER + 0x36 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable Link + 15 + 1 + read-write + + + DISABLE + Channel-to-channel linking disabled + 0 + + + ENABLE + Channel-to-channel linking enabled + 0x1 + + + + + + + TCD_CITER_ELINKYES + TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) + CITER + 0x36 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 4 + read-write + + + ELINK + Enable Link + 15 + 1 + read-write + + + DISABLE + Channel-to-channel linking disabled + 0 + + + ENABLE + Channel-to-channel linking enabled + 0x1 + + + + + + + TCD_DLAST_SGA + TCD Last Destination Address Adjustment / Scatter Gather Address + 0x38 + 32 + read-write + 0 + 0 + + + DLAST_SGA + Last Destination Address Adjustment / Scatter Gather Address + 0 + 32 + read-write + + + + + TCD_CSR + TCD Control and Status + 0x3C + 16 + read-write + 0 + 0x1 + + + START + Channel Start + 0 + 1 + read-write + + + CHANNEL_NOT_STARTED + Channel not explicitly started + 0 + + + CHANNEL_STARTED + Channel explicitly started via a software-initiated service request + 0x1 + + + + + INTMAJOR + Enable Interrupt If Major count complete + 1 + 1 + read-write + + + DISABLE + End-of-major loop interrupt disabled + 0 + + + ENABLE + End-of-major loop interrupt enabled + 0x1 + + + + + INTHALF + Enable Interrupt If Major Counter Half-complete + 2 + 1 + read-write + + + DISABLE + Halfway point interrupt disabled + 0 + + + ENABLE + Halfway point interrupt enabled + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + CHANNEL_NOT_AFFECTED + No operation + 0 + + + ERQ_FIELD_CLEAR + Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + NORMAL_FORMAT + Current channel's TCD is normal format + 0 + + + SCATTER_GATHER_FORMAT + Current channel's TCD specifies scatter/gather format. + 0x1 + + + + + MAJORELINK + Enable Link When Major Loop Complete + 5 + 1 + read-write + + + DISABLE + Channel-to-channel linking disabled + 0 + + + ENABLE + Channel-to-channel linking enabled + 0x1 + + + + + EEOP + Enable End-Of-Packet Processing + 6 + 1 + read-write + + + DISABLE + End-of-packet operation disabled + 0 + + + ENABLE + End-of-packet hardware input signal enabled + 0x1 + + + + + ESDA + Enable Store Destination Address + 7 + 1 + read-write + + + DISABLE + Ability to store destination address to system memory disabled + 0 + + + ENABLE + Ability to store destination address to system memory enabled + 0x1 + + + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 4 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + NO_STALL + No eDMA engine stalls + 0 + + + ENGINE_STALLS_FOUR + eDMA engine stalls for 4 cycles after each R/W + 0x2 + + + ENGINE_STALLS_EIGHT + eDMA engine stalls for 8 cycles after each R/W + 0x3 + + + + + + + TCD_BITER_ELINKNO + TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) + BITER + 0x3E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables Link + 15 + 1 + read-write + + + DISABLE + Channel-to-channel linking disabled + 0 + + + ENABLE + Channel-to-channel linking enabled + 0x1 + + + + + + + TCD_BITER_ELINKYES + TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) + BITER + 0x3E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 4 + read-write + + + ELINK + Enable Link + 15 + 1 + read-write + + + DISABLE + Channel-to-channel linking disabled + 0 + + + ENABLE + Channel-to-channel linking enabled + 0x1 + + + + + + + + + + EWM0 + EWM + EWM + 0x40013000 + + 0 + 0x6 + registers + + + EWM0 + 18 + + + + CTRL + Control + 0 + 8 + read-write + 0 + 0xFF + + + EWMEN + EWM Enable + 0 + 1 + read-writeOnce + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + ASSIN + Assertion State Select + 1 + 1 + read-writeOnce + + + DISABLE + Logic 0 + 0 + + + ENABLE + Logic 1 + 0x1 + + + + + INEN + Input Enable + 2 + 1 + read-writeOnce + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + INTEN + Interrupt Enable + 3 + 1 + read-write + + + ZERO + Deasserts interrupt requests + 0 + + + INT_REQ + Generates interrupt requests + 0x1 + + + + + + + SERV + Service + 0x1 + 8 + read-write + 0 + 0xFF + + + SERVICE + Service + 0 + 8 + read-write + + + + + CMPL + Compare Low + 0x2 + 8 + read-writeOnce + 0 + 0xFF + + + COMPAREL + Compare Low + 0 + 8 + read-writeOnce + + + + + CMPH + Compare High + 0x3 + 8 + read-writeOnce + 0xFF + 0xFF + + + COMPAREH + Compare High + 0 + 8 + read-writeOnce + + + + + CLKPRESCALER + Clock Prescaler + 0x5 + 8 + read-writeOnce + 0 + 0xFF + + + CLK_DIV + Clock Divider + 0 + 8 + read-writeOnce + + + + + + + MSCM + MSCM + MSCM + 0x40014000 + + 0 + 0x824 + registers + + + MSCM0 + 20 + + + + CPxTYPE + Processor X Type Register + 0 + 32 + read-only + 0 + 0 + + + RYPZ + Processor x Revision + 0 + 8 + read-only + + + PERSONALITY + Processor x Personality + 8 + 24 + read-only + + + + + CPxNUM + Processor X Number Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFE + + + CPN + Processor x Number + 0 + 1 + read-only + + + + + CPxMASTER + Processor X Master Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFC0 + + + PPMN + Processor x Physical Master Number + 0 + 6 + read-only + + + + + CPxCOUNT + Processor X Count Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PCNT + Processor Count + 0 + 2 + read-only + + + + + CPxCFG0 + Processor X Configuration Register 0 + 0x10 + 32 + read-only + 0 + 0 + + + DCWY + Level 1 Data Cache Ways + 0 + 8 + read-only + + + DCSZ + Level 1 Data Cache Size + 8 + 8 + read-only + + + ICWY + Level 1 Instruction Cache Ways + 16 + 8 + read-only + + + ICSZ + Level 1 Instruction Cache Size + 24 + 8 + read-only + + + + + CPxCFG1 + Processor X Configuration Register 1 + 0x14 + 32 + read-only + 0 + 0xFFFF + + + L2WY + Level 2 Instruction Cache Ways + 16 + 8 + read-only + + + L2SZ + Level 2 Instruction Cache Size + 24 + 8 + read-only + + + + + CPxCFG2 + Processor X Configuration Register 2 + 0x18 + 32 + read-only + 0x10001 + 0xFF00FF + + + TMUSZ + Tightly-coupled Memory Upper Size + 8 + 8 + read-only + + + TMLSZ + Tightly-coupled Memory Lower Size + 24 + 8 + read-only + + + + + CPxCFG3 + Processor X Configuration Register 3 + 0x1C + 32 + read-only + 0 + 0xFFFFFC80 + + + FPU + Floating Point Unit + 0 + 1 + read-only + + + exclude + FPU support is not included. + 0 + + + include + FPU support is included. + 0x1 + + + + + SIMD + SIMD/NEON instruction support + 1 + 1 + read-only + + + exclude + SIMD/NEON support is not included. + 0 + + + include + SIMD/NEON support is included. + 0x1 + + + + + JAZ + Jazelle support + 2 + 1 + read-only + + + exclude + Jazelle support is not included. + 0 + + + include + Jazelle support is included. + 0x1 + + + + + MMU + Memory Management Unit + 3 + 1 + read-only + + + exclude + MMU support is not included. + 0 + + + include + MMU support is included. + 0x1 + + + + + TZ + Trust Zone + 4 + 1 + read-only + + + exclude + Trust Zone support is not included. + 0 + + + include + Trust Zone support is included. + 0x1 + + + + + CMP + Core Memory Protection unit + 5 + 1 + read-only + + + exclude + Core Memory Protection is not included. + 0 + + + include + Core Memory Protection is included. + 0x1 + + + + + BB + Bit Banding + 6 + 1 + read-only + + + exclude + Bit Banding is not supported. + 0 + + + include + Bit Banding is supported. + 0x1 + + + + + SBP + System Bus Ports + 8 + 2 + read-only + + + + + CP0TYPE + Processor 0 Type Register + 0x20 + 32 + read-only + 0x4D333301 + 0xFFFFFFFF + + + RYPZ + Processor 0 Revision + 0 + 8 + read-only + + + PERSONALITY + Processor 0 Personality + 8 + 24 + read-only + + + + + CP0NUM + Processor 0 Number Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CPN + Processor 0 Number + 0 + 1 + read-only + + + + + CP0MASTER + Processor 0 Master Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + PPMN + Processor 0 Physical Master Number + 0 + 6 + read-only + + + + + CP0COUNT + Processor 0 Count Register + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + PCNT + Processor Count + 0 + 2 + read-only + + + + + CP0CFG0 + Processor 0 Configuration Register 0 + 0x30 + 32 + read-only + 0x4080000 + 0xFFFFFFFF + + + DCWY + Level 1 Data Cache Ways + 0 + 8 + read-only + + + DCSZ + Level 1 Data Cache Size + 8 + 8 + read-only + + + ICWY + Level 1 Instruction Cache Ways + 16 + 8 + read-only + + + ICSZ + Level 1 Instruction Cache Size + 24 + 8 + read-only + + + + + CP0CFG1 + Processor 0 Configuration Register 1 + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + L2WY + Level 2 Instruction Cache Ways + 16 + 8 + read-only + + + L2SZ + Level 2 Instruction Cache Size + 24 + 8 + read-only + + + + + CP0CFG2 + Processor 0 Configuration Register 2 + 0x38 + 32 + read-only + 0x10001 + 0xFFFFFFFF + + + TMUSZ + Tightly-coupled Memory Upper Size + 8 + 8 + read-only + + + TMLSZ + Tightly-coupled Memory Lower Size + 24 + 8 + read-only + + + + + CP0CFG3 + Processor 0 Configuration Register 3 + 0x3C + 32 + read-only + 0x231 + 0xFFFFFFFF + + + FPU + Floating Point Unit + 0 + 1 + read-only + + + exclude + FPU support is not included. + 0 + + + include + FPU support is included. + 0x1 + + + + + SIMD + SIMD/NEON instruction support + 1 + 1 + read-only + + + exclude + SIMD/NEON support is not included. + 0 + + + include + SIMD/NEON support is included. + 0x1 + + + + + JAZ + Jazelle support + 2 + 1 + read-only + + + exclude + Jazelle support is not included. + 0 + + + include + Jazelle support is included. + 0x1 + + + + + MMU + Memory Management Unit + 3 + 1 + read-only + + + exclude + MMU support is not included. + 0 + + + include + MMU support is included. + 0x1 + + + + + TZ + Trust Zone + 4 + 1 + read-only + + + exclude + Trust Zone support is not included. + 0 + + + include + Trust Zone support is included. + 0x1 + + + + + CMP + Core Memory Protection unit + 5 + 1 + read-only + + + exclude + Core Memory Protection is not included. + 0 + + + include + Core Memory Protection is included. + 0x1 + + + + + BB + Bit Banding + 6 + 1 + read-only + + + exclude + Bit Banding is not supported. + 0 + + + include + Bit Banding is supported. + 0x1 + + + + + SBP + System Bus Ports + 8 + 2 + read-only + + + + + OCMDR0 + On-Chip Memory Descriptor Register + 0x400 + 32 + read-only + 0xEB089000 + 0xFFFFFFFF + + + OCMPU + OCMPU + 12 + 1 + read-only + + + OCMT + OCMT + 13 + 3 + read-only + + + sysram + OCMEMn is a System RAM. + 0 + + + rom + OCMEMn is a ROM. + 0x3 + + + flash + OCMEMn is a Program Flash. + 0x4 + + + + + OCMW + OCMW + 17 + 3 + read-only + + + bit32 + OCMEMn 32-bits wide + 0x2 + + + bit64 + OCMEMn 64-bits wide + 0x3 + + + bit128 + OCMEMn 128-bits wide + 0x4 + + + bit256 + OCMEMn 256-bits wide + 0x5 + + + + + OCMSZ + OCMSZ + 24 + 4 + read-only + + + zero + no OCMEMn + 0 + + + size1kb + 1KB OCMEMn + 0x1 + + + size2kb + 2KB OCMEMn + 0x2 + + + size4kb + 4KB OCMEMn + 0x3 + + + size8kb + 8KB OCMEMn + 0x4 + + + size16kb + 16KB OCMEMn + 0x5 + + + size32k + 32KB OCMEMn + 0x6 + + + size64kb + 64KB OCMEMn + 0x7 + + + size128kb + 128KB OCMEMn + 0x8 + + + size256kb + 256KB OCMEMn + 0x9 + + + size512kb + 512KB OCMEMn + 0xA + + + size1mb + 1MB OCMEMn + 0xB + + + size2mb + 2MB OCMEMn + 0xC + + + size4mb + 4MB OCMEMn + 0xD + + + size8mb + 8MB OCMEMn + 0xE + + + size16mb + 16MB OCMEMn + 0xF + + + + + OCMSZH + OCMSZH + 28 + 1 + read-only + + + powerof2 + OCMEMn is a power-of-2 capacity. + 0 + + + nonpowerof2 + OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. + 0x1 + + + + + OCMECC + OCMECC + 29 + 1 + read-only + + + exclude + OCMEMn does not have ECC support. + 0 + + + include + OCMEMn has ECC support. + 0x1 + + + + + V + V + 31 + 1 + read-only + + + exclude + OCMEMn is not present. + 0 + + + include + OCMEMn is present. + 0x1 + + + + + + + OCMDR1 + On-Chip Memory Descriptor Register + 0x404 + 32 + read-only + 0xD8047000 + 0xFFFFFFFF + + + OCMPU + OCMPU + 12 + 1 + read-only + + + OCMT + OCMT + 13 + 3 + read-only + + + sysram + OCMEMn is a System RAM. + 0 + + + rom + OCMEMn is a ROM. + 0x3 + + + flash + OCMEMn is a Program Flash. + 0x4 + + + + + OCMW + OCMW + 17 + 3 + read-only + + + bit32 + OCMEMn 32-bits wide + 0x2 + + + bit64 + OCMEMn 64-bits wide + 0x3 + + + bit128 + OCMEMn 128-bits wide + 0x4 + + + bit256 + OCMEMn 256-bits wide + 0x5 + + + + + OCMSZ + OCMSZ + 24 + 4 + read-only + + + zero + no OCMEMn + 0 + + + size1kb + 1KB OCMEMn + 0x1 + + + size2kb + 2KB OCMEMn + 0x2 + + + size4kb + 4KB OCMEMn + 0x3 + + + size8kb + 8KB OCMEMn + 0x4 + + + size16kb + 16KB OCMEMn + 0x5 + + + size32k + 32KB OCMEMn + 0x6 + + + size64kb + 64KB OCMEMn + 0x7 + + + size128kb + 128KB OCMEMn + 0x8 + + + size256kb + 256KB OCMEMn + 0x9 + + + size512kb + 512KB OCMEMn + 0xA + + + size1mb + 1MB OCMEMn + 0xB + + + size2mb + 2MB OCMEMn + 0xC + + + size4mb + 4MB OCMEMn + 0xD + + + size8mb + 8MB OCMEMn + 0xE + + + size16mb + 16MB OCMEMn + 0xF + + + + + OCMSZH + OCMSZH + 28 + 1 + read-only + + + powerof2 + OCMEMn is a power-of-2 capacity. + 0 + + + nonpowerof2 + OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. + 0x1 + + + + + OCMECC + OCMECC + 29 + 1 + read-only + + + exclude + OCMEMn does not have ECC support. + 0 + + + include + OCMEMn has ECC support. + 0x1 + + + + + V + V + 31 + 1 + read-only + + + exclude + OCMEMn is not present. + 0 + + + include + OCMEMn is present. + 0x1 + + + + + + + OCMDR2 + On-Chip Memory Descriptor Register + 0x408 + 32 + read-only + 0xE5041000 + 0xFFFFFFFF + + + OCMPU + OCMPU + 12 + 1 + read-only + + + OCMT + OCMT + 13 + 3 + read-only + + + sysram + OCMEMn is a System RAM. + 0 + + + rom + OCMEMn is a ROM. + 0x3 + + + flash + OCMEMn is a Program Flash. + 0x4 + + + + + OCMW + OCMW + 17 + 3 + read-only + + + bit32 + OCMEMn 32-bits wide + 0x2 + + + bit64 + OCMEMn 64-bits wide + 0x3 + + + bit128 + OCMEMn 128-bits wide + 0x4 + + + bit256 + OCMEMn 256-bits wide + 0x5 + + + + + OCMSZ + OCMSZ + 24 + 4 + read-only + + + zero + no OCMEMn + 0 + + + size1kb + 1KB OCMEMn + 0x1 + + + size2kb + 2KB OCMEMn + 0x2 + + + size4kb + 4KB OCMEMn + 0x3 + + + size8kb + 8KB OCMEMn + 0x4 + + + size16kb + 16KB OCMEMn + 0x5 + + + size32k + 32KB OCMEMn + 0x6 + + + size64kb + 64KB OCMEMn + 0x7 + + + size128kb + 128KB OCMEMn + 0x8 + + + size256kb + 256KB OCMEMn + 0x9 + + + size512kb + 512KB OCMEMn + 0xA + + + size1mb + 1MB OCMEMn + 0xB + + + size2mb + 2MB OCMEMn + 0xC + + + size4mb + 4MB OCMEMn + 0xD + + + size8mb + 8MB OCMEMn + 0xE + + + size16mb + 16MB OCMEMn + 0xF + + + + + OCMSZH + OCMSZH + 28 + 1 + read-only + + + powerof2 + OCMEMn is a power-of-2 capacity. + 0 + + + nonpowerof2 + OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. + 0x1 + + + + + OCMECC + OCMECC + 29 + 1 + read-only + + + exclude + OCMEMn does not have ECC support. + 0 + + + include + OCMEMn has ECC support. + 0x1 + + + + + V + V + 31 + 1 + read-only + + + exclude + OCMEMn is not present. + 0 + + + include + OCMEMn is present. + 0x1 + + + + + + + OCMDR3 + On-Chip Memory Descriptor Register + 0x40C + 32 + read-only + 0xE7041000 + 0xFFFFFFFF + + + OCMPU + OCMPU + 12 + 1 + read-only + + + OCMT + OCMT + 13 + 3 + read-only + + + sysram + OCMEMn is a System RAM. + 0 + + + rom + OCMEMn is a ROM. + 0x3 + + + flash + OCMEMn is a Program Flash. + 0x4 + + + + + OCMW + OCMW + 17 + 3 + read-only + + + bit32 + OCMEMn 32-bits wide + 0x2 + + + bit64 + OCMEMn 64-bits wide + 0x3 + + + bit128 + OCMEMn 128-bits wide + 0x4 + + + bit256 + OCMEMn 256-bits wide + 0x5 + + + + + OCMSZ + OCMSZ + 24 + 4 + read-only + + + zero + no OCMEMn + 0 + + + size1kb + 1KB OCMEMn + 0x1 + + + size2kb + 2KB OCMEMn + 0x2 + + + size4kb + 4KB OCMEMn + 0x3 + + + size8kb + 8KB OCMEMn + 0x4 + + + size16kb + 16KB OCMEMn + 0x5 + + + size32k + 32KB OCMEMn + 0x6 + + + size64kb + 64KB OCMEMn + 0x7 + + + size128kb + 128KB OCMEMn + 0x8 + + + size256kb + 256KB OCMEMn + 0x9 + + + size512kb + 512KB OCMEMn + 0xA + + + size1mb + 1MB OCMEMn + 0xB + + + size2mb + 2MB OCMEMn + 0xC + + + size4mb + 4MB OCMEMn + 0xD + + + size8mb + 8MB OCMEMn + 0xE + + + size16mb + 16MB OCMEMn + 0xF + + + + + OCMSZH + OCMSZH + 28 + 1 + read-only + + + powerof2 + OCMEMn is a power-of-2 capacity. + 0 + + + nonpowerof2 + OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. + 0x1 + + + + + OCMECC + OCMECC + 29 + 1 + read-only + + + exclude + OCMEMn does not have ECC support. + 0 + + + include + OCMEMn has ECC support. + 0x1 + + + + + V + V + 31 + 1 + read-only + + + exclude + OCMEMn is not present. + 0 + + + include + OCMEMn is present. + 0x1 + + + + + + + OCMDR4 + On-Chip Memory Descriptor Register + 0x410 + 32 + read-only + 0xD7041000 + 0xFFFFFFFF + + + OCMPU + OCMPU + 12 + 1 + read-only + + + OCMT + OCMT + 13 + 3 + read-only + + + sysram + OCMEMn is a System RAM. + 0 + + + rom + OCMEMn is a ROM. + 0x3 + + + flash + OCMEMn is a Program Flash. + 0x4 + + + + + OCMW + OCMW + 17 + 3 + read-only + + + bit32 + OCMEMn 32-bits wide + 0x2 + + + bit64 + OCMEMn 64-bits wide + 0x3 + + + bit128 + OCMEMn 128-bits wide + 0x4 + + + bit256 + OCMEMn 256-bits wide + 0x5 + + + + + OCMSZ + OCMSZ + 24 + 4 + read-only + + + zero + no OCMEMn + 0 + + + size1kb + 1KB OCMEMn + 0x1 + + + size2kb + 2KB OCMEMn + 0x2 + + + size4kb + 4KB OCMEMn + 0x3 + + + size8kb + 8KB OCMEMn + 0x4 + + + size16kb + 16KB OCMEMn + 0x5 + + + size32k + 32KB OCMEMn + 0x6 + + + size64kb + 64KB OCMEMn + 0x7 + + + size128kb + 128KB OCMEMn + 0x8 + + + size256kb + 256KB OCMEMn + 0x9 + + + size512kb + 512KB OCMEMn + 0xA + + + size1mb + 1MB OCMEMn + 0xB + + + size2mb + 2MB OCMEMn + 0xC + + + size4mb + 4MB OCMEMn + 0xD + + + size8mb + 8MB OCMEMn + 0xE + + + size16mb + 16MB OCMEMn + 0xF + + + + + OCMSZH + OCMSZH + 28 + 1 + read-only + + + powerof2 + OCMEMn is a power-of-2 capacity. + 0 + + + nonpowerof2 + OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. + 0x1 + + + + + OCMECC + OCMECC + 29 + 1 + read-only + + + exclude + OCMEMn does not have ECC support. + 0 + + + include + OCMEMn has ECC support. + 0x1 + + + + + V + V + 31 + 1 + read-only + + + exclude + OCMEMn is not present. + 0 + + + include + OCMEMn is present. + 0x1 + + + + + + + OCMDR5 + On-Chip Memory Descriptor Register + 0x414 + 32 + read-only + 0xE4041000 + 0xFFFFFFFF + + + OCMPU + OCMPU + 12 + 1 + read-only + + + OCMT + OCMT + 13 + 3 + read-only + + + sysram + OCMEMn is a System RAM. + 0 + + + rom + OCMEMn is a ROM. + 0x3 + + + flash + OCMEMn is a Program Flash. + 0x4 + + + + + OCMW + OCMW + 17 + 3 + read-only + + + bit32 + OCMEMn 32-bits wide + 0x2 + + + bit64 + OCMEMn 64-bits wide + 0x3 + + + bit128 + OCMEMn 128-bits wide + 0x4 + + + bit256 + OCMEMn 256-bits wide + 0x5 + + + + + OCMSZ + OCMSZ + 24 + 4 + read-only + + + zero + no OCMEMn + 0 + + + size1kb + 1KB OCMEMn + 0x1 + + + size2kb + 2KB OCMEMn + 0x2 + + + size4kb + 4KB OCMEMn + 0x3 + + + size8kb + 8KB OCMEMn + 0x4 + + + size16kb + 16KB OCMEMn + 0x5 + + + size32k + 32KB OCMEMn + 0x6 + + + size64kb + 64KB OCMEMn + 0x7 + + + size128kb + 128KB OCMEMn + 0x8 + + + size256kb + 256KB OCMEMn + 0x9 + + + size512kb + 512KB OCMEMn + 0xA + + + size1mb + 1MB OCMEMn + 0xB + + + size2mb + 2MB OCMEMn + 0xC + + + size4mb + 4MB OCMEMn + 0xD + + + size8mb + 8MB OCMEMn + 0xE + + + size16mb + 16MB OCMEMn + 0xF + + + + + OCMSZH + OCMSZH + 28 + 1 + read-only + + + powerof2 + OCMEMn is a power-of-2 capacity. + 0 + + + nonpowerof2 + OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. + 0x1 + + + + + OCMECC + OCMECC + 29 + 1 + read-only + + + exclude + OCMEMn does not have ECC support. + 0 + + + include + OCMEMn has ECC support. + 0x1 + + + + + V + V + 31 + 1 + read-only + + + exclude + OCMEMn is not present. + 0 + + + include + OCMEMn is present. + 0x1 + + + + + + + SECURE_IRQ + Secure Interrupt Request + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEC_IRQ_ARG + Secure Interrupt Argument + 0 + 32 + read-write + + + + + 4 + 0x4 + UID[%s] + Unique ID n + 0x810 + 32 + read-only + 0 + 0 + + + UID0 + Unique ID 0 + 0 + 32 + read-only + + + + + SID + System ID + 0x820 + 32 + read-only + 0 + 0 + + + QI + Qual Info + 0 + 2 + read-only + + + industrial + Industrial + 0x1 + + + auto + Auto + 0x3 + + + + + SIREV + Silicon Revision + 2 + 2 + read-only + + + spin2nd + 2nd Major Spin + 0x1 + + + spin1st + 1st Major Spin + 0x2 + + + init + Initial mask set + 0x3 + + + + + PINID + Pin Identification + 4 + 3 + read-only + + + pin40 + 40HVQFN + 0x2 + + + pin48 + 48HVQFN + 0x3 + + + pin56 + 56HVQFN + 0x4 + + + + + CMP + CMP Presence + 7 + 1 + read-only + + + exclude + No CMP + 0 + + + include + CMP present + 0x1 + + + + + FLXIO + FlexIO Presence + 8 + 1 + read-only + + + exclude + No FlexIO + 0 + + + include + FlexIO present + 0x1 + + + + + VREF + VREF Presence + 9 + 1 + read-only + + + exclude + No VREF + 0 + + + include + VREF present + 0x1 + + + + + I3C + I3C Presence + 10 + 1 + read-only + + + exclude + No I3C + 0 + + + include + I3C present + 0x1 + + + + + CAN + CAN Presence + 11 + 1 + read-only + + + exclude + No CAN + 0 + + + include + CAN present + 0x1 + + + + + SEC + Secure Enclave Presence + 12 + 1 + read-only + + + exclude + No Secure Enclave + 0 + + + include + Secure Enclave present + 0x1 + + + + + RAMSZ + RAM Size + 13 + 3 + read-only + + + size96k + 96 KB + 0 + + + size128k + 128 KB + 0x7 + + + + + FLSZ + Flash Size + 16 + 4 + read-only + + + size1mb + 1 MB + 0xD + + + size512kb + 512 KB + 0xF + + + + + BLEF + Bluetooth LE Feature + 20 + 4 + read-only + + + noble + No Bluetooth LE present + 0 + + + v5dot1 + Bluetooth LE 5.1 + 0x1 + + + v5dot2 + Bluetooth LE 5.2 + 0x2 + + + v5dot3 + Bluetooth LE 5.3 + 0x3 + + + upgr + Bluetooth LE Upgrade + 0xF + + + + + RADIOF + Radio Feature + 24 + 4 + read-only + + + zero + 802.15.4 + 0 + + + one + Bluetooth LE + 0x1 + + + two + Bluetooth LE + 15.4 + 0x2 + + + + + FAMID + Family ID + 28 + 4 + read-only + + + k4w1 + K4W1 + 0 + + + + + + + + + SMSCM + SMSCM + SMSCM + 0x40015000 + + 0 + 0xC04 + registers + + + + DBGEN + Debug Enable + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBGEN + Invasive Debug Enable (DFF3 bitfield) + 0 + 3 + read-write + + read + + r000 + Invasive Debug Disabled. + 0 + + + + write + + w2s + W2S - Enable Invasive Debug. + 0x2 + + + w5c + W5C - Disable Invasive Debug. + 0x5 + + + + + SPIDEN + Secure Invasive Debug Enable (DFF3 bitfield) + 4 + 3 + read-write + + read + + r000 + Secure Invasive Debug Disabled. + 0 + + + + write + + w2s + W2S - Enable Secure Invasive Debug. + 0x2 + + + w5c + W5C - Disable Secure Invasive Debug. + 0x5 + + + + + NIDEN + Non-Invasive Debug Enable (DFF3 bitfield) + 8 + 3 + read-write + + read + + r000 + Non-Invasive Debug Disabled. + 0 + + + + write + + w2s + W2S - Enable Non-Invasive Debug. + 0x2 + + + w5c + W5C - Disable Non-Invasive Debug. + 0x5 + + + + + SPNIDEN + Secure Non-Invasive Debug Enable (DFF3 bitfield) + 12 + 3 + read-write + + read + + r000 + Secure Non-Invasive Debug Disabled. + 0 + + + + write + + w2s + W2S - Enable Secure Non-Invasive Debug. + 0x2 + + + w5c + W5C - Disable Secure Non-Invasive Debug. + 0x5 + + + + + ALTDBGEN + Alternate Invasive Debug Enable (DFF3 bitfield) + 16 + 3 + read-write + + read + + r000 + Alternate Invasive Debug Disabled. + 0 + + + + write + + w2s + W2S - Enable Alternate Invasive Debug. + 0x2 + + + w5c + W5C - Disable Alternate Invasive Debug. + 0x5 + + + + + ALTEN + Alternate Enable (DFF3 bitfield) + 20 + 3 + read-write + + read + + r000 + Alternate Disabled. + 0 + + + + write + + w2s + W2S - Enable Alternate. + 0x2 + + + w5c + W5C - Disable Alternate. + 0x5 + + + + + + + DBGEN_B + Debug Enable Complement + 0x4 + 32 + read-write + 0x222222 + 0xFFFFFFFF + + + DBGEN_B + Invasive Debug Enable Complement (DFF3 bitfield) + 0 + 3 + read-write + + read + + r000 + Invasive Debug Enabled. + 0 + + + + write + + w2s + W2S - Disable Invasive Debug. + 0x2 + + + w5c + W5C - Enable Invasive Debug. + 0x5 + + + + + SPIDEN_B + Secure Invasive Debug Enable - Complement (DFF3 bitfield) + 4 + 3 + read-write + + read + + r000 + Secure Invasive Debug Enabled. + 0 + + + + write + + w2s + W2S - Disable Secure Invasive Debug. + 0x2 + + + w5c + W5C - Enable Secure Invasive Debug. + 0x5 + + + + + NIDEN_B + Non-Invasive Debug Enable Complement (DFF3 bitfield) + 8 + 3 + read-write + + read + + r000 + Non-Invasive Debug Enabled. + 0 + + + + write + + w2s + W2S - Disable Non-Invasive Debug. + 0x2 + + + w5c + W5C - Enable Non-Invasive Debug. + 0x5 + + + + + SPNIDEN_B + Secure Non-Invasive Debug Enable Complement (DFF3 bitfield) + 12 + 3 + read-write + + read + + r000 + Secure Non-Invasive Debug Enabled. + 0 + + + + write + + w2s + W2S - Disable Secure Non-Invasive Debug. + 0x2 + + + w5c + W5C - Enable Secure Non-Invasive Debug. + 0x5 + + + + + ALTDBGEN_B + Alternate Invasive Debug Enable Complement (DFF3 bitfield) + 16 + 3 + read-write + + read + + r000 + Alternate Invasive Debug Enabled. + 0 + + + + write + + w2s + W2S - Alternate Disable Invasive Debug. + 0x2 + + + w5c + W5C - Alternate Enable Invasive Debug. + 0x5 + + + + + ALTEN_B + Alternate Enable Complement (DFF3 bitfield) + 20 + 3 + read-write + + read + + r000 + Alternrate Enabled. + 0 + + + + write + + w2s + W2S - Disable Alternate. + 0x2 + + + w5c + W5C - Enable Alternate. + 0x5 + + + + + + + DBGEN_LOCK + Debug Enable Lock + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + Lock (DFF3 bitfield) + 0 + 3 + read-write + + write + + wlock_0 + Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK]. + 0 + + + wlock_1 + Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK]. + 0x1 + + + wlock_2 + Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK]. + 0x2 + + + wlock_3 + Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK]. + 0x3 + + + wlock_4 + Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK]. + 0x4 + + + w5c + When DBGEN_LOCK[LOCK] is locked, DBGEN_LOCK[LOCK] cannot be unlocked with a write of 101b to this field. When DBGEN_LOCK[LOCK] is unlocked, a write of 101b to this field, DBGEN_LOCK[LOCK] remains unlocked and the DBGEN[DBGEN, SPIDEN, NIDEN, SPNIDEN],DBGEN_B[DBGEN_B, SPIDEN_B, NIDEN_B, SPNIDEN_B] fields remain writeable. + 0x5 + + + wlock_7 + Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK]. + 0x7 + + + + + ALT_DBGEN_LOCK + Alternate Lock (DFF3 bitfield) + 16 + 3 + read-write + + write + + wlock_0 + Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK]. + 0 + + + wlock_1 + Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK]. + 0x1 + + + wlock_2 + Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK]. + 0x2 + + + wlock_3 + Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK]. + 0x3 + + + wlock_4 + Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK]. + 0x4 + + + w5c + When ALT_DBGEN_LOCK is locked, ALT_DBGEN_LOCK cannot be unlocked with a write of 101b to this field. When ALT_DBGEN_LOCK is unlocked, a write of 101b to this field, ALT_DBGEN_LOCK remains unlocked and DBGEN/DBGEN_B remains writeable. + 0x5 + + + wlock_7 + Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK]. + 0x7 + + + + + ALT_EN_LOCK + Alternate Lock (DFF3 bitfield) + 20 + 3 + read-write + + write + + wlock_0 + Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK]. + 0 + + + wlock_1 + Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK]. + 0x1 + + + wlock_2 + Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK]. + 0x2 + + + wlock_3 + Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK]. + 0x3 + + + wlock_4 + Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK]. + 0x4 + + + w5c + f When ALT_EN_LOCK is locked, ALT_EN_LOCK cannot be unlocked with a write of 101b to this field. When ALT_EN_LOCK is unlocked, a write of 101b to this field, ALT_EN_LOCK remains unlocked and ALTEN/ALTEN_B remains writeable. + 0x5 + + + wlock_7 + Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK]. + 0x7 + + + + + + + DBG_AUTH_BEACON + Debug Authentication Beacon + 0x20 + 32 + read-write + 0 + 0 + + + AUTH_BEACON + Authentication Beacon + 0 + 16 + read-write + + + CREDENTIAL_BEACON + Credential Beacon + 16 + 16 + read-write + + + + + LIFECYCLE + Lifecycle Fuse Word + 0x30 + 32 + read-only + 0 + 0xFF030FF + + + CLC + Converged Lifecycle + 0 + 8 + read-only + + + blank + BLANK + 0 + + + fab + NXP Fab + 0x1 + + + prov + NXP Provisioned + 0x3 + + + open + OEM Open + 0x7 + + + swc + OEM Secure World Closed + 0xF + + + closed + OEM Closed + 0x1F + + + oemr + OEM Return + 0x3F + + + ret + NXP Return + 0x7F + + + locked + OEM Locked + 0x9F + + + brick + BRICK + #11xxxxxx + + + + + DBG_EN_LOCK + Debug Enable Lock + 8 + 1 + read-only + + + zero + The debug access control registers remain open when jumping to customer code. + 0 + + + one + The debug access control registers are write-locked before jumping to customer code. + 0x1 + + + + + DBG_AUTH_DIS + Debug Authentication Disabled + 9 + 1 + read-only + + + zero + Debug Authentication enabled. + 0 + + + one + Debug Authentication disabled. + 0x1 + + + + + TZM_EN + Trust Zone Mode Enable + 10 + 1 + read-only + + + zero + TZ-M is disabled by default, can be enabled by software. + 0 + + + one + TZ-M is enabled. + 0x1 + + + + + DICE_EN + DICE Enable + 11 + 1 + read-only + + + zero + DICE is disabled by default. + 0 + + + one + DICE is enabled. + 0x1 + + + + + SERIAL_DIS + Serial Download Disabled + 14 + 1 + read-only + + + zero + Serial download path is enabled. + 0 + + + one + Serial download path is disabled. + 0x1 + + + + + WAKEUP_DIS + Wakeup Disabled + 15 + 1 + read-only + + + zero + Boot-ROM LP wakup is enabled. + 0 + + + one + Boot-ROM LP wakup is disabled. + 0x1 + + + + + CTRK_REVOKE + Revocation indicator from OEM Firmware Authentication Public Key + 16 + 4 + read-only + + + SWD_ID + Serial Wire Debug Instance ID + 28 + 4 + read-only + + + + + LIFECYCLE_B + Lifecycle Fuse Word Complement + 0x34 + 32 + read-only + 0 + 0xFF030FF + + + CLC_B + Converged Lifecycle Complement + 0 + 8 + read-only + + + brick + BRICK + #00xxxxxx + + + locked + OEM Locked + 0x60 + + + ret + NXP Return + 0x80 + + + oemr + OEM Return + 0xC0 + + + closed + OEM Closed + 0xE0 + + + swc + OEM Secure World Closed + 0xF0 + + + open + OEM Open + 0xF8 + + + prov + NXP Provisioned + 0xFC + + + fab + NXP Fab + 0xFE + + + blank + BLANK + 0xFF + + + + + DBG_EN_LOCK_B + Debug Enable Lock Complement + 8 + 1 + read-only + + + zero + The debug access control registers are write-locked before jumping to customer code. + 0 + + + one + The debug access control registers remain open when jumping to customer code. + 0x1 + + + + + DBG_AUTH_DIS_B + Debug Authentication Disabled Complement + 9 + 1 + read-only + + + zero + Debug Authentication disabled. + 0 + + + one + Debug Authentication enabled. + 0x1 + + + + + TZM_EN_B + Trust Zone Mode Enable Complement + 10 + 1 + read-only + + + zero + TZ-M is enabled. + 0 + + + one + TZ-M is disabled by default, can be enabled by software. + 0x1 + + + + + DICE_EN_B + DICE Enable Complement + 11 + 1 + read-only + + + zero + DICE is enabled. + 0 + + + one + DICE is disabled by default. + 0x1 + + + + + SERIAL_DIS_B + Serial Download Disabled Complement + 14 + 1 + read-only + + + zero + Serial download path is disabled. + 0 + + + one + Serial download path is enabled. + 0x1 + + + + + WAKEUP_DIS_B + Wakeup Disabled Complement + 15 + 1 + read-only + + + zero + Boot-ROM LP wakup is disabled. + 0 + + + one + Boot-ROM LP wakup is enabled. + 0x1 + + + + + CTRK_REVOKE_B + Revocation indicator from OEM Firmware Authentication Public Key Complement + 16 + 4 + read-only + + + SWD_ID_B + Serial Wire Debug Instance ID Complement + 28 + 4 + read-only + + + + + ROM_LOCKOUT + ROM Lockout Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROMWA + ROM Watermark Address + 4 + 18 + read-write + + + REGLOCK + ROM_LOCKOUT Register Lock (DFF3 bitfield) + 29 + 3 + read-write + + write + + wlock_0 + Lock ROM_LOCKOUT register. + 0 + + + wlock_1 + Lock ROM_LOCKOUT register. + 0x1 + + + wlock_2 + Lock ROM_LOCKOUT register. + 0x2 + + + wlock_3 + Lock ROM_LOCKOUT register. + 0x3 + + + wlock_4 + Lock ROM_LOCKOUT register. + 0x4 + + + w5c + Writing this value has no effect. + 0x5 + + + wlock_7 + Lock ROM_LOCKOUT register. + 0x7 + + + + + + + SCTR + Security Counter Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA32 + Data, 32 bits + 0 + 32 + read-write + + + + + SCTRP1 + Security Counter Plus 1 Register + 0x104 + 32 + write-only + 0 + 0xFFFFFFFF + + + DONTCARE32 + Don't Care Data, 32 bits + 0 + 32 + write-only + + + + + SCTRM1 + Security Counter Minus 1 Register + 0x10C + 32 + write-only + 0 + 0xFFFFFFFF + + + DONTCARE32 + Don't Care Data, 32 bits + 0 + 32 + write-only + + + + + SCTRPX + Security Counter Plus X Register + 0x114 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA32 + Data, 32 bits + 0 + 32 + write-only + + + + + SCTRMX + Security Counter Minus X Register + 0x11C + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA32 + Data, 32 bits + 0 + 32 + write-only + + + + + OCMDR0 + On-Chip Memory Descriptor Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + OCMCF0 + OCMEM Control Field 0 + 0 + 4 + read-write + + + OCMCF1 + OCMEM Control Field 1 + 4 + 4 + read-write + + + OCMCF2 + OCMEM Control Field 2 + 8 + 4 + read-write + + + RO + Read-Only + 16 + 1 + read-write + + + zero + Writes to the OCMDRn[11:0] are allowed + 0 + + + one + Writes to the OCMDRn[11:0] are ignored + 0x1 + + + + + + + OCMDR2 + On-Chip Memory Descriptor Register + 0x408 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + OCMCF0 + OCMEM Control Field 0 + 0 + 4 + read-write + + + RO + Read-Only + 16 + 1 + read-write + + + zero + Writes to the OCMDRn[11:0] are allowed + 0 + + + one + Writes to the OCMDRn[11:0] are ignored + 0x1 + + + + + + + OCMDR3 + On-Chip Memory Descriptor Register + 0x40C + 32 + read-write + 0x3 + 0xFFFFFFFF + + + OCMCF0 + OCMEM Control Field 0 + 0 + 4 + read-write + + + RO + Read-Only + 16 + 1 + read-write + + + zero + Writes to the OCMDRn[11:0] are allowed + 0 + + + one + Writes to the OCMDRn[11:0] are ignored + 0x1 + + + + + + + OCMDR5 + On-Chip Memory Descriptor Register + 0x414 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + OCMCF0 + OCMEM Control Field 0 + 0 + 4 + read-write + + + RO + Read-Only + 16 + 1 + read-write + + + zero + Writes to the OCMDRn[11:0] are allowed + 0 + + + one + Writes to the OCMDRn[11:0] are ignored + 0x1 + + + + + + + OCMECR + On-Chip Memory ECC Control Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENCR + Enable RAM ECC Non-correctable Reporting + 0 + 1 + read-write + + + disable + Non-correctable reporting disabled + 0 + + + enable + Non-correctable reporting enabled + 0x1 + + + + + E1BR + Enable RAM ECC 1 Bit Reporting + 8 + 1 + read-write + + + disable + 1-bit reporting disabled + 0 + + + enable + 1-bit reporting enabled + 0x1 + + + + + + + OCMEIR + On-Chip Memory ECC Interrupt Register + 0x488 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENCERRN + ECC Non-correctable Error OCRAMn + 0 + 8 + read-write + oneToClear + + + E1BERRN + ECC 1-bit Error OCRAMn + 8 + 8 + read-write + oneToClear + + + EELOC + ECC Error Location + 24 + 4 + read-only + + + non_correctable_ocram0 + non-correctable on OCRAM0 + 0 + + + non_correctable_ocram1 + non-correctable on OCRAM1 + 0x1 + + + non_correctable_ocram2 + non-correctable on OCRAM2 + 0x2 + + + non_correctable_ocram3 + non-correctable on OCRAM3 + 0x3 + + + non_correctable_ocram4 + non-correctable on OCRAM4 + 0x4 + + + non_correctable_ocram5 + non-correctable on OCRAM5 + 0x5 + + + non_correctable_ocram6 + non-correctable on OCRAM6 + 0x6 + + + non_correctable_ocram7 + non-correctable on OCRAM7 + 0x7 + + + correctable_ocram0 + 1-bit correctable on OCRAM0 + 0x8 + + + correctable_ocram1 + 1-bit correctable on OCRAM1 + 0x9 + + + correctable_ocram2 + 1-bit correctable on OCRAM2 + 0xA + + + correctable_ocram3 + 1-bit correctable on OCRAM3 + 0xB + + + correctable_ocram4 + 1-bit correctable on OCRAM4 + 0xC + + + correctable_ocram5 + 1-bit correctable on OCRAM5 + 0xD + + + correctable_ocram6 + 1-bit correctable on OCRAM6 + 0xE + + + correctable_ocram7 + 1-bit correctable on OCRAM7 + 0xF + + + + + VALID + Valid ECC Error Location field + 31 + 1 + read-only + + + not_valid + ECC Error Location field is not valid + 0 + + + valid + ECC Error Location field is valid + 0x1 + + + + + + + OCMFAR + On-Chip Memory Fault Address Register + 0x490 + 32 + read-only + 0 + 0xFFFFFFFF + + + EFADD + ECC Fault Address + 0 + 32 + read-only + + + + + OCMFTR + On-Chip Memory Fault Attribute Register + 0x494 + 32 + read-only + 0 + 0xFFFFFFFF + + + EFPRT + On-Chip Memory ECC Fault Protection + 0 + 4 + read-only + + + EFMS + On-Chip Memory ECC Fault Master Size + 4 + 3 + read-only + + + size_8bit + 8-bit size + 0 + + + size_16bit + 16-bit size + 0x1 + + + size_32bit + 32-bit size + 0x2 + + + size_64bit + 64-bit size + 0x3 + + + + + EFW + On-Chip Memory ECC Fault Write + 7 + 1 + read-only + + + not_write_bus_cycle + Last captured ECC event was not a write bus cycle + 0 + + + write_bus_cycle + Last captured ECC event was a write bus cycle + 0x1 + + + + + EFMST + On-Chip Memory ECC Fault Master Number + 8 + 8 + read-only + + + EFSYN + On-Chip Memory ECC Fault Syndrome + 16 + 8 + read-only + + + + + OCMFDRH + On-Chip Memory ECC Fault Data High Register + 0x498 + 32 + read-only + 0 + 0xFFFFFFFF + + + EFDH + On-Chip Memory ECC Fault Data High + 0 + 32 + read-only + + + + + OCMFDRL + On-Chip Memory ECC Fault Data Low Register + 0x49C + 32 + read-only + 0 + 0xFFFFFFFF + + + EFDL + On-Chip Memory ECC Fault Data Low + 0 + 32 + read-only + + + + + CPCR + Core Platform Control Register + 0xC00 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + AXBS0_RREN + AXBS0 Round Robin Enable + 0 + 1 + read-write + + + zero + AXBS0 in fixed priority arbitration mode at reset. + 0 + + + one + AXBS0 in round robin arbitration mode at reset. + 0x1 + + + + + + + + + SPC0 + SPC + SPC + 0x40016000 + + 0 + 0x600 + registers + + + SPC0 + 21 + + + + VERID + Version ID + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + STANDARD + Standard features + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + SC + Status Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUSY + SPC Busy Status Flag + 0 + 1 + read-only + + + BUSY_NO + Not busy + 0 + + + BUSY_YES + Busy + 0x1 + + + + + SPC_LP_REQ + SPC Power Mode Configuration Status Flag + 1 + 1 + read-write + oneToClear + + read + + ACTIVE + SPC is in Active mode; the ACTIVE_CFG register has control + 0 + + + LOW_POWER + All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + 0x1 + + + + + SPC_LP_MODE + Power Domain Low-Power Mode Request + 4 + 4 + read-only + + + MODE0 + Sleep mode with system clock running + 0 + + + MODE1 + SLEEP with system clock off + 0x1 + + + MODE2 + DSLEEP with system clock off + 0x2 + + + MODE4 + PDOWN with system clock off + 0x4 + + + MODE8 + DPDOWN with system clock off + 0x8 + + + + + ISO_CLR + Isolation Clear Flags + 16 + 3 + read-write + oneToClear + + + SWITCH_STATE + Power Switch State + 31 + 1 + read-only + + + OFF + Off + 0 + + + ON + On + 0x1 + + + + + + + CNTRL + SPC Regulator Control + 0x14 + 32 + read-writeOnce + 0x7 + 0xFFFFFFFF + + + CORELDO_EN + LDO_CORE Regulator Enable + 0 + 1 + read-writeOnce + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SYSLDO_EN + LDO_SYS Regulator Enable + 1 + 1 + read-writeOnce + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DCDC_EN + DCDC_CORE Regulator Enable + 2 + 1 + read-writeOnce + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + + + LPREQ_CFG + Low-Power Request Configuration + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LPREQOE + Low-Power Request Output Enable + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + LPREQPOL + Low-Power Request Output Pin Polarity Control + 1 + 1 + read-write + + + HIGH + High + 0 + + + LOW + Low + 0x1 + + + + + LPREQOV + Low-Power Request Output Override + 2 + 2 + read-write + + + FORCE_NO + Not forced + 0 + + + FORCE_LOW + Forced low (ignore LPREQPOL settings) + 0x2 + + + FORCE_HIGH + Forced high (ignore LPREQPOL settings) + 0x3 + + + + + + + CFG + SPC Configuration + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTG_PWSWTCH_SLEEP_EN + Integrated Power Switch Sleep Enable + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INTG_PWSWTCH_WKUP_EN + Integrated Power Switch Wake-up Enable + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INTG_PWSWTCH_SLEEP_ACTIVE_EN + Integrated Power Switch Active Enable + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INTG_PWSWTCH_WKUP_ACTIVE_EN + Integrated Power Switch Wake-up Enable + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + + + 3 + 0x4 + PD_STATUS[%s] + SPC Power Domain Mode Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWR_REQ_STATUS + Power Request Status Flag + 0 + 1 + read-only + + + REQ_NO + Did not request + 0 + + + REQ_YES + Requested + 0x1 + + + + + PD_LP_REQ + Power Domain Low Power Request Flag + 4 + 1 + read-write + oneToClear + + + REQ_NO + Did not request + 0 + + + REQ_YES + Requested + 0x1 + + + + + LP_MODE + Power Domain Low Power Mode Request + 8 + 4 + read-only + + + MODE0 + SLEEP with system clock running + 0 + + + MODE1 + SLEEP with system clock off + 0x1 + + + MODE2 + DSLEEP with system clock off + 0x2 + + + MODE4 + PDOWN with system clock off + 0x4 + + + MODE8 + DPDOWN with system clock off + 0x8 + + + + + + + SRAMCTL + SRAM Control + 0x40 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + VSM + Voltage Select Margin + 0 + 2 + read-write + + + VSM1 + 1.0 V + 0x1 + + + VSM2 + 1.1 V + 0x2 + + + VSM3 + SRAM configured for 1.1 V operation + 0x3 + + + + + REQ + SRAM Voltage Update Request + 30 + 1 + read-write + + + REQ_NO + Do not request + 0 + + + REQ_YES + Request + 0x1 + + + + + ACK + SRAM Voltage Update Request Acknowledge + 31 + 1 + read-only + + + ACK_NO + Not acknowledged + 0 + + + ACK_YES + Acknowledged + 0x1 + + + + + + + WAKEUP + General Purpose Wake-up + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKEUP + Wake-up + 0 + 32 + read-write + + + + + ACTIVE_CFG + Active Power Mode Configuration + 0x100 + 32 + read-write + 0x3F100E15 + 0xFFFFFFFF + + + CORELDO_VDD_DS + LDO_CORE VDD Drive Strength + 0 + 1 + read-write + + + LOW + Low + 0 + + + NORMAL + Normal + 0x1 + + + + + CORELDO_VDD_LVL + LDO_CORE VDD Regulator Voltage Level + 2 + 2 + read-write + + + MID + Regulate to mid voltage (1.0 V) + 0x1 + + + NORMAL + Regulate to normal voltage (1.1 V) + 0x2 + + + SAFE + Regulate to safe-mode voltage (1.15 V) + 0x3 + + + + + SYSLDO_VDD_DS + LDO_SYS VDD Drive Strength + 4 + 1 + read-write + + + LOW + Low + 0 + + + NORMAL + Normal + 0x1 + + + + + SYSLDO_VDD_LVL + LDO_SYS VDD Regulator Voltage Level + 6 + 1 + read-write + + + NORMAL + Normal voltage (1.8 V) + 0 + + + OVER + Overdrive voltage (2.5 V) + 0x1 + + + + + DCDC_VDD_DS + DCDC VDD Drive Strength + 8 + 2 + read-write + + + LOW + Low + 0x1 + + + NORMAL + Normal + 0x2 + + + + + DCDC_VDD_LVL + DCDC VDD Regulator Voltage Level + 10 + 2 + read-write + + + DCDC00 + Low undervoltage (1.25 V) + 0 + + + DCDC01 + Midvoltage (1.35 V) + 0x1 + + + DCDC10 + Normal voltage (2.5 V) + 0x2 + + + DCDC11 + Safe-mode voltage (1.8 V) + 0x3 + + + + + GLITCH_DETECT_DISABLE + VDD Core Glitch Detect Disable + 12 + 1 + read-write + + + DISABLED + VDD Core Low Voltage Glitch Detect enabled + 0 + + + ENABLED + VDD Core Low Voltage Glitch Detect disabled + 0x1 + + + + + LPBUFF_EN + CMP Bandgap Buffer Enable + 18 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + BGMODE + Bandgap Mode + 20 + 2 + read-write + + + BGMODE0 + Bandgap disabled + 0 + + + BGMODE01 + Bandgap enabled, buffer disabled + 0x1 + + + BGMODE10 + Bandgap enabled, buffer enabled + 0x2 + + + + + CORE_LVDE + Core Low-Voltage Detection Enable + 24 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SYS_LVDE + System Low-Voltage Detection Enable + 25 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + IO_LVDE + IO Low-Voltage Detection Enable + 26 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + CORE_HVDE + Core High-Voltage Detection Enable + 27 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SYS_HVDE + System High-Voltage Detection Enable + 28 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + IO_HVDE + IO High-Voltage Detection Enable + 29 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + + + LP_CFG + Low-Power Mode Configuration + 0x104 + 32 + read-write + 0x21D04 + 0xFFFFFFFF + + + CORELDO_VDD_DS + LDO_CORE VDD Drive Strength + 0 + 1 + read-write + + + LOW + Low + 0 + + + NORMAL + Normal + 0x1 + + + + + CORELDO_VDD_LVL + LDO_CORE VDD Regulator Voltage Level + 2 + 2 + read-write + + + UNDER + Under voltage (0.95 V) + 0 + + + MID + Mid voltage (1.0 V) + 0x1 + + + NORMAL + Normal voltage (1.1 V) + 0x2 + + + SAFE + Safe-mode voltage (1.15 V) + 0x3 + + + + + SYSLDO_VDD_DS + LDO_SYS VDD Drive Strength + 4 + 1 + read-write + + + LOW + Low + 0 + + + NORMAL + Normal + 0x1 + + + + + DCDC_VDD_DS + DCDC VDD Drive Strength + 8 + 2 + read-write + + + PULSE + Pulse refresh + 0 + + + LOW + Low + 0x1 + + + NORMAL + Normal + 0x2 + + + + + DCDC_VDD_LVL + DCDC VDD Regulator Voltage Level + 10 + 2 + read-write + + + VDD00 + Low under voltage (1.25 V) + 0 + + + VDD01 + Mid voltage (1.35 V) + 0x1 + + + VDD10 + Normal voltage (2.5 V) + 0x2 + + + VDD11 + Safe-mode voltage (1.8 V) + 0x3 + + + + + GLITCH_DETECT_DISABLE + VDD Core Glitch Detect Disable + 12 + 1 + read-write + + + ENABLE + Enable + 0 + + + DISABLE + Disable + 0x1 + + + + + COREVDD_IVS_EN + CORE VDD Internal Voltage Scaling (IVS) Enable + 17 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + LPBUFF_EN + CMP Bandgap Buffer Enable + 18 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + BGMODE + Bandgap Mode + 20 + 2 + read-write + + + BGMODE0 + Bandgap disabled + 0 + + + BGMODE01 + Bandgap enabled, buffer disabled + 0x1 + + + BGMODE10 + Bandgap enabled, buffer enabled + 0x2 + + + + + LP_IREFEN + Low-Power IREF Enable + 23 + 1 + read-write + + + DISABLE + Disable for power saving in Deep Power Down mode + 0 + + + ENABLE + Enable + 0x1 + + + + + CORE_LVDE + Core Low Voltage Detect Enable + 24 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SYS_LVDE + System Low Voltage Detect Enable + 25 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + IO_LVDE + IO Low Voltage Detect Enable + 26 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + CORE_HVDE + Core High Voltage Detect Enable + 27 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SYS_HVDE + System High Voltage Detect Enable + 28 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + IO_HVDE + IO High Voltage Detect Enable + 29 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + + + LPWKUP_DELAY + Low Power Wake-Up Delay + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPWKUP_DELAY + Low-Power Wake-Up Delay + 0 + 16 + read-write + + + + + ACTIVE_VDELAY + Active Voltage Trim Delay + 0x124 + 32 + read-write + 0xC8 + 0xFFFFFFFF + + + ACTIVE_VDELAY + Active Voltage Delay + 0 + 16 + read-write + + + + + VD_STAT + Voltage Detect Status Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + COREVDD_LVDF + Core VDD Low-Voltage Detect Flag + 0 + 1 + read-write + oneToClear + + + DISABLED + Low-voltage event not detected + 0 + + + ENABLED + Low-voltage event detected + 0x1 + + + + + SYSVDD_LVDF + System VDD Low-Voltage Detect Flag + 1 + 1 + read-write + oneToClear + + + DISABLED + Low-voltage event not detected + 0 + + + ENABLED + Low-voltage event detected + 0x1 + + + + + IOVDD_LVDF + IO VDD Low-Voltage Detect Flag + 2 + 1 + read-write + oneToClear + + + DISABLED + Low-voltage event not detected + 0 + + + ENABLED + Low-voltage event detected + 0x1 + + + + + COREVDD_HVDF + Core VDD High-Voltage Detect Flag + 4 + 1 + read-write + oneToClear + + + DISABLED + High-voltage event not detected + 0 + + + ENABLED + High-voltage event detected + 0x1 + + + + + SYSVDD_HVDF + System VDD High-Voltage Detect Flag + 5 + 1 + read-write + oneToClear + + + DISABLED + High-voltage event not detected + 0 + + + ENABLED + High-voltage event detected + 0x1 + + + + + IOVDD_HVDF + IO VDD High-Voltage Detect Flag + 6 + 1 + read-write + oneToClear + + + DISABLED + High-voltage event not detected + 0 + + + ENABLED + High-voltage event detected + 0x1 + + + + + + + VD_CORE_CFG + Core Voltage Detect Configuration Register + 0x134 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + LVDRE + Core VDD Low-Voltage Detect Reset Enable + 0 + 1 + read-write + + + DISABLED + COREVDD_LVDF does not generate hardware reset + 0 + + + ENABLED + COREVDD_LVDF does generate hardware reset + 0x1 + + + + + LVDIE + Core VDD Low-Voltage Detect Interrupt Enable + 1 + 1 + read-write + + + DISABLED + COREVDD_LVDF does not generate hardware interrupt (user polling) + 0 + + + ENABLED + COREVDD_LVDF does generate hardware interrupt + 0x1 + + + + + HVDRE + Core VDD High-Voltage Detect Reset Enable + 2 + 1 + read-write + + + DISABLED + COREVDD_HVDF does not generate hardware reset + 0 + + + ENABLED + COREVDD_HVDF does generate hardware reset + 0x1 + + + + + HVDIE + Core VDD High-Voltage Detect Interrupt Enable + 3 + 1 + read-write + + + DISABLED + COREVDD_HVDF does not generate hardware interrupt (user polling) + 0 + + + ENABLED + COREVDD_HVDF does generate hardware interrupt + 0x1 + + + + + LOCK + CORE Voltage Detect Reset Enable Lock Bit + 16 + 1 + read-write + + + DISABLED + Writes to VD_CORE_CGF[LVDRE] and VD_CORE_CFG[HVDRE] are allowed. + 0 + + + ENABLED + Writes to VD_CORE_CGF[LVDRE] and VD_CORE_CFG[HVDRE] are ignored. + 0x1 + + + + + + + VD_SYS_CFG + System Voltage Detect Configuration Register + 0x138 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + LVDRE + System VDD Low-Voltage Detect Reset Enable + 0 + 1 + read-write + + + DISABLED + SYSVDD_LVDF does not generate hardware reset + 0 + + + ENABLED + SYSVDD_LVDF does generate hardware reset + 0x1 + + + + + LVDIE + System VDD Low-Voltage Detect Interrupt Enable + 1 + 1 + read-write + + + DISABLED + SYSVDD_LVDF does not generate hardware interrupt (user polling) + 0 + + + ENABLED + SYSVDD_LVDF does generate hardware interrupt + 0x1 + + + + + HVDRE + System VDD High-Voltage Detect Reset Enable + 2 + 1 + read-write + + + DISABLED + SYSVDD_HVDF does not generate hardware reset + 0 + + + ENABLED + SYSVDD_HVDF does generate hardware reset + 0x1 + + + + + HVDIE + System VDD High-Voltage Detect Interrupt Enable + 3 + 1 + read-write + + + DISABLED + SYSVDD_HVDF does not generate hardware interrupt (user polling) + 0 + + + ENABLED + SYSVDD_HVDF does generate hardware interrupt + 0x1 + + + + + LVSEL + System VDD Low-Voltage Level Select + 8 + 1 + read-write + + + DISABLED + Trip point set to Normal level (See the device data sheet for the normal level value) + 0 + + + ENABLED + Trip point set to Safe level (See the device data sheet for the safe level value) + 0x1 + + + + + LOCK + System Voltage Detect Reset Enable Lock Bit + 16 + 1 + read-write + + + DISABLED + Writes to VD_SYS_CFG[LVDRE, HVDRE, LVSEL] are allowed. + 0 + + + ENABLED + Writes to VD_SYS_CFG[LVDRE, HVDRE, LVSEL] are ignored. + 0x1 + + + + + + + VD_IO_CFG + IO Voltage Detect Configuration Register + 0x13C + 32 + read-write + 0x101 + 0xFFFFFFFF + + + LVDRE + IO VDD Low-Voltage Detect Reset Enable + 0 + 1 + read-write + + + DISABLED + IOVDD_LVDF does not generate hardware reset + 0 + + + ENABLED + IOVDD_LVDF does generate hardware reset + 0x1 + + + + + LVDIE + IO VDD Low-Voltage Detect Interrupt Enable + 1 + 1 + read-write + + + DISABLED + IOVDD_LVDF does not generate hardware interrupt (user polling) + 0 + + + ENABLED + IOVDD_LVDF does generate hardware interrupt + 0x1 + + + + + HVDRE + IO VDD High-Voltage Detect Reset Enable + 2 + 1 + read-write + + + DISABLED + IOVDD_HVDF does not generate hardware reset + 0 + + + ENABLED + IOVDD_HVDF does generate hardware reset + 0x1 + + + + + HVDIE + IO VDD High-Voltage Detect Interrupt Enable + 3 + 1 + read-write + + + DISABLED + IOVDD_HVDF does not generate hardware interrupt (user polling) + 0 + + + ENABLED + IOVDD_HVDF does generate hardware interrupt + 0x1 + + + + + LVSEL + IO VDD Low-Voltage Level Select + 8 + 1 + read-write + + + DISABLED + Trip point set to Normal (See the device data sheet for the normal level value) + 0 + + + ENABLED + Trip point set to Safe (See the device data sheet for the safe level value) + 0x1 + + + + + LOCK + IO Voltage Detect Reset Enable Lock Bit + 16 + 1 + read-write + + + DISABLED + Writes to VD_IO_CFG[LVDRE, HVDRE, HVSEL, LVSEL] are allowed. + 0 + + + ENABLED + Writes to VD_IO_CFG[LVDRE, HVDRE, HVSEL, LVSEL] are ignored. + 0x1 + + + + + + + EVD_CFG + External Voltage Domain Configuration Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + EVDISO + External Voltage Domain Isolation + 0 + 3 + read-write + + + EVDLPISO + External Voltage Domain Low Power Isolation + 8 + 3 + read-write + + + EVDSTAT + External Voltage Domain Status + 16 + 3 + read-only + + + + + VDD_CORE_GLITCH_DETECT_SC + VDD Core Glitch Detect Status Control Register + 0x144 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + CNT_SELECT + CNT_SELECT + 0 + 2 + read-write + + + CNT00 + Select bit-0 of 4-bit Ripple Counter to detect glitch on VDD Core + 0 + + + CNT01 + Select bit-1 of 4-bit Ripple Counter to detect glitch on VDD Core + 0x1 + + + CNT10 + Select bit-2 of 4-bit Ripple Counter to detect glitch on VDD Core + 0x2 + + + CNT11 + Select bit-3 of 4-bit Ripple Counter to detect glitch on VDD Core + 0x3 + + + + + TIMEOUT + TIMEOUT + 2 + 4 + read-write + + + RE + Core VDD Glitch Detect Reset Enable + 6 + 1 + read-write + + + DISABLED + GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset + 0 + + + ENABLED + GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset + 0x1 + + + + + IE + Core VDD Glitch Detect Interrupt Enable + 7 + 1 + read-write + + + DISABLED + GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) + 0 + + + ENABLED + GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt + 0x1 + + + + + GLITCH_DETECT_FLAG + GLITCH_DETECT_FLAG + 8 + 4 + read-write + oneToClear + + + LOCK + VDD Core Voltage Glitch Detect Reset Enable Lock Bit + 16 + 1 + read-write + + + DISABLED + Writes to RE are allowed. + 0 + + + ENABLED + Writes to RE are ignored. + 0x1 + + + + + + + CORELDO_CFG + LDO_CORE Configuration Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + DPDOWN_PULLDOWN_DISABLE + LDO_CORE Deep Power Down Pulldown Disable + 16 + 1 + read-write + + + DISABLED + LDO_CORE pulldown in Deep Power Down not disabled + 0 + + + ENABLED + LDO_CORE pulldown in Deep Power Down disabled + 0x1 + + + + + + + SYSLDO_CFG + LDO_SYS Configuration Register + 0x400 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISINKEN + Current Sink Enable + 0 + 1 + read-write + + + DISABLED + Disable current sink feature of System low power regulator. + 0 + + + ENABLED + Enable current sink feature of System low power regulator. + 0x1 + + + + + + + DCDC_CFG + DCDC Configuration Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREQ_CNTRL_ON + DCDC Burst Frequency Control Enable + 0 + 1 + read-write + + + FREQ_CNTRL + DCDC Burst Frequency Control Register + 8 + 6 + read-write + + + VOUT2P5_SEL + VOUT2P5_SEL + 18 + 1 + read-write + + + DISABLED + DCDC Vout set by DCDC_VDD_LVL register + 0 + + + ENABLED + DCDC Vout set to 2p5V. + 0x1 + + + + + + + DCDC_BURST_CFG + DCDC BURST Configuration Register + 0x504 + 32 + read-write + 0x1400000 + 0xFFFFFFFF + + + BURST_REQ + Software Burst Request Register + 0 + 1 + read-write + + + DISABLED + No burst request generated + 0 + + + ENABLED + Burst request generated + 0x1 + + + + + EXT_BURST_EN + DCDC External Burst Request Enable Register + 1 + 1 + read-write + + + DISABLED + External Burst Request are not enabled + 0 + + + ENABLED + External Burst Request are enabled + 0x1 + + + + + BURST_ACK + DCDC Burst Acknowledge Flag + 3 + 1 + read-write + oneToClear + + + DISABLED + DCDC Burst request has not acknowledged. + 0 + + + ENABLED + DCDC Burst request has completed and acknowledged. + 0x1 + + + + + PULSE_REFRESH_CNT + DCDC 16-bit refresh count value + 16 + 16 + read-write + + + + + + + SYSPM + SYSPM + SYSPM + 0x40017000 + + 0 + 0x330 + registers + + + + CFGSS0 + Configuration 0 + 0 + 32 + read-only + 0xFF0000FF + 0xFFFFFFFF + + + ID + Identifier + 0 + 8 + read-only + + + HRL + Hardware revision level + 8 + 8 + read-only + + + NCTRS + Number of Counters + 16 + 8 + read-only + + + MSC + Miscellaneous + 24 + 8 + read-only + + + + + CFGSS1 + Configuration 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ID + Identifier + 0 + 8 + read-only + + + HRL + Hardware revision level + 8 + 8 + read-only + + + NCTRS + Number of Counters + 16 + 8 + read-only + + + MSC + Miscellaneous + 24 + 8 + read-only + + + + + CFGSS2 + Configuration 2 + 0x8 + 32 + read-only + 0x1030002 + 0xFFFFFFFF + + + ID + Identifier + 0 + 8 + read-only + + + HRL + Hardware revision level + 8 + 8 + read-only + + + NCTRS + Number of Counters + 16 + 8 + read-only + + + MSC + Miscellaneous + 24 + 8 + read-only + + + + + CFGSS3 + Configuration 3 + 0xC + 32 + read-only + 0x2030002 + 0xFFFFFFFF + + + ID + Identifier + 0 + 8 + read-only + + + HRL + Hardware revision level + 8 + 8 + read-only + + + NCTRS + Number of Counters + 16 + 8 + read-only + + + MSC + Miscellaneous + 24 + 8 + read-only + + + + + 2 + 0x100 + PMCR[%s] + no description available + 0x200 + + PMCR + Performance Monitor Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MENB + Module is Enabled + 0 + 1 + read-only + + + DISABLE + Disable the performance monitor. + 0 + + + ENABLE + Enable the performance monitor. + 0x1 + + + + + SSC + Start/Stop Control + 1 + 3 + read-write + + + val0 + Idle + 0 + + + val1 + local stop + 0x1 + + + val2 + local start + 0x2 + + + val3 + local start + 0x3 + + + + + CMODE + Count Mode + 4 + 2 + read-write + + + val0 + count in both user and previleged modes + 0 + + + val2 + count only in user mode + 0x2 + + + val3 + count only in privileged mode + 0x3 + + + + + DCIFSH + Disable Counters if Stopped or Halted + 6 + 1 + read-write + + + DISABLE + Conitnue counting + 0 + + + ENABLE + Stops counting when the CPU is halted + 0x1 + + + + + RICTR + Resets the Instruction Counter + 7 + 1 + read-write + + + DISABLE + do not reset the instruction counter + 0 + + + ENABLE + clear the instruction counter + 0x1 + + + + + RECTR1 + Reset Event Counter 1 + 8 + 1 + read-write + + + RECTR2 + Reset Event Counter 2 + 9 + 1 + read-write + + + RECTR3 + Reset Event Counter 3 + 10 + 1 + read-write + + + DISABLE + Counter runs normally + 0 + + + ENABLE + Counter value resets at the end of the cycle + 0x1 + + + + + SELEVT1 + Select Event 1 + 11 + 7 + read-write + + + SELEVT2 + Select Event 2 + 18 + 7 + read-write + + + SELEVT3 + Select Event 3 + 25 + 7 + read-write + + + + + 3 + 0x8 + PMECTR[%s] + no description available + 0x18 + + PMECTR_HI_ + Performance Monitor Event Counter + 0 + 8 + read-only + 0 + 0xFF + + + ECTR + Event Counter + 0 + 8 + read-only + + + + + PMECTR_LO_ + Performance Monitor Event Counter + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECTR + Event Counter + 0 + 32 + read-only + + + + + + + + + TRGMUX0 + TRGMUX + TRGMUX + 0x40018000 + + 0 + 0x38 + registers + + + + TRGMUX_OUT0 + TRGMUX TRGMUX_OUT0 Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + SEL1 + Trigger MUX Source Select 1 + 8 + 7 + read-write + + + SEL2 + Trigger MUX Source Select 2 + 16 + 7 + read-write + + + SEL3 + Trigger MUX Source Select 3 + 24 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPIT0 + TRGMUX LPIT0 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + SEL1 + Trigger MUX Source Select 1 + 8 + 7 + read-write + + + SEL2 + Trigger MUX Source Select 2 + 16 + 7 + read-write + + + SEL3 + Trigger MUX Source Select 3 + 24 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + TPM0 + TRGMUX TPM0 Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + SEL1 + Trigger MUX Source Select 1 + 8 + 7 + read-write + + + SEL2 + Trigger MUX Source Select 2 + 16 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + TPM1 + TRGMUX TPM1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + SEL1 + Trigger MUX Source Select 1 + 8 + 7 + read-write + + + SEL2 + Trigger MUX Source Select 2 + 16 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPI2C0 + TRGMUX LPI2C0 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPI2C1 + TRGMUX LPI2C1 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPSPI0 + TRGMUX LPSPI0 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPSPI1 + TRGMUX LPSPI1 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPUART0 + TRGMUX LPUART0 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + LPUART1 + TRGMUX LPUART1 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + FlexIO0 + TRGMUX FlexIO0 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + SEL1 + Trigger MUX Source Select 1 + 8 + 7 + read-write + + + SEL2 + Trigger MUX Source Select 2 + 16 + 7 + read-write + + + SEL3 + Trigger MUX Source Select 3 + 24 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + ADC_GP0 + TRGMUX ADC_GP0 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + SEL1 + Trigger MUX Source Select 1 + 8 + 7 + read-write + + + SEL2 + Trigger MUX Source Select 2 + 16 + 7 + read-write + + + SEL3 + Trigger MUX Source Select 3 + 24 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + CMP_GP0 + TRGMUX CMP_GP0 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + CMP_GP1 + TRGMUX CMP_GP1 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEL0 + Trigger MUX Source Select 1 + 0 + 7 + read-write + + + LK + TRGMUX register lock. + 31 + 1 + read-write + + + UNLOCKED + Register can be written. + 0 + + + LOCKED + Register cannot be written until the next system Reset. + 0x1 + + + + + + + + + WUU0 + WUU + WUU + 0x40019000 + + 0 + 0x5C + registers + + + WUU0 + 22 + + + + VERID + Version ID + 0 + 32 + read-only + 0x1000001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + STANDARD + Standard features implemented + 0 + + + FILT_ALL_PWR + Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x20202002 + 0xFFFFFFFF + + + FILTERS + Filter Number + 0 + 8 + read-only + + + DMAS + DMA Number + 8 + 8 + read-only + + + MODULES + Module Number + 16 + 8 + read-only + + + PINS + Pin Number + 24 + 8 + read-only + + + + + PE1 + Pin Enable 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WUPE0 + Wakeup pin enable for WUU_Pn + 0 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE1 + Reserved + 2 + 2 + read-write + + + DISABLE + Not supported + 0 + + + EN_RISE_HI + Not supported + 0x1 + + + EN_FALL_LO + Not supported + 0x2 + + + EN_ANY + Not supported + 0x3 + + + + + WUPE2 + Wakeup pin enable for WUU_Pn + 4 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE3 + Wakeup pin enable for WUU_Pn + 6 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE4 + Wakeup pin enable for WUU_Pn + 8 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE5 + Wakeup pin enable for WUU_Pn + 10 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE6 + Reserved + 12 + 2 + read-write + + + DISABLE + Not supported + 0 + + + EN_RISE_HI + Not supported + 0x1 + + + EN_FALL_LO + Not supported + 0x2 + + + EN_ANY + Not supported + 0x3 + + + + + WUPE7 + Wakeup pin enable for WUU_Pn + 14 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE8 + Wakeup pin enable for WUU_Pn + 16 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE9 + Wakeup pin enable for WUU_Pn + 18 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE10 + Wakeup pin enable for WUU_Pn + 20 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE11 + Wakeup pin enable for WUU_Pn + 22 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE12 + Wakeup pin enable for WUU_Pn + 24 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE13 + Wakeup pin enable for WUU_Pn + 26 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE14 + Wakeup pin enable for WUU_Pn + 28 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE15 + Wakeup pin enable for WUU_Pn + 30 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + + + PE2 + Pin Enable 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WUPE27 + Wakeup pin enable for WUU_Pn + 22 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + WUPE28 + Wakeup pin enable for WUU_Pn + 24 + 2 + read-write + + + DISABLE + Disables as a wakeup pin + 0 + + + EN_RISE_HI + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + + + ME + Module Interrupt Enable + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + WUME0 + Module iterrupt wakeup enable for module n + 0 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME1 + Module iterrupt wakeup enable for module n + 1 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME2 + Module iterrupt wakeup enable for module n + 2 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME3 + Module iterrupt wakeup enable for module n + 3 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME4 + Module iterrupt wakeup enable for module n + 4 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME5 + Module iterrupt wakeup enable for module n + 5 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME6 + Module iterrupt wakeup enable for module n + 6 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUME7 + Module iterrupt wakeup enable for module n + 7 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + + + DE + Module DMA/Trigger Enable + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + WUDE0 + DMA/Trigger wakeup enable for module n + 0 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUDE1 + DMA/Trigger wakeup enable for module n + 1 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUDE2 + DMA/Trigger wakeup enable for module n + 2 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUDE4 + DMA/Trigger wakeup enable for module n + 4 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUDE5 + DMA/Trigger wakeup enable for module n + 5 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUDE8 + DMA/Trigger wakeup enable for module n + 8 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + WUDE9 + DMA/Trigger wakeup enable for module n + 9 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + + + PF + Pin Flag + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + WUF0 + Wakeup flag for WUU_Pn + 0 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF2 + Wakeup flag for WUU_Pn + 2 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF3 + Wakeup flag for WUU_Pn + 3 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF4 + Wakeup flag for WUU_Pn + 4 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF5 + Wakeup flag for WUU_Pn + 5 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF7 + Wakeup flag for WUU_Pn + 7 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF8 + Wakeup flag for WUU_Pn + 8 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF9 + Wakeup flag for WUU_Pn + 9 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF10 + Wakeup flag for WUU_Pn + 10 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF11 + Wakeup flag for WUU_Pn + 11 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF12 + Wakeup flag for WUU_Pn + 12 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF13 + Wakeup flag for WUU_Pn + 13 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF14 + Wakeup flag for WUU_Pn + 14 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF15 + Wakeup flag for WUU_Pn + 15 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF27 + Wakeup flag for WUU_Pn + 27 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + WUF28 + Wakeup flag for WUU_Pn + 28 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + + + FILT + Pin Filter + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILTSEL1 + Filter 1 Pin Select + 0 + 5 + read-write + + + FILTE1 + Filter 1 Enable + 5 + 2 + read-write + + + DISABLE + Disable filter + 0 + + + EN_RISE_HI + Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enable filter. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + FILTF1 + Filter 1 Flag + 7 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + FILTSEL2 + Filter 2 Pin Select + 8 + 5 + read-write + + + FILTE2 + Filter 2 Enable + 13 + 2 + read-write + + + DISABLE + Disable filter + 0 + + + EN_RISE_HI + Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a trigger request: Detect on high level + 0x1 + + + EN_FALL_LO + Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a trigger request: Detect on low level + 0x2 + + + EN_ANY + Enable filter. When configured as an interrupt/DMA request: Detect on any edge + 0x3 + + + + + FILTF2 + Filter 2 Flag + 15 + 1 + read-write + oneToClear + + + NO_FLAG + No + 0 + + + FLAG + Yes + 0x1 + + + + + + + PDC1 + Pin DMA/Trigger Configuration 1 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + WUPDC0 + Wakeup pin configuration for WUU_Pn + 0 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC1 + Reserved + 2 + 2 + read-write + + + INTERRUPT + Not supported + 0 + + + DMA_REQ + Not supported + 0x1 + + + TRIGGER + Not supported + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC2 + Wakeup pin configuration for WUU_Pn + 4 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC3 + Wakeup pin configuration for WUU_Pn + 6 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC4 + Wakeup pin configuration for WUU_Pn + 8 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC5 + Wakeup pin configuration for WUU_Pn + 10 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC6 + Reserved + 12 + 2 + read-write + + + INTERRUPT + Not supported + 0 + + + DMA_REQ + Not supported + 0x1 + + + TRIGGER + Not supported + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC7 + Wakeup pin configuration for WUU_Pn + 14 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC8 + Wakeup pin configuration for WUU_Pn + 16 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC9 + Wakeup pin configuration for WUU_Pn + 18 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC10 + Wakeup pin configuration for WUU_Pn + 20 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC11 + Wakeup pin configuration for WUU_Pn + 22 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC12 + Wakeup pin configuration for WUU_Pn + 24 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC13 + Wakeup pin configuration for WUU_Pn + 26 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC14 + Wakeup pin configuration for WUU_Pn + 28 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC15 + Wakeup pin configuration for WUU_Pn + 30 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + + + PDC2 + Pin DMA/Trigger Configuration 2 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + WUPDC27 + Wakeup pin configuration for WUU_Pn + 22 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + WUPDC28 + Wakeup pin configuration for WUU_Pn + 24 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + RES + Reserved + 0x3 + + + + + + + FDC + Pin Filter DMA/Trigger Configuration + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILTC1 + Filter configuration for FILTn + 0 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + + + FILTC2 + Filter configuration for FILTn + 2 + 2 + read-write + + + INTERRUPT + Interrupt + 0 + + + DMA_REQ + DMA request + 0x1 + + + TRIGGER + Trigger event + 0x2 + + + + + + + PMC + Pin Mode Configuration + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + WUPMC0 + Wakeup pin mode configuration for WUU_Pn + 0 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC2 + Wakeup pin mode configuration for WUU_Pn + 2 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC3 + Wakeup pin mode configuration for WUU_Pn + 3 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC4 + Wakeup pin mode configuration for WUU_Pn + 4 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC5 + Wakeup pin mode configuration for WUU_Pn + 5 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC7 + Wakeup pin mode configuration for WUU_Pn + 7 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC8 + Wakeup pin mode configuration for WUU_Pn + 8 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC9 + Wakeup pin mode configuration for WUU_Pn + 9 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC10 + Wakeup pin mode configuration for WUU_Pn + 10 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC11 + Wakeup pin mode configuration for WUU_Pn + 11 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC12 + Wakeup pin mode configuration for WUU_Pn + 12 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC13 + Wakeup pin mode configuration for WUU_Pn + 13 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC14 + Wakeup pin mode configuration for WUU_Pn + 14 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC15 + Wakeup pin mode configuration for WUU_Pn + 15 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC27 + Wakeup pin mode configuration for WUU_Pn + 27 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + WUPMC28 + Wakeup pin mode configuration for WUU_Pn + 28 + 1 + read-write + + + LOW_PWR_ONLY + Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0 + + + ANY_PWR + Active during all power modes. Software must not modify the corresponding fields within the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers. + 0x1 + + + + + + + FMC + Pin Filter Mode Configuration + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILTM1 + Filter Mode for FILTn + 0 + 1 + read-write + + + LOW_PWR_ONLY + Active only during Deep Sleep/Power Down mode + 0 + + + ANY_PWR + Active during all power modes + 0x1 + + + + + FILTM2 + Filter Mode for FILTn + 1 + 1 + read-write + + + LOW_PWR_ONLY + Active only during Deep Sleep/Power Down mode + 0 + + + ANY_PWR + Active during all power modes + 0x1 + + + + + + + + + WDOG0 + WDOG + WDOG + 0x4001A000 + + 0 + 0x10 + registers + + + WDOG0 + 23 + + + + CS + Control and Status Register + 0 + 32 + read-write + 0x3A80 + 0xFFFFFFFF + + + STOP + Stop Enable + 0 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + WAIT + Wait Enable + 1 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + DBG + Debug Enable + 2 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + TST + Watchdog Test + 3 + 2 + read-write + + + DIS + Watchdog test mode disabled. + 0 + + + EN + Watchdog user mode enabled (test mode disabled). After testing the watchdog, software should use this setting to indicate the watchdog is functioning normally in user mode. + 0x1 + + + EN_LOW + Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + 0x2 + + + EN_HIGH + Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + 0x3 + + + + + UPDATE + Allow updates + 5 + 1 + read-write + + + DIS + Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + 0 + + + EN + Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + 0x1 + + + + + INT + Watchdog Interrupt + 6 + 1 + read-write + + + DIS + Watchdog interrupts are disabled. Watchdog resets are not delayed. + 0 + + + EN + Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + 0x1 + + + + + EN + Watchdog Enable + 7 + 1 + read-write + + + DIS + Watchdog disabled. + 0 + + + EN + Watchdog enabled. + 0x1 + + + + + CLK + Watchdog Clock + 8 + 2 + read-write + + + RCS + Reconfiguration Success + 10 + 1 + read-only + + + RECONFIG + Reconfiguring WDOG. + 0 + + + SUCCESS + Reconfiguration is successful. + 0x1 + + + + + ULK + Unlock status + 11 + 1 + read-only + + + LOCK + Locked + 0 + + + UNLOCK + Unlocked + 0x1 + + + + + PRES + Watchdog prescaler + 12 + 1 + read-write + + + DIS + 256 prescaler disabled. + 0 + + + EN + 256 prescaler enabled. + 0x1 + + + + + CMD32EN + Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + 13 + 1 + read-write + + + DIS + Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + 0 + + + EN + Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + 0x1 + + + + + FLG + Watchdog Interrupt Flag + 14 + 1 + read-write + oneToClear + + + NO + No interrupt occurred. + 0 + + + YES + An interrupt occurred. + 0x1 + + + + + WIN + Watchdog Window + 15 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + + + CNT + Counter Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CNTLOW + Low byte of the Watchdog Counter + 0 + 8 + read-write + + + CNTHIGH + High byte of the Watchdog Counter + 8 + 8 + read-write + + + + + TOVAL + Timeout Value Register + 0x8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TOVALLOW + Low byte of the timeout value + 0 + 8 + read-write + + + TOVALHIGH + High byte of the timeout value + 8 + 8 + read-write + + + + + WIN + Window Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINLOW + Low byte of Watchdog Window + 0 + 8 + read-write + + + WINHIGH + High byte of Watchdog Window + 8 + 8 + read-write + + + + + + + WDOG1 + WDOG + WDOG + 0x4001B000 + + 0 + 0x10 + registers + + + WDOG1 + 24 + + + + CS + Control and Status Register + 0 + 32 + read-write + 0x3A00 + 0xFFFFFFFF + + + STOP + Stop Enable + 0 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + WAIT + Wait Enable + 1 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + DBG + Debug Enable + 2 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + TST + Watchdog Test + 3 + 2 + read-write + + + DIS + Watchdog test mode disabled. + 0 + + + EN + Watchdog user mode enabled (test mode disabled). After testing the watchdog, software should use this setting to indicate the watchdog is functioning normally in user mode. + 0x1 + + + EN_LOW + Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + 0x2 + + + EN_HIGH + Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + 0x3 + + + + + UPDATE + Allow updates + 5 + 1 + read-write + + + DIS + Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + 0 + + + EN + Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + 0x1 + + + + + INT + Watchdog Interrupt + 6 + 1 + read-write + + + DIS + Watchdog interrupts are disabled. Watchdog resets are not delayed. + 0 + + + EN + Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + 0x1 + + + + + EN + Watchdog Enable + 7 + 1 + read-write + + + DIS + Watchdog disabled. + 0 + + + EN + Watchdog enabled. + 0x1 + + + + + CLK + Watchdog Clock + 8 + 2 + read-write + + + RCS + Reconfiguration Success + 10 + 1 + read-only + + + RECONFIG + Reconfiguring WDOG. + 0 + + + SUCCESS + Reconfiguration is successful. + 0x1 + + + + + ULK + Unlock status + 11 + 1 + read-only + + + LOCK + Locked + 0 + + + UNLOCK + Unlocked + 0x1 + + + + + PRES + Watchdog prescaler + 12 + 1 + read-write + + + DIS + 256 prescaler disabled. + 0 + + + EN + 256 prescaler enabled. + 0x1 + + + + + CMD32EN + Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + 13 + 1 + read-write + + + DIS + Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + 0 + + + EN + Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + 0x1 + + + + + FLG + Watchdog Interrupt Flag + 14 + 1 + read-write + oneToClear + + + NO + No interrupt occurred. + 0 + + + YES + An interrupt occurred. + 0x1 + + + + + WIN + Watchdog Window + 15 + 1 + read-write + + + DIS + Disables + 0 + + + EN + Enables + 0x1 + + + + + + + CNT + Counter Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CNTLOW + Low byte of the Watchdog Counter + 0 + 8 + read-write + + + CNTHIGH + High byte of the Watchdog Counter + 8 + 8 + read-write + + + + + TOVAL + Timeout Value Register + 0x8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TOVALLOW + Low byte of the timeout value + 0 + 8 + read-write + + + TOVALHIGH + High byte of the timeout value + 8 + 8 + read-write + + + + + WIN + Window Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINLOW + Low byte of Watchdog Window + 0 + 8 + read-write + + + WINHIGH + High byte of Watchdog Window + 8 + 8 + read-write + + + + + + + MRCC + MRCC + MRCC + 0x4001C000 + + 0 + 0x42C + registers + + + + MRCC_EWM0 + EWM0 Reset and Clock Control + 0x4C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_SYSPM0 + SYSPM0 Reset and Clock Control + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_WDOG0 + WDOG0 Reset and Clock Control + 0x68 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_WDOG1 + WDOG1 Reset and Clock Control + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_SFA0 + SFA0 Reset and Clock Control + 0x74 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_CRC0 + CRC0 Reset and Clock Control + 0x8C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_SECSUBSYS + ELE Reset and Clock Control + 0x90 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPIT0 + LPIT0 Reset and Clock Control + 0xBC + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_TSTMR0 + TSTMR0 Reset and Clock Control + 0xC0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_TPM0 + TPM0 Reset and Clock Control + 0xC4 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + clkroot_func_5 + 32K-CLK + 0x5 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_TPM1 + TPM1 Reset and Clock Control + 0xC8 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + clkroot_func_5 + 32K-CLK + 0x5 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPI2C0 + LPI2C0 Reset and Clock Control + 0xCC + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPI2C1 + LPI2C1 Reset and Clock Control + 0xD0 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_I3C0 + I3C0 Reset and Clock Control + 0xD4 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPSPI0 + LPSPI0 Reset and Clock Control + 0xD8 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPSPI1 + LPSPI1 Reset and Clock Control + 0xDC + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPUART0 + LPUART0 Reset and Clock Control + 0xE0 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + clkroot_func_5 + 32K-CLK + 0x5 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPUART1 + LPUART1 Reset and Clock Control + 0xE4 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + clkroot_func_5 + 32K-CLK + 0x5 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_FLEXIO0 + FLEXIO0 Reset and Clock Control + 0xE8 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_SEMA0 + SEMA42 Reset and Clock Control + 0xFC + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_DATA_STREAM_2P4 + DSB Reset and Clock Control + 0x104 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_PORTA + PORTA Reset and Clock Control + 0x108 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_PORTB + PORTB Reset and Clock Control + 0x10C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_PORTC + PORTC Reset and Clock Control + 0x110 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPADC0 + ADC0 Reset and Clock Control + 0x11C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + MUX + Functional Clock Mux Select + 4 + 3 + read-write + + + clkroot_func_0 + The clock is off + 0 + + + clkroot_func_2 + FRO-6M + 0x2 + + + clkroot_func_3 + FRO-192M + 0x3 + + + clkroot_func_4 + SOSC-CLK + 0x4 + + + + + DIV + Functional Clock Divider + 8 + 4 + read-write + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPCMP0 + LPCMP0 Reset and Clock Control + 0x120 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_LPCMP1 + LPCMP1 Reset and Clock Control + 0x124 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_VREF0 + VREF0 Reset and Clock Control + 0x128 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_GPIOA + GPIOA Reset and Clock Control + 0x404 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_GPIOB + GPIOB Reset and Clock Control + 0x408 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_GPIOC + GPIOC Reset and Clock Control + 0x40C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_DMA0 + DMA0 Reset and Clock Control + 0x410 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + RSTB + Reset Negation + 30 + 1 + read-write + + + RESETING + Module is held in reset + 0 + + + NORMAL + Module released from reset + 0x1 + + + + + PR + Peripheral Present + 31 + 1 + read-only + + + DISABLED + Module is not present; writes to this register are ignored + 0 + + + ENABLED + Module is present + 0x1 + + + + + + + MRCC_PFLEXNVM + FMC-NPX Reset and Clock Control + 0x414 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_SRAM0 + CTCM Reset and Clock Control + 0x41C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_SRAM1 + STCM0 Reset and Clock Control + 0x420 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_SRAM2 + STCM1 Reset and Clock Control + 0x424 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + MRCC_SRAM3 + STCM2 Reset and Clock Control + 0x428 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CC + Clock Configuration + 0 + 2 + read-write + + + OFF + Peripheral clocks are disabled; module does not stall low power mode entry + 0 + + + ON + Peripheral clocks are enabled; module does not stall low power mode entry + 0x1 + + + HW + Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle + 0x2 + + + ON_UNTIL_SLEEP + Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle. + 0x3 + + + + + + + + + SFA0 + Signal Frequency Analyser + SFA + SFA + 0x4001D000 + + 0 + 0x38 + registers + + + SFA0 + 26 + + + + CTRL + Signal Frequency Analyser (SFA) Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MODE + MEASUREMENT MODE + 0 + 2 + read-write + + + mode0 + Frequency measurement performed with REF frequency > CUT Frequency. + 0 + + + mode1 + Frequency measurement performed with REF frequency < CUT Frequency. + 0x1 + + + mode2 + CUT period measurement performed. + 0x2 + + + + + SFA_IRQ_EN + SFA Interrupt Enable + 5 + 1 + read-write + + + SFA_IRQ_EN0 + Interrupts are disabled. + 0 + + + SFA_IRQ_EN1 + Interrupts are enabled. + 0x1 + + + + + SFA_EN + SFA Enable + 6 + 1 + read-write + + + SFA_EN0 + The SFA is disabled. + 0 + + + SFA_EN1 + The SFA is enabled. + 0x1 + + + + + CUT_PREDIV + CUT_PREDIV + 16 + 8 + read-write + + + CUT_PREDIV0 + No Divide + 0 + + + CUT_PREDIV1 + No Divide + 0x1 + + + CUT_PREDIV2 + Divide by 2 + 0x2 + + + CUT_PREDIV3 + Divide by 2 + 0x3 + + + CUT_PREDIV4 + Divide by 4 + 0x4 + + + CUT_PREDIV5 + Divide by 4 + 0x5 + + + CUT_PREDIV6 + Divide by 6 + 0x6 + + + CUT_PREDIV7 + Divide by 6 + 0x7 + + + CUT_PREDIV8 + Divide by 8 + 0x8 + + + CUT_PREDIV9 + Divide by 8 + 0x9 + + + CUT_PREDIVa_10 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA + + + CUT_PREDIVa_11 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB + + + CUT_PREDIVa_12 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC + + + CUT_PREDIVa_13 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD + + + CUT_PREDIVa_14 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE + + + CUT_PREDIVa_15 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF + + + CUT_PREDIVa_16 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x10 + + + CUT_PREDIVa_17 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x11 + + + CUT_PREDIVa_18 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x12 + + + CUT_PREDIVa_19 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x13 + + + CUT_PREDIVa_20 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x14 + + + CUT_PREDIVa_21 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x15 + + + CUT_PREDIVa_22 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x16 + + + CUT_PREDIVa_23 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x17 + + + CUT_PREDIVa_24 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x18 + + + CUT_PREDIVa_25 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x19 + + + CUT_PREDIVa_26 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x1A + + + CUT_PREDIVa_27 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x1B + + + CUT_PREDIVa_28 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x1C + + + CUT_PREDIVa_29 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x1D + + + CUT_PREDIVa_30 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x1E + + + CUT_PREDIVa_31 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x1F + + + CUT_PREDIVa_32 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x20 + + + CUT_PREDIVa_33 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x21 + + + CUT_PREDIVa_34 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x22 + + + CUT_PREDIVa_35 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x23 + + + CUT_PREDIVa_36 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x24 + + + CUT_PREDIVa_37 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x25 + + + CUT_PREDIVa_38 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x26 + + + CUT_PREDIVa_39 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x27 + + + CUT_PREDIVa_40 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x28 + + + CUT_PREDIVa_41 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x29 + + + CUT_PREDIVa_42 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x2A + + + CUT_PREDIVa_43 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x2B + + + CUT_PREDIVa_44 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x2C + + + CUT_PREDIVa_45 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x2D + + + CUT_PREDIVa_46 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x2E + + + CUT_PREDIVa_47 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x2F + + + CUT_PREDIVa_48 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x30 + + + CUT_PREDIVa_49 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x31 + + + CUT_PREDIVa_50 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x32 + + + CUT_PREDIVa_51 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x33 + + + CUT_PREDIVa_52 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x34 + + + CUT_PREDIVa_53 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x35 + + + CUT_PREDIVa_54 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x36 + + + CUT_PREDIVa_55 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x37 + + + CUT_PREDIVa_56 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x38 + + + CUT_PREDIVa_57 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x39 + + + CUT_PREDIVa_58 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x3A + + + CUT_PREDIVa_59 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x3B + + + CUT_PREDIVa_60 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x3C + + + CUT_PREDIVa_61 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x3D + + + CUT_PREDIVa_62 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x3E + + + CUT_PREDIVa_63 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x3F + + + CUT_PREDIVa_64 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x40 + + + CUT_PREDIVa_65 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x41 + + + CUT_PREDIVa_66 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x42 + + + CUT_PREDIVa_67 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x43 + + + CUT_PREDIVa_68 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x44 + + + CUT_PREDIVa_69 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x45 + + + CUT_PREDIVa_70 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x46 + + + CUT_PREDIVa_71 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x47 + + + CUT_PREDIVa_72 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x48 + + + CUT_PREDIVa_73 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x49 + + + CUT_PREDIVa_74 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x4A + + + CUT_PREDIVa_75 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x4B + + + CUT_PREDIVa_76 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x4C + + + CUT_PREDIVa_77 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x4D + + + CUT_PREDIVa_78 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x4E + + + CUT_PREDIVa_79 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x4F + + + CUT_PREDIVa_80 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x50 + + + CUT_PREDIVa_81 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x51 + + + CUT_PREDIVa_82 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x52 + + + CUT_PREDIVa_83 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x53 + + + CUT_PREDIVa_84 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x54 + + + CUT_PREDIVa_85 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x55 + + + CUT_PREDIVa_86 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x56 + + + CUT_PREDIVa_87 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x57 + + + CUT_PREDIVa_88 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x58 + + + CUT_PREDIVa_89 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x59 + + + CUT_PREDIVa_90 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x5A + + + CUT_PREDIVa_91 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x5B + + + CUT_PREDIVa_92 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x5C + + + CUT_PREDIVa_93 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x5D + + + CUT_PREDIVa_94 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x5E + + + CUT_PREDIVa_95 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x5F + + + CUT_PREDIVa_96 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x60 + + + CUT_PREDIVa_97 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x61 + + + CUT_PREDIVa_98 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x62 + + + CUT_PREDIVa_99 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x63 + + + CUT_PREDIVa_100 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x64 + + + CUT_PREDIVa_101 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x65 + + + CUT_PREDIVa_102 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x66 + + + CUT_PREDIVa_103 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x67 + + + CUT_PREDIVa_104 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x68 + + + CUT_PREDIVa_105 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x69 + + + CUT_PREDIVa_106 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x6A + + + CUT_PREDIVa_107 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x6B + + + CUT_PREDIVa_108 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x6C + + + CUT_PREDIVa_109 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x6D + + + CUT_PREDIVa_110 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x6E + + + CUT_PREDIVa_111 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x6F + + + CUT_PREDIVa_112 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x70 + + + CUT_PREDIVa_113 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x71 + + + CUT_PREDIVa_114 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x72 + + + CUT_PREDIVa_115 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x73 + + + CUT_PREDIVa_116 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x74 + + + CUT_PREDIVa_117 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x75 + + + CUT_PREDIVa_118 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x76 + + + CUT_PREDIVa_119 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x77 + + + CUT_PREDIVa_120 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x78 + + + CUT_PREDIVa_121 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x79 + + + CUT_PREDIVa_122 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x7A + + + CUT_PREDIVa_123 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x7B + + + CUT_PREDIVa_124 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x7C + + + CUT_PREDIVa_125 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x7D + + + CUT_PREDIVa_126 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x7E + + + CUT_PREDIVa_127 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x7F + + + CUT_PREDIVa_128 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x80 + + + CUT_PREDIVa_129 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x81 + + + CUT_PREDIVa_130 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x82 + + + CUT_PREDIVa_131 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x83 + + + CUT_PREDIVa_132 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x84 + + + CUT_PREDIVa_133 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x85 + + + CUT_PREDIVa_134 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x86 + + + CUT_PREDIVa_135 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x87 + + + CUT_PREDIVa_136 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x88 + + + CUT_PREDIVa_137 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x89 + + + CUT_PREDIVa_138 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x8A + + + CUT_PREDIVa_139 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x8B + + + CUT_PREDIVa_140 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x8C + + + CUT_PREDIVa_141 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x8D + + + CUT_PREDIVa_142 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x8E + + + CUT_PREDIVa_143 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x8F + + + CUT_PREDIVa_144 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x90 + + + CUT_PREDIVa_145 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x91 + + + CUT_PREDIVa_146 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x92 + + + CUT_PREDIVa_147 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x93 + + + CUT_PREDIVa_148 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x94 + + + CUT_PREDIVa_149 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x95 + + + CUT_PREDIVa_150 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x96 + + + CUT_PREDIVa_151 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x97 + + + CUT_PREDIVa_152 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x98 + + + CUT_PREDIVa_153 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x99 + + + CUT_PREDIVa_154 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x9A + + + CUT_PREDIVa_155 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x9B + + + CUT_PREDIVa_156 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x9C + + + CUT_PREDIVa_157 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x9D + + + CUT_PREDIVa_158 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x9E + + + CUT_PREDIVa_159 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0x9F + + + CUT_PREDIVa_160 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA0 + + + CUT_PREDIVa_161 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA1 + + + CUT_PREDIVa_162 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA2 + + + CUT_PREDIVa_163 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA3 + + + CUT_PREDIVa_164 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA4 + + + CUT_PREDIVa_165 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA5 + + + CUT_PREDIVa_166 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA6 + + + CUT_PREDIVa_167 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA7 + + + CUT_PREDIVa_168 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA8 + + + CUT_PREDIVa_169 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xA9 + + + CUT_PREDIVa_170 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xAA + + + CUT_PREDIVa_171 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xAB + + + CUT_PREDIVa_172 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xAC + + + CUT_PREDIVa_173 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xAD + + + CUT_PREDIVa_174 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xAE + + + CUT_PREDIVa_175 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xAF + + + CUT_PREDIVa_176 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB0 + + + CUT_PREDIVa_177 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB1 + + + CUT_PREDIVa_178 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB2 + + + CUT_PREDIVa_179 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB3 + + + CUT_PREDIVa_180 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB4 + + + CUT_PREDIVa_181 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB5 + + + CUT_PREDIVa_182 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB6 + + + CUT_PREDIVa_183 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB7 + + + CUT_PREDIVa_184 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB8 + + + CUT_PREDIVa_185 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xB9 + + + CUT_PREDIVa_186 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xBA + + + CUT_PREDIVa_187 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xBB + + + CUT_PREDIVa_188 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xBC + + + CUT_PREDIVa_189 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xBD + + + CUT_PREDIVa_190 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xBE + + + CUT_PREDIVa_191 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xBF + + + CUT_PREDIVa_192 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC0 + + + CUT_PREDIVa_193 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC1 + + + CUT_PREDIVa_194 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC2 + + + CUT_PREDIVa_195 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC3 + + + CUT_PREDIVa_196 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC4 + + + CUT_PREDIVa_197 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC5 + + + CUT_PREDIVa_198 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC6 + + + CUT_PREDIVa_199 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC7 + + + CUT_PREDIVa_200 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC8 + + + CUT_PREDIVa_201 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xC9 + + + CUT_PREDIVa_202 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xCA + + + CUT_PREDIVa_203 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xCB + + + CUT_PREDIVa_204 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xCC + + + CUT_PREDIVa_205 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xCD + + + CUT_PREDIVa_206 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xCE + + + CUT_PREDIVa_207 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xCF + + + CUT_PREDIVa_208 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD0 + + + CUT_PREDIVa_209 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD1 + + + CUT_PREDIVa_210 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD2 + + + CUT_PREDIVa_211 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD3 + + + CUT_PREDIVa_212 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD4 + + + CUT_PREDIVa_213 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD5 + + + CUT_PREDIVa_214 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD6 + + + CUT_PREDIVa_215 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD7 + + + CUT_PREDIVa_216 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD8 + + + CUT_PREDIVa_217 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xD9 + + + CUT_PREDIVa_218 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xDA + + + CUT_PREDIVa_219 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xDB + + + CUT_PREDIVa_220 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xDC + + + CUT_PREDIVa_221 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xDD + + + CUT_PREDIVa_222 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xDE + + + CUT_PREDIVa_223 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xDF + + + CUT_PREDIVa_224 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE0 + + + CUT_PREDIVa_225 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE1 + + + CUT_PREDIVa_226 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE2 + + + CUT_PREDIVa_227 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE3 + + + CUT_PREDIVa_228 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE4 + + + CUT_PREDIVa_229 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE5 + + + CUT_PREDIVa_230 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE6 + + + CUT_PREDIVa_231 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE7 + + + CUT_PREDIVa_232 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE8 + + + CUT_PREDIVa_233 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xE9 + + + CUT_PREDIVa_234 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xEA + + + CUT_PREDIVa_235 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xEB + + + CUT_PREDIVa_236 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xEC + + + CUT_PREDIVa_237 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xED + + + CUT_PREDIVa_238 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xEE + + + CUT_PREDIVa_239 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xEF + + + CUT_PREDIVa_240 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF0 + + + CUT_PREDIVa_241 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF1 + + + CUT_PREDIVa_242 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF2 + + + CUT_PREDIVa_243 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF3 + + + CUT_PREDIVa_244 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF4 + + + CUT_PREDIVa_245 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF5 + + + CUT_PREDIVa_246 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF6 + + + CUT_PREDIVa_247 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF7 + + + CUT_PREDIVa_248 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF8 + + + CUT_PREDIVa_249 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xF9 + + + CUT_PREDIVa_250 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xFA + + + CUT_PREDIVa_251 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xFB + + + CUT_PREDIVa_252 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xFC + + + CUT_PREDIVa_253 + Divide by CUT_PREDIV - CUT_PREDIV%2 + 0xFD + + + CUT_PREDIVe + Divide by 254 + 0xFE + + + CUT_PREDIVf + Divide by 254 + 0xFF + + + + + CUT_SEL + CUT_SEL + 24 + 4 + read-write + + + CUT_PIN_EN + CUT_PIN_EN + 31 + 1 + read-write + + + + + CTRL_EXT + Signal Frequency Analyser (SFA) Control Extended + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CUT_CLK_EN + CUT_CLK_EN + 0 + 16 + read-write + + + + + CNT_STAT + Signal Frequency Analyser Count Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + REF_STOPPED + REF_STOPPED + 0 + 1 + read-only + + + CUT_STOPPED + CUT_STOPPED + 1 + 1 + read-only + + + MEAS_STARTED + Measurement Started Flag + 2 + 1 + read-only + + + REF_CNT_TIMEOUT + Reference Counter Time Out + 3 + 1 + read-only + + + SFA_IRQ + SFA Interrupt Request + 4 + 1 + read-write + oneToClear + + + FREQ_GT_MAX_IRQ + FREQ_GT_MAX interrupt flag + 5 + 1 + read-write + oneToClear + + + FREQ_LT_MIN_IRQ + FREQ_LT_MIN interrupt flag + 6 + 1 + read-write + oneToClear + + + + + CUT_CNT + Signal Frequency Analyser Clock Under Test Counter + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CUT_CNT + CUT_CNT + 0 + 32 + read-write + + + + + REF_CNT + Signal Frequency Analyser Reference Clock Counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + REF_CNT + REF_CNT + 0 + 32 + read-write + + + + + CUT_TARGET + Signal Frequency Analyser Clock Under Test Target Count + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CUT_TARGET + CUT_TARGET + 0 + 32 + read-write + + + + + REF_TARGET + Signal Frequency Analyser Reference Clock Target Count + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + REF_TARGET + REF_TARGET + 0 + 32 + read-write + + + + + REF_CNT_ST_SAVED + Signal Frequency Analyser Reference Clock Count Start Saved Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + REF_CNT_ST_SAVED + REF_CNT_ST_SAVED + 0 + 32 + read-only + + + + + REF_CNT_END_SAVED + Signal Frequency Analyser Reference Clock Count End Saved Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + REF_CNT_END_SAVED + REF_CNT_END_SAVED + 0 + 32 + read-only + + + + + CTRL2 + Extended control register for SFA + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + REF_CLK_SEL + Reference clock select + 0 + 2 + read-write + + + FREQ_GT_MAX_IRQ_EN + FREQ_GT_MAX interrupt enable + 16 + 1 + read-write + + + FREQ_LT_MIN_IRQ_EN + FREQ_LT_MIN interrupt enable + 17 + 1 + read-write + + + + + REF_LOW_LIMIT_CNT + Record the low limit reference clock count + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + REF_LOW_LIMIT_CNT + Low limit reference clock count value + 0 + 32 + read-write + + + + + REF_HIGH_LIMIT_CNT + This register record the low limit of ref clk counter + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + REF_HIGH_LIMIT_CNT + High limit reference clock count value + 0 + 32 + read-write + + + + + CUT_LOW_LIMIT_CNT + Record the CUT clock low limit counter + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + cut_low_limit_cnt + Low limit cut clock count value + 0 + 32 + read-write + + + + + CUT_HIGH_LIMIT_CNT + Record high limit count of cut clock + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + cut_high_limit_cnt + High limit cut clock count value + 0 + 32 + read-write + + + + + + + RF_SFA + Signal Frequency Analyser + SFA + 0x48A06300 + + 0 + 0x38 + registers + + + + SCG0 + SCG + SCG + 0x4001E000 + + 0 + 0x404 + registers + + + SCG0 + 25 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + VERSION + SCG Version Number + 0 + 32 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x9800001E + 0xFFFFFFFF + + + CLKPRES + Clock Present + 0 + 8 + read-only + + + SOSC + System OSC (SOSC) is present. + #xxxxxx1x + + + + + DIVPRES + Divider Present + 27 + 5 + read-only + + + DIVSLOW + System DIVSLOW is present. + #xxxx1 + + + + + + + CSR + Clock Status Register + 0x10 + 32 + read-only + 0x3020001 + 0xFFFFFFFF + + + DIVSLOW + Slow Clock Divide Ratio + 0 + 4 + read-only + + + DIV_1 + Divide-by-1 + 0 + + + DIV_2 + Divide-by-2 + 0x1 + + + DIV_3 + Divide-by-3 + 0x2 + + + DIV_4 + Divide-by-4 + 0x3 + + + DIV_5 + Divide-by-5 + 0x4 + + + DIV_6 + Divide-by-6 + 0x5 + + + DIV_7 + Divide-by-7 + 0x6 + + + DIV_8 + Divide-by-8 + 0x7 + + + DIV_9 + Divide-by-9 + 0x8 + + + DIV_10 + Divide-by-10 + 0x9 + + + DIV_11 + Divide-by-11 + 0xA + + + DIV_12 + Divide-by-12 + 0xB + + + DIV_13 + Divide-by-13 + 0xC + + + DIV_14 + Divide-by-14 + 0xD + + + DIV_15 + Divide-by-15 + 0xE + + + DIV_16 + Divide-by-16 + 0xF + + + + + DIVBUS + Bus Clock Divide Ratio + 4 + 4 + read-only + + + DIV_1 + Divide-by-1 + 0 + + + DIV_2 + Divide-by-2 + 0x1 + + + DIV_3 + Divide-by-3 + 0x2 + + + DIV_4 + Divide-by-4 + 0x3 + + + DIV_5 + Divide-by-5 + 0x4 + + + DIV_6 + Divide-by-6 + 0x5 + + + DIV_7 + Divide-by-7 + 0x6 + + + DIV_8 + Divide-by-8 + 0x7 + + + DIV_9 + Divide-by-9 + 0x8 + + + DIV_10 + Divide-by-10 + 0x9 + + + DIV_11 + Divide-by-11 + 0xA + + + DIV_12 + Divide-by-12 + 0xB + + + DIV_13 + Divide-by-13 + 0xC + + + DIV_14 + Divide-by-14 + 0xD + + + DIV_15 + Divide-by-15 + 0xE + + + DIV_16 + Divide-by-16 + 0xF + + + + + DIVCORE + Core Clock Divide Ratio + 16 + 4 + read-only + + + DIV_1 + Divide-by-1 + 0 + + + DIV_2 + Divide-by-2 + 0x1 + + + DIV_3 + Divide-by-3 + 0x2 + + + DIV_4 + Divide-by-4 + 0x3 + + + DIV_5 + Divide-by-5 + 0x4 + + + DIV_6 + Divide-by-6 + 0x5 + + + DIV_7 + Divide-by-7 + 0x6 + + + DIV_8 + Divide-by-8 + 0x7 + + + DIV_9 + Divide-by-9 + 0x8 + + + DIV_10 + Divide-by-10 + 0x9 + + + DIV_11 + Divide-by-11 + 0xA + + + DIV_12 + Divide-by-12 + 0xB + + + DIV_13 + Divide-by-13 + 0xC + + + DIV_14 + Divide-by-14 + 0xD + + + DIV_15 + Divide-by-15 + 0xE + + + DIV_16 + Divide-by-16 + 0xF + + + + + SCS + System Clock Source + 24 + 4 + read-only + + + SOSC + System OSC (SOSC_CLK) + 0x1 + + + SIRC + Slow IRC (SIRC_CLK) + 0x2 + + + FIRC + Fast IRC (FIRC_CLK) + 0x3 + + + ROSC + RTC OSC (ROSC_CLK) + 0x4 + + + + + + + RCCR + Run Clock Control Register + 0x14 + 32 + read-write + 0x3020001 + 0xFFFFFFFF + + + DIVSLOW + Slow Clock Divide Ratio + 0 + 4 + read-write + + + DIV_1 + Divide-by-1 + 0 + + + DIV_2 + Divide-by-2 + 0x1 + + + DIV_3 + Divide-by-3 + 0x2 + + + DIV_4 + Divide-by-4 + 0x3 + + + DIV_5 + Divide-by-5 + 0x4 + + + DIV_6 + Divide-by-6 + 0x5 + + + DIV_7 + Divide-by-7 + 0x6 + + + DIV_8 + Divide-by-8 + 0x7 + + + DIV_9 + Divide-by-9 + 0x8 + + + DIV_10 + Divide-by-10 + 0x9 + + + DIV_11 + Divide-by-11 + 0xA + + + DIV_12 + Divide-by-12 + 0xB + + + DIV_13 + Divide-by-13 + 0xC + + + DIV_14 + Divide-by-14 + 0xD + + + DIV_15 + Divide-by-15 + 0xE + + + DIV_16 + Divide-by-16 + 0xF + + + + + DIVBUS + Bus Clock Divide Ratio + 4 + 4 + read-write + + + DIV_1 + Divide-by-1 + 0 + + + DIV_2 + Divide-by-2 + 0x1 + + + DIV_3 + Divide-by-3 + 0x2 + + + DIV_4 + Divide-by-4 + 0x3 + + + DIV_5 + Divide-by-5 + 0x4 + + + DIV_6 + Divide-by-6 + 0x5 + + + DIV_7 + Divide-by-7 + 0x6 + + + DIV_8 + Divide-by-8 + 0x7 + + + DIV_9 + Divide-by-9 + 0x8 + + + DIV_10 + Divide-by-10 + 0x9 + + + DIV_11 + Divide-by-11 + 0xA + + + DIV_12 + Divide-by-12 + 0xB + + + DIV_13 + Divide-by-13 + 0xC + + + DIV_14 + Divide-by-14 + 0xD + + + DIV_15 + Divide-by-15 + 0xE + + + DIV_16 + Divide-by-16 + 0xF + + + + + DIVCORE + Core Clock Divide Ratio + 16 + 4 + read-write + + + DIV_1 + Divide-by-1 + 0 + + + DIV_2 + Divide-by-2 + 0x1 + + + DIV_3 + Divide-by-3 + 0x2 + + + DIV_4 + Divide-by-4 + 0x3 + + + DIV_5 + Divide-by-5 + 0x4 + + + DIV_6 + Divide-by-6 + 0x5 + + + DIV_7 + Divide-by-7 + 0x6 + + + DIV_8 + Divide-by-8 + 0x7 + + + DIV_9 + Divide-by-9 + 0x8 + + + DIV_10 + Divide-by-10 + 0x9 + + + DIV_11 + Divide-by-11 + 0xA + + + DIV_12 + Divide-by-12 + 0xB + + + DIV_13 + Divide-by-13 + 0xC + + + DIV_14 + Divide-by-14 + 0xD + + + DIV_15 + Divide-by-15 + 0xE + + + DIV_16 + Divide-by-16 + 0xF + + + + + SCS + System Clock Source + 24 + 3 + read-write + + + SOSC + System OSC (SOSC_CLK) + 0x1 + + + SIRC + Slow IRC (SIRC_CLK) + 0x2 + + + FIRC + Fast IRC (FIRC_CLK) + 0x3 + + + ROSC + RTC OSC (ROSC_CLK) + 0x4 + + + + + + + CLKOUTCNFG + SCG CLKOUT Configuration Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKOUTSEL + SCG Clkout Select + 24 + 4 + read-write + + + DIVEXT + SCG SLOW Clock + 0 + + + SOSC + System OSC (SOSC_CLK) + 0x1 + + + SIRC + Slow IRC (SIRC_CLK) + 0x2 + + + FIRC + Fast IRC (FIRC_CLK) + 0x3 + + + ROSC + RTC OSC (ROSC_CLK) + 0x4 + + + + + + + SOSCCSR + System OSC Control Status Register + 0x100 + 32 + read-write + 0 + 0xFBFFFFFF + + + SOSCEN + System OSC Enable + 0 + 1 + read-write + + + DISABLED + System OSC is disabled + 0 + + + ENABLED + System OSC is enabled + 0x1 + + + + + SOSCSTEN + System OSC Stop Enable + 1 + 1 + read-write + + + DISABLED + System OSC is disabled in any of the sleep modes + 0 + + + ENABLED + System OSC is enabled in SLEEP mode only if SOSCEN=1. SOSCSTEN must be cleared when its power domain is going to enter Deep Sleep or Power Down mode. + 0x1 + + + + + SOSCCM + System OSC Clock Monitor Enable + 16 + 1 + read-write + + + DISABLED + System OSC Clock Monitor is disabled + 0 + + + ENABLED + System OSC Clock Monitor is enabled + 0x1 + + + + + SOSCCMRE + System OSC Clock Monitor Reset Enable + 17 + 1 + read-write + + + GENERATE_INTERRUPT + Clock Monitor generates interrupt when error detected + 0 + + + GENERATE_RESET + Clock Monitor generates reset when error detected + 0x1 + + + + + LK + Lock Register + 23 + 1 + read-write + + + WRITE_ENABLED + This Control Status Register can be written. + 0 + + + WRITE_DISABLED + This Control Status Register cannot be written. + 0x1 + + + + + SOSCVLD + System OSC Valid + 24 + 1 + read-only + + + DISABLED + System OSC is not enabled or clock is not valid + 0 + + + ENABLED + System OSC is enabled and output clock is valid + 0x1 + + + + + SOSCSEL + System OSC Selected + 25 + 1 + read-only + + + NOT_SOSC + System OSC is not the system clock source + 0 + + + SOSC + System OSC is the system clock source + 0x1 + + + + + SOSCERR + System OSC Clock Error + 26 + 1 + read-write + oneToClear + + + DISABLED_OR_NO_ERROR + System OSC Clock Monitor is disabled or has not detected an error + 0 + + + ENABLED_AND_ERROR + System OSC Clock Monitor is enabled and detected an error + 0x1 + + + + + + + SIRCCSR + Slow IRC Control Status Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIRCSTEN + Slow IRC Stop Enable + 1 + 1 + read-write + + + DISABLED + Slow IRC is disabled in sleep modes + 0 + + + ENABLED + Slow IRC is enabled in SLEEP mode + 0x1 + + + + + LK + Lock Register + 23 + 1 + read-write + + + WRITE_ENABLED + Control Status Register can be written. + 0 + + + WRITE_DISABLED + Control Status Register cannot be written. + 0x1 + + + + + SIRCVLD + Slow IRC Valid + 24 + 1 + read-only + + + DISABLED_OR_NOT_VALID + Slow IRC is not enabled or clock is not valid + 0 + + + ENABLED_AND_VALID + Slow IRC is enabled and output clock is valid + 0x1 + + + + + SIRCSEL + Slow IRC Selected + 25 + 1 + read-only + + + NOT_SIRC + Slow IRC is not the system clock source + 0 + + + SIRC + Slow IRC is the system clock source + 0x1 + + + + + + + FIRCCSR + Fast IRC Control Status Register + 0x300 + 32 + read-write + 0x3000001 + 0xFFFFFFFF + + + FIRCEN + Fast IRC Enable + 0 + 1 + read-write + + + DISABLED + Fast IRC is disabled + 0 + + + ENABLED + Fast IRC is enabled + 0x1 + + + + + FIRCSTEN + Fast IRC Stop Enable + 1 + 1 + read-write + + + DISABLED_IN_STOP_MODES + Fast IRC is disabled in sleep modes. + 0 + + + ENABLED_IN_STOP_MODES + Fast IRC is enabled in SLEEP modes + 0x1 + + + + + FIRCTREN + Fast IRC Trim Enable + 8 + 1 + read-write + + + DISABLED + Disable trimming Fast IRC to an external clock source + 0 + + + ENABLED + Enable trimming Fast IRC to an external clock source + 0x1 + + + + + FIRCTRUP + Fast IRC Trim Update + 9 + 1 + read-write + + + DISABLED + Disable Fast IRC trimming updates + 0 + + + ENABLED + Enable Fast IRC trimming updates + 0x1 + + + + + TRIM_LOCK + Fast IRC TRIM LOCK + 10 + 1 + read-write + + + FIRC_NOT_LOCKED + FIRC auto trim not locked to target frequency range. + 0 + + + FIRC_LOCKED + FIRC auto trim locked to target frequency range + 0x1 + + + + + COARSE_TRIM_BYPASS + Fast Coarse Auto Trim Bypass + 11 + 1 + read-write + + + NOT_BYPASSED + FIRC Coarse Auto Trim NOT Bypassed + 0 + + + BYPASSED + FIRC Coarse Auto Trim Bypassed + 0x1 + + + + + LK + Lock Register + 23 + 1 + read-write + + + WRITE_ENABLED + Control Status Register can be written. + 0 + + + WRITE_DISABLED + Control Status Register cannot be written. + 0x1 + + + + + FIRCVLD + Fast IRC Valid status + 24 + 1 + read-only + + + NOT_ENABLED_OR_NOT_VALID + Fast IRC is not enabled or clock is not valid. + 0 + + + ENABLED_AND_VALID + Fast IRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + 0x1 + + + + + FIRCSEL + Fast IRC Selected status + 25 + 1 + read-only + + + NOT_FIRC + Fast IRC is not the system clock source + 0 + + + FIRC + Fast IRC is the system clock source + 0x1 + + + + + FIRCERR + Fast IRC Clock Error + 26 + 1 + read-write + oneToClear + + + ERROR_NOT_DETECTED + Error not detected with the Fast IRC trimming. + 0 + + + ERROR_DETECTED + Error detected with the Fast IRC trimming. + 0x1 + + + + + + + FIRCCFG + Fast IRC Configuration Register + 0x308 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + RANGE + Frequency Range + 0 + 2 + read-write + + + FIRC_48MHZ + 48 MHz FIRC clock selected. + 0 + + + FIRC_64MHZ + 64 MHz FIRC clock selected. + 0x1 + + + FIRC_96MHZ + 96 MHz FIRC clock selected. + 0x2 + + + FIRC_192MHZ + 192 MHz FIRC clock selected. + 0x3 + + + + + + + FIRCTCFG + Fast IRC Trim Configuration Register + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIMSRC + Trim Source + 0 + 2 + read-write + + + SOSC + System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. + 0x2 + + + RTC_OSC + RTC OSC (32.768 kHz) + 0x3 + + + + + TRIMDIV + Fast IRC Trim Predivide + 16 + 11 + read-write + + + + + FIRCSTAT + Fast IRC Status Register + 0x318 + 32 + read-write + 0 + 0xFFFFC000 + + + TRIMFINE + Trim Fine + 0 + 8 + read-write + + + TRIMCOAR + Trim Coarse + 8 + 6 + read-write + + + + + ROSCCSR + RTC OSC Control Status Register + 0x400 + 32 + read-write + 0 + 0xFBFFFFFF + + + ROSCCM + RTC OSC Clock Monitor + 16 + 1 + read-write + + + DISABLED + RTC OSC Clock Monitor is disabled + 0 + + + ENABLED + RTC OSC Clock Monitor is enabled + 0x1 + + + + + ROSCCMRE + RTC OSC Clock Monitor Reset Enable + 17 + 1 + read-write + + + GENERATE_INTERRUPT + Clock Monitor generates interrupt when error detected + 0 + + + GENERATE_RESET + Clock Monitor generates reset when error detected + 0x1 + + + + + LK + Lock Register + 23 + 1 + read-write + + + WRITE_ENABLED + Control Status Register can be written. + 0 + + + WRITE_DISABLED + Control Status Register cannot be written. + 0x1 + + + + + ROSCVLD + RTC OSC Valid + 24 + 1 + read-only + + + DISABLED_OR_NOT_VALID + RTC OSC is not enabled or clock is not valid + 0 + + + ENABLED_AND_VALID + RTC OSC is enabled and output clock is valid + 0x1 + + + + + ROSCSEL + RTC OSC Selected + 25 + 1 + read-only + + + NOT_ROSC + RTC OSC is not the system clock source + 0 + + + ROSC + RTC OSC is the system clock source + 0x1 + + + + + ROSCERR + RTC OSC Clock Error + 26 + 1 + read-write + oneToClear + + + DISABLED_OR_NO_ERROR + RTC OSC Clock Monitor is disabled or has not detected an error + 0 + + + ENABLED_AND_ERROR + RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error + 0x1 + + + + + + + + + CCM32K + CCM32K + CCM32K + 0x4001F000 + + 0 + 0x20 + registers + + + + FRO32K_CTRL + Free Running 32 kHz Oscillator Control Register + 0 + 32 + read-write + 0x880001 + 0xFFFFFFFF + + + FRO_EN + FRO Enable + 0 + 1 + read-write + + + FRO_EN0 + FRO is disabled + 0 + + + FRO_EN1 + FRO is enabled + 0x1 + + + + + LOCK_EN + Write Access Lock + 31 + 1 + read-write + + + LOCK_EN0 + Register write access is unlocked + 0 + + + LOCK_EN1 + Register write access is locked + 0x1 + + + + + + + FRO32K_TRIM + Free Running 32 kHz Oscillator Trim Register + 0x4 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + FREQ_TRIM + Frequency Trim + 0 + 11 + read-write + + + FREQ_TRIM1024 + Default trim value + 0x400 + + + + + IFR_DIS + IFR Loading Disable Control + 29 + 1 + read-write + + + IFR_DIS0 + IFR loading is enabled + 0 + + + IFR_DIS1 + IFR loading is disabled + 0x1 + + + + + LOCK_EN + Write Access Lock + 31 + 1 + read-write + + + LOCK_EN0 + Register write access is unlocked + 0 + + + LOCK_EN1 + Register write access is locked + 0x1 + + + + + + + OSC32K_CTRL + 32 kHz OSC Control Register + 0x8 + 32 + read-write + 0 + 0x87F8FF9F + + + OSC_EN + Crystal Oscillator Enable + 0 + 1 + read-write + + + OSC_EN0 + Oscillator is disabled + 0 + + + OSC_EN1 + Oscillator is enabled + 0x1 + + + + + OSC_BYP_EN + Crystal Oscillator Bypass Enable + 1 + 1 + read-write + + + OSC_BYP_EN0 + Crystal oscillator is not bypassed + 0 + + + OSC_BYP_EN1 + Crystal oscillator is bypassed + 0x1 + + + + + CAP_SEL_EN + Crystal Load Capacitance Selection Enable + 7 + 1 + read-write + + + CAP_SEL_EN0 + Internal capacitance bank is not enabled + 0 + + + CAP_SEL_EN1 + Internal capacitance bank is enabled + 0x1 + + + + + EXTAL_CAP_SEL + Crystal load capacitance selection bits + 8 + 4 + read-write + + + EXTAL_CAP_SEL0 + 0 pF + 0 + + + EXTAL_CAP_SEL1 + 2 pF + 0x1 + + + EXTAL_CAP_SEL2 + 4 pF + 0x2 + + + EXTAL_CAP_SEL3 + 6 pF + 0x3 + + + EXTAL_CAP_SEL4 + 8 pF + 0x4 + + + EXTAL_CAP_SEL5 + 10 pF + 0x5 + + + EXTAL_CAP_SEL6 + 12 pF + 0x6 + + + EXTAL_CAP_SEL7 + 14 pF + 0x7 + + + EXTAL_CAP_SEL8 + 16 pF + 0x8 + + + EXTAL_CAP_SEL9 + 18 pF + 0x9 + + + EXTAL_CAP_SEL10 + 20 pF + 0xA + + + EXTAL_CAP_SEL11 + 22 pF + 0xB + + + EXTAL_CAP_SEL12 + 24 pF + 0xC + + + EXTAL_CAP_SEL13 + 26 pF + 0xD + + + EXTAL_CAP_SEL14 + 28 pF + 0xE + + + EXTAL_CAP_SEL15 + 30 pF + 0xF + + + + + XTAL_CAP_SEL + Crystal load capacitance selection bits + 12 + 4 + read-write + + + XTAL_CAP_SEL0 + 0 pF + 0 + + + XTAL_CAP_SEL1 + 2 pF + 0x1 + + + XTAL_CAP_SEL2 + 4 pF + 0x2 + + + XTAL_CAP_SEL3 + 6 pF + 0x3 + + + XTAL_CAP_SEL4 + 8 pF + 0x4 + + + XTAL_CAP_SEL5 + 10 pF + 0x5 + + + XTAL_CAP_SEL6 + 12 pF + 0x6 + + + XTAL_CAP_SEL7 + 14 pF + 0x7 + + + XTAL_CAP_SEL8 + 16 pF + 0x8 + + + XTAL_CAP_SEL9 + 18 pF + 0x9 + + + XTAL_CAP_SEL10 + 20 pF + 0xA + + + XTAL_CAP_SEL11 + 22 pF + 0xB + + + XTAL_CAP_SEL12 + 24 pF + 0xC + + + XTAL_CAP_SEL13 + 26 pF + 0xD + + + XTAL_CAP_SEL14 + 28 pF + 0xE + + + XTAL_CAP_SEL15 + 30 pF + 0xF + + + + + COARSE_AMP_GAIN + Amplifier gain adjustment bits to allow the use of a wide range of external crystal ESR values. + 20 + 2 + read-write + + + COARSE_AMP_GAIN0 + ESR_Range0 + 0 + + + COARSE_AMP_GAIN1 + ESR_Range1 + 0x1 + + + COARSE_AMP_GAIN2 + ESR_Range2 + 0x2 + + + COARSE_AMP_GAIN3 + ESR_Range3 + 0x3 + + + + + SOX_EN + SOX Mode Enable + 24 + 1 + read-write + + + SOX_EN1 + SOX mode is disabled. + 0 + + + SOX_EN0 + SOX mode is enabled. + 0x1 + + + + + LOCK_EN + Write Access Lock bit + 31 + 1 + read-write + + + LOCK_EN0 + Register write access is unlocked + 0 + + + LOCK_EN1 + Register write access is locked + 0x1 + + + + + + + STATUS + Status Register + 0xC + 32 + read-only + 0x10 + 0xFFFFFFFF + + + OSC32K_RDY + 32 kHz Oscillator ready bit. + 0 + 1 + read-only + + + OSC32K_RDY0 + Clock output from crystal oscillator is not stable. + 0 + + + OSC32K_RDY1 + Clock output from crystal oscillator is stable. + 0x1 + + + + + OSC32K_ACTIVE + 32 kHz Oscillator active bit + 2 + 1 + read-only + + + OSC32K_ACTIVE0 + OSC32K is not the active clock source + 0 + + + OSC32K_ACTIVE1 + OSC32K is the active clock source + 0x1 + + + + + FRO32K_ACTIVE + 32 kHz FRO active bit + 4 + 1 + read-only + + + FRO32K_ACTIVE0 + FRO32K is not the active clock source + 0 + + + FRO32K_ACTIVE1 + FRO32K is the active clock source + 0x1 + + + + + CLOCK_DET + Clock Detect + 6 + 1 + read-only + + + CLOCK_DET0 + Clock error is not detected + 0 + + + CLOCK_DET1 + Clock error is detected + 0x1 + + + + + + + CLKMON_CTRL + Clock Monitor Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_EN + CLKMON Enable + 0 + 1 + read-write + + + MON_EN0 + CLKMON is disabled + 0 + + + MON_EN1 + CLKMON is enabled + 0x1 + + + + + FREQ_TRIM + Frequency trim bits + 1 + 2 + read-write + + + FREQ_TRIM00 + Clock monitor asserts 2 cycle after expected edge (assert after 10 cycles with no edge) + 0 + + + FREQ_TRIM01 + Clock monitor asserts 4 cycles after expected edge (assert after 12 cycles with no edge) + 0x1 + + + FREQ_TRIM10 + Clock monitor asserts 6 cycles after expected edge (assert after 14 cycles with no edge) + 0x2 + + + FREQ_TRIM11 + Clock monitor asserts 8 cycles after expected edge (assert after 16 cycles with no edge) + 0x3 + + + + + DIVIDE_TRIM + Divide Trim + 3 + 2 + read-write + + + DIVIDE_TRIM00 + Clock monitor operates at 1 kHz for both FRO32K and OSC32K + 0 + + + DIVIDE_TRIM01 + Clock monitor operates at 64 Hz for FRO32K and clock monitor operates at 1 kHz for OSC32K (Reserved) + 0x1 + + + DIVIDE_TRIM10 + Clock monitor operates at 1 kHz for FRO32K and clock monitor operates at 64 Hz for OSC32K (Reserved) + 0x2 + + + DIVIDE_TRIM11 + Clock monitor operates at 64 Hz for both FRO32K and OSC32K + 0x3 + + + + + LOCK_EN + Write Access Lock bit + 31 + 1 + read-write + + + LOCK_EN0 + Register write access is unlocked + 0 + + + LOCK_EN1 + Register write access is locked + 0x1 + + + + + + + CGC32K + 32 kHz Clock Gate Control Register + 0x1C + 32 + read-write + 0x1F + 0xFFFFFFFF + + + CLK_OE_32K + 32 kHz clock output enable bits + 0 + 5 + read-write + + + CLK_OE_32K0 + Clock output is disabled + 0 + + + CLK_OE_32K1 + Clock output is enabled + 0x1 + + + + + CLK_SEL_32K + 32 kHz clock source selection bit + 5 + 1 + read-write + + + CLK_SEL_32K0 + FRO32K clock output is selected as clock source + 0 + + + CLK_SEL_32K1 + OSC32K clock output is selected as clock source + 0x1 + + + + + LOCK_EN + Write Access Lock bit + 31 + 1 + read-write + + + LOCK_EN0 + Register write access is unlocked + 0 + + + LOCK_EN1 + Register write access is locked + 0x1 + + + + + + + + + FMU0 + Flash + FMU + 0x40020000 + + 0 + 0x30 + registers + + + FMU0 + 27 + + + + FSTAT + Flash Status Register + 0 + 32 + read-write + 0x80 + 0xFFFFFFFE + + + FAIL + Command Fail Flag + 0 + 1 + read-only + + + fail0 + Error not detected + 0 + + + fail1 + Error detected + 0x1 + + + + + CMDABT + Command Abort Flag + 2 + 1 + read-write + oneToClear + + + cmdabt0 + No command abort detected + 0 + + + cmdabt1 + Command abort detected + 0x1 + + + + + PVIOL + Command Protection Violation Flag + 4 + 1 + read-write + oneToClear + + + pviol0 + No protection violation detected + 0 + + + pviol1 + Protection violation detected + 0x1 + + + + + ACCERR + Command Access Error Flag + 5 + 1 + read-write + oneToClear + + + accerr0 + No access error detected + 0 + + + accerr1 + Access error detected + 0x1 + + + + + CWSABT + Command Write Sequence Abort Flag + 6 + 1 + read-write + oneToClear + + + cwsabt0 + Command write sequence not aborted + 0 + + + cwsabt1 + Command write sequence aborted + 0x1 + + + + + CCIF + Command Complete Interrupt Flag + 7 + 1 + read-write + oneToClear + + + ccif0 + Flash command, initialization, or power mode recovery in progress + 0 + + + ccif1 + Flash command, initialization, or power mode recovery has completed + 0x1 + + + + + CMDPRT + Command protection level + 8 + 2 + read-only + + + cmdprt00 + Secure, normal access + 0 + + + cmdprt01 + Secure, privileged access + 0x1 + + + cmdprt10 + Nonsecure, normal access + 0x2 + + + cmdprt11 + Nonsecure, privileged access + 0x3 + + + + + CMDP + Command protection status flag + 11 + 1 + read-only + + + cmdp0 + Command protection level and domain ID are stale + 0 + + + cmdp1 + Command protection level (CMDPRT) and domain ID (CMDDID) are set + 0x1 + + + + + CMDDID + Command domain ID + 12 + 4 + read-only + + + DFDIF + Double Bit Fault Detect Interrupt Flag + 16 + 1 + read-write + oneToClear + + + dfdif0 + Double bit fault not detected during a valid flash read access + 0 + + + dfdif1 + Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + 0x1 + + + + + SALV_USED + Salvage Used for Erase operation + 17 + 1 + read-only + + + salv_used0 + Salvage not used during last operation + 0 + + + salv_used1 + Salvage used during the last erase operation + 0x1 + + + + + PEWEN + Program-Erase Write Enable Control + 24 + 2 + read-only + + + pewen00 + Writes are not enabled + 0 + + + pewen01 + Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + 0x1 + + + pewen10 + Writes are enabled for one flash or IFR page (page programming) + 0x2 + + + + + PERDY + Program-Erase Ready Control/Status Flag + 31 + 1 + read-write + oneToClear + + + perdy0 + Program or sector erase command operation not stalled + 0 + + + perdy1 + Program or sector erase command operation ready to execute + 0x1 + + + + + + + FCNFG + Flash Configuration Register + 0x4 + 32 + read-write + 0 + 0xFFFFFF + + + CCIE + Command Complete Interrupt Enable + 7 + 1 + read-write + + + ccie0 + Command complete interrupt disabled + 0 + + + ccie1 + Command complete interrupt enabled + 0x1 + + + + + ERSREQ + Mass Erase Request + 8 + 1 + read-only + + + ersreq0 + No request or request complete + 0 + + + ersreq1 + Request to run the Mass Erase operation + 0x1 + + + + + DFDIE + Double Bit Fault Detect Interrupt Enable + 16 + 1 + read-write + + + dfdie0 + Double bit fault detect interrupt disabled + 0 + + + dfdie1 + Double bit fault detect interrupt enabled + 0x1 + + + + + ERSIEN0 + Erase IFR Sector Enable - Block 0 + 24 + 4 + read-only + + + ersien00 + Block 0 IFR Sector X is protected from erase by ERSSCR command + 0 + + + ersien01 + Block 0 IFR Sector X is not protected from erase by ERSSCR command + 0x1 + + + + + ERSIEN1 + Erase IFR Sector Enable - Block 1 (for dual block configs) + 28 + 4 + read-only + + + ersien10 + Block 1 IFR Sector X is protected from erase by ERSSCR command + 0 + + + ersien11 + Block 1 IFR Sector X is not protected from erase by ERSSCR command + 0x1 + + + + + + + FCTRL + Flash Control Register + 0x8 + 32 + read-write + 0x100 + 0xFFFFFFF0 + + + RWSC + Read Wait-State Control + 0 + 4 + read-write + + + LSACTIVE + Low speed active mode + 8 + 1 + read-write + + + lsactive0 + Full speed active mode requested + 0 + + + lsactive1 + Low speed active mode requested + 0x1 + + + + + FDFD + Force Double Bit Fault Detect + 16 + 1 + read-write + + + fdfd0 + FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + 0 + + + fdfd1 + FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. + 0x1 + + + + + ABTREQ + Abort Request + 24 + 1 + read-write + + + abtreq0 + No request to abort a command write sequence + 0 + + + abtreq1 + Request to abort a command write sequence + 0x1 + + + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + FCCOB%s + Flash Common Command Object Registers + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCOBn + CCOBn + 0 + 32 + read-write + + + + + + + REGFILE0 + REGFILE + REGFILE + 0x40021000 + + 0 + 0x20 + registers + + + + 8 + 0x4 + REG[%s] + Register File Register index + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG + Register File + 0 + 32 + read-write + + + + + + + REGFILE1 + REGFILE + REGFILE + 0x40022000 + + 0 + 0x108 + registers + + + + 8 + 0x4 + REG[%s] + Register File Register index + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG + Register File + 0 + 32 + read-write + + + + + WAR + Write Access Register + 0x100 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + WAR0 + REG0 Register Write Access + 0 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR0 field. + 0x1 + + + + + WAR1 + REG1 Register Write Access + 1 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR1 field. + 0x1 + + + + + WAR2 + REG2 Register Write Access + 2 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR2 field. + 0x1 + + + + + WAR3 + REG3 Register Write Access + 3 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR3 field. + 0x1 + + + + + WAR4 + REG4 Register Write Access + 4 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR4 field. + 0x1 + + + + + WAR5 + REG5 Register Write Access + 5 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR5 field. + 0x1 + + + + + WAR6 + REG6 Register Write Access + 6 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR6 field. + 0x1 + + + + + WAR7 + REG7 Register Write Access + 7 + 1 + read-write + + + b0 + Not allow to write to the REGn register and WARn field until next reset. + 0 + + + b1 + Allow to write to the REGn register and WAR7 field. + 0x1 + + + + + + + RAR + Read Access Register + 0x104 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + RAR0 + REG0 Register Read Access + 0 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR1 + REG1 Register Read Access + 1 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR2 + REG2 Register Read Access + 2 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR3 + REG3 Register Read Access + 3 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR4 + REG4 Register Read Access + 4 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR5 + REG5 Register Read Access + 5 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR6 + REG6 Register Read Access + 6 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + RAR7 + REG7 Register Read Access + 7 + 1 + read-write + + + b0 + Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0. + 0 + + + b1 + Allow to read the REGn register. + 0x1 + + + + + + + + + CRC0 + CRC + CRC + 0x40023000 + + 0 + 0xC + registers + + + + DATA + CRC Data + 0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + LL + CRC Low Lower Byte + 0 + 8 + read-write + + + LU + CRC Low Upper Byte + 8 + 8 + read-write + + + HL + CRC High Lower Byte + 16 + 8 + read-write + + + HU + CRC High Upper Byte + 24 + 8 + read-write + + + + + GPOLY + CRC Polynomial + 0x4 + 32 + read-write + 0x1021 + 0xFFFFFFFF + + + LOW + Low Polynominal Half-Word + 0 + 16 + read-write + + + HIGH + High Polynominal Half-Word + 16 + 16 + read-write + + + + + CTRL + CRC Control + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCRC + TCRC + 24 + 1 + read-write + + + TCRC_0 + 16-bit + 0 + + + TCRC_1 + 32-bit + 0x1 + + + + + WAS + Write as Seed + 25 + 1 + read-write + + + WAS_0 + Data values + 0 + + + WAS_1 + Seed values + 0x1 + + + + + FXOR + Complement Read of CRC Data Register + 26 + 1 + read-write + + + FXOR_0 + No XOR on reading + 0 + + + FXOR_1 + Inverts or complements the read value of the CRC Data + 0x1 + + + + + TOTR + Transpose Type for Read + 28 + 2 + read-write + + + TOTR_0 + No transposition + 0 + + + TOTR_1 + Bits in bytes are transposed; bytes are not transposed + 0x1 + + + TOTR_2 + Both bits in bytes and bytes are transposed + 0x2 + + + TOTR_3 + Only bytes are transposed; no bits in a byte are transposed + 0x3 + + + + + TOT + Transpose Type for Writes + 30 + 2 + read-write + + + TOT_0 + No transposition + 0 + + + TOT_1 + Bits in bytes are transposed; bytes are not transposed + 0x1 + + + TOT_2 + Both bits in bytes and bytes are transposed + 0x2 + + + TOT_3 + Only bytes are transposed; no bits in a byte are transposed + 0x3 + + + + + + + + + ELEMUA + ELE_MUA + ELE_MU + 0x40024000 + + 0 + 0xFFF + registers + + + ELE_CMD + 28 + + + ELE_SECURE + 29 + + + ELE_NONSECURE + 30 + + + + VER + Version ID Register + 0 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + FEATURE + Feature Set Number + 0 + 16 + read-only + + + standard + Standard features are implemented. + 0 + + + + + MINOR + Minor Version Number (0x00 ) + 16 + 8 + read-only + + + MAJOR + Major Version Number (0x01 ) + 24 + 8 + read-only + + + + + PAR + Parameter Register + 0x4 + 32 + read-only + 0x210 + 0xFFFFFFFF + + + TR_NUM + Number of Transmit (TRn) registers (8'd16) + 0 + 8 + read-only + + + RR_NUM + Number of Receive (RRn) registers (8'd2) + 8 + 8 + read-only + + + + + UNUSED0 + Unused Register 0 + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + SR + Status Register + 0xC + 32 + read-only + 0x20 + 0xFFFFFFFF + + + TEP + Transmit Empty Pending + 5 + 1 + read-only + + + RFP + Receive Full Pending Flag + 6 + 1 + read-only + + + clear + No data is ready to be read. All RSR[RFn] bits are clear. + 0 + + + set + Data is ready to be read. One or more RSR[RFn] bits are set. + 0x1 + + + + + + + TCR + Transmit Control Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIEn + Transmit Register n Empty Interrupt Enable + 0 + 16 + read-write + + + + + TSR + Transmit Status Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + TEn + Transmit Register n Empty + 0 + 16 + read-only + + + + + RSR + Receive Status Register + 0x12C + 32 + read-only + 0 + 0xFFFFFFFF + + + RFn + Receive Register n Full + 0 + 2 + read-only + + + + + UNUSED1 + Unused Register 1 + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA16 + Unused 16-bit Register + 0 + 16 + read-write + + + + + 16 + 0x4 + TR[%s] + Transmit Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TR_DATA + Transmit Data + 0 + 32 + read-write + + + + + 2 + 0x4 + RR[%s] + Receive Register + 0x280 + 32 + read-only + 0 + 0xFFFFFFFF + + + RR_DATA + Receive Data + 0 + 32 + read-only + + + + + SEMA4_SR + Semaphore Status Register + 0x400 + 32 + read-only + 0 + 0xFFFFFFFF + + + OWNR16 + Semaphore Owner + 0 + 16 + read-only + + + SSS_CIP2 + Security SubSystem (ELE) command group 2 in progress + 16 + 1 + read-only + + + srv_req2_no + Service request group 2 not being processed by ELE + 0 + + + srv_req2_yes + Service request group 2 being processed by ELE + 0x1 + + + + + SSS_CIP1 + Security SubSystem (ELE) command group 1 in progress + 17 + 1 + read-only + + + srv_req1_no + Service request group 1 not being processed by ELE + 0 + + + srv_req1_yes + Service request group 1 being processed by ELE + 0x1 + + + + + SSS_LCK + Security SubSystem (ELE) lockup + 24 + 1 + read-only + + + sss_no_lockup + Edgelock enclave is not locked up + 0 + + + sss_lockup + Edgelock enclave is locked up in an unrecoverable state + 0x1 + + + + + MISC_BSY + Miscellaneous ELE Busy Indicators + 25 + 6 + read-only + + + SSS_BSY + Security SubSystem (ELE) Busy + 31 + 1 + read-only + + + not_busy + Edgelock enclave is not busy + 0 + + + busy + Edgelock enclave CPU is busy + 0x1 + + + + + + + SEMA4_OWNR + Semaphore Ownership Register + 0x474 + 32 + read-only + 0 + 0xFFFFFFFF + + + OWNR32 + Semaphore Owner + 0 + 32 + read-only + + + + + SEMA4_ACQ + Semaphore Acquire Register + 0x998 + 32 + read-only + 0 + 0xFFFFFFFF + + + OWNR32 + Semaphore Owner + 0 + 32 + read-only + + + + + SEMA4_REL + Semaphore Release Register + 0xACC + 32 + read-only + 0 + 0xFFFFFFFF + + + OWNR32 + Semaphore Owner + 0 + 32 + read-only + + + + + SEMA4_FREL + Semaphore Forced Release Register + 0xBA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + OWNR32 + Semaphore Owner + 0 + 32 + read-only + + + + + + + TRDC + TRDC + TRDC + 0x40026000 + + 0 + 0x42C4 + registers + + + TRDC0 + 31 + + + + TRDC_CR + TRDC Register + 0 + 32 + read-write + 0x10 + 0xFFF0FFFF + + + GVLDM + Global Valid for Domain Assignment Controllers + 0 + 1 + read-write + oneToSet + + + DISABLED + TRDC DACs are disabled. + 0 + + + ENABLED + TRDC DACs are enabled. + 0x1 + + + + + HRL + Hardware Revision Level + 1 + 4 + read-only + + + GVLDB + Global Valid for Memory Block Checkers + 14 + 1 + read-write + oneToSet + + + DISABLED + TRDC MBCs are disabled. + 0 + + + ENABLED + TRDC MBCs are enabled. + 0x1 + + + + + GVLDR + Global Valid for Memory Region Checkers + 15 + 1 + read-write + oneToSet + + + DISABLED + TRDC MRCs are disabled. + 0 + + + ENABLED + TRDC MRCs are enabled. + 0x1 + + + + + LK1 + Lock Status + 30 + 1 + read-write + + + INVALID + The CR can be written by any secure privileged write. + 0 + + + VALID + The CR is locked (read-only) until the next reset. + 0x1 + + + + + + + TRDC_HWCFG0 + Hardware Configuration Register 0 + 0xF0 + 32 + read-only + 0x21030403 + 0xFFFFFFFF + + + NDID + Number of domains + 0 + 4 + read-only + + + NMSTR + Number of bus masters + 8 + 8 + read-only + + + NMBC + Number of MBCs + 16 + 3 + read-only + + + NMRC + Number of MRCs + 24 + 4 + read-only + + + MID + Module ID + 28 + 4 + read-only + + + + + TRDC_HWCFG1 + TRDC Hardware Configuration Register 1 + 0xF4 + 32 + read-only + 0 + 0xFFFFFFF8 + + + DID + Domain identifier number + 0 + 3 + read-only + + + + + DACFG0 + Domain Assignment Configuration Register + 0x100 + 8 + read-only + 0x1 + 0xFF + + + NMDAR + Number of master domain assignment registers for bus master m + 0 + 4 + read-only + + + NCM + Non-CPU Master + 7 + 1 + read-only + + + CPU + Bus master is a processor. + 0 + + + NON_CPU + Bus master is a non-processor. + 0x1 + + + + + + + DACFG1 + Domain Assignment Configuration Register + 0x101 + 8 + read-only + 0x81 + 0xFF + + + NMDAR + Number of master domain assignment registers for bus master m + 0 + 4 + read-only + + + NCM + Non-CPU Master + 7 + 1 + read-only + + + CPU + Bus master is a processor. + 0 + + + NON_CPU + Bus master is a non-processor. + 0x1 + + + + + + + DACFG2 + Domain Assignment Configuration Register + 0x102 + 8 + read-only + 0x81 + 0xFF + + + NMDAR + Number of master domain assignment registers for bus master m + 0 + 4 + read-only + + + NCM + Non-CPU Master + 7 + 1 + read-only + + + CPU + Bus master is a processor. + 0 + + + NON_CPU + Bus master is a non-processor. + 0x1 + + + + + + + DACFG3 + Domain Assignment Configuration Register + 0x103 + 8 + read-only + 0x81 + 0xFF + + + NMDAR + Number of master domain assignment registers for bus master m + 0 + 4 + read-only + + + NCM + Non-CPU Master + 7 + 1 + read-only + + + CPU + Bus master is a processor. + 0 + + + NON_CPU + Bus master is a non-processor. + 0x1 + + + + + + + MBC0_CFG0 + Memory Block Configuration Register + 0x140 + 32 + read-only + 0x30043020 + 0xFFFFFFFF + + + SLV0_NMBLK + Number of blocks in slave 0. + 0 + 10 + read-only + + + SLV0_BLKSZL2 + Block size log2 in slave 0. + 10 + 5 + read-only + + + SLV1_NMBLK + Number of blocks in slave 1. + 16 + 10 + read-only + + + SLV1_BLKSZL2 + Block size log2 in slave 1. + 26 + 5 + read-only + + + + + MBC0_CFG1 + Memory Block Configuration Register + 0x144 + 32 + read-only + 0x300C3001 + 0xFFFFFFFF + + + SLV2_NMBLK + Number of blocks in slave 2. + 0 + 10 + read-only + + + SLV2_BLKSZL2 + Block size log2 in slave 2. + 10 + 5 + read-only + + + SLV3_NMBLK + Number of blocks in slave 3. + 16 + 10 + read-only + + + SLV3_BLKSZL2 + Block size log2 in slave 3. + 26 + 5 + read-only + + + + + MBC1_CFG0 + Memory Block Configuration Register + 0x148 + 32 + read-only + 0x30083002 + 0xFFFFFFFF + + + SLV0_NMBLK + Number of blocks in slave 0. + 0 + 10 + read-only + + + SLV0_BLKSZL2 + Block size log2 in slave 0. + 10 + 5 + read-only + + + SLV1_NMBLK + Number of blocks in slave 1. + 16 + 10 + read-only + + + SLV1_BLKSZL2 + Block size log2 in slave 1. + 26 + 5 + read-only + + + + + MBC1_CFG1 + Memory Block Configuration Register + 0x14C + 32 + read-only + 0x30023005 + 0xFFFFFFFF + + + SLV2_NMBLK + Number of blocks in slave 2. + 0 + 10 + read-only + + + SLV2_BLKSZL2 + Block size log2 in slave 2. + 10 + 5 + read-only + + + SLV3_NMBLK + Number of blocks in slave 3. + 16 + 10 + read-only + + + SLV3_BLKSZL2 + Block size log2 in slave 3. + 26 + 5 + read-only + + + + + MBC2_CFG0 + Memory Block Configuration Register + 0x150 + 32 + read-only + 0x3004304F + 0xFFFFFFFF + + + SLV0_NMBLK + Number of blocks in slave 0. + 0 + 10 + read-only + + + SLV0_BLKSZL2 + Block size log2 in slave 0. + 10 + 5 + read-only + + + SLV1_NMBLK + Number of blocks in slave 1. + 16 + 10 + read-only + + + SLV1_BLKSZL2 + Block size log2 in slave 1. + 26 + 5 + read-only + + + + + MBC2_CFG1 + Memory Block Configuration Register + 0x154 + 32 + read-only + 0x30003010 + 0xFFFFFFFF + + + SLV2_NMBLK + Number of blocks in slave 2. + 0 + 10 + read-only + + + SLV2_BLKSZL2 + Block size log2 in slave 2. + 10 + 5 + read-only + + + SLV3_NMBLK + Number of blocks in slave 3. + 16 + 10 + read-only + + + SLV3_BLKSZL2 + Block size log2 in slave 3. + 26 + 5 + read-only + + + + + MBC3_CFG0 + Memory Block Configuration Register + 0x158 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV0_NMBLK + Number of blocks in slave 0. + 0 + 10 + read-only + + + SLV0_BLKSZL2 + Block size log2 in slave 0. + 10 + 5 + read-only + + + SLV1_NMBLK + Number of blocks in slave 1. + 16 + 10 + read-only + + + SLV1_BLKSZL2 + Block size log2 in slave 1. + 26 + 5 + read-only + + + + + MBC3_CFG1 + Memory Block Configuration Register + 0x15C + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV2_NMBLK + Number of blocks in slave 2. + 0 + 10 + read-only + + + SLV2_BLKSZL2 + Block size log2 in slave 2. + 10 + 5 + read-only + + + SLV3_NMBLK + Number of blocks in slave 3. + 16 + 10 + read-only + + + SLV3_BLKSZL2 + Block size log2 in slave 3. + 26 + 5 + read-only + + + + + MRCFG0 + Memory Region Configuration Register + 0x160 + 8 + read-only + 0x8 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG1 + Memory Region Configuration Register + 0x161 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG2 + Memory Region Configuration Register + 0x162 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG3 + Memory Region Configuration Register + 0x163 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG4 + Memory Region Configuration Register + 0x164 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG5 + Memory Region Configuration Register + 0x165 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG6 + Memory Region Configuration Register + 0x166 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + MRCFG7 + Memory Region Configuration Register + 0x167 + 8 + read-only + 0 + 0xFF + + + NMRGD + Number of memory region descriptors for memory region checker n + 0 + 5 + read-only + + + + + TRDC_IDAU_CR + TRDC IDAU Control Register + 0x1C0 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + CFGSECEXT + Configure Security Extension + 3 + 1 + read-only + + + DISABLED + ARMv8M Security Extension is disabled + 0 + + + ENABLED + ARMv8-M Security Extension is enabled + 0x1 + + + + + MPUSDIS + Secure Memory Protection Unit Disabled + 4 + 1 + read-only + + + DISABLED + Secure MPU is enabled + 0 + + + ENABLED + Secure MPU is disabled + 0x1 + + + + + MPUNSDIS + NonSecure Memory Protection Unit Disabled + 5 + 1 + read-only + + + DISABLED + Nonsecure MPU is enabled + 0 + + + ENABLED + Nonsecure MPU is disabled + 0x1 + + + + + SAUDIS + Security Attribution Unit Disable + 6 + 1 + read-only + + + DISABLED + SAU is enabled + 0 + + + ENABLED + SAU is disabled + 0x1 + + + + + LKSVTAIRCR + Lock Secure VTOR, Application interrupt and Reset Control Registers + 8 + 1 + read-write + oneToSet + + + UNLOCK + Unlock these registers + 0 + + + LOCK + Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + 0x1 + + + + + LKNSVTOR + Lock Nonsecure Vector Table Offset Register + 9 + 1 + read-write + oneToSet + + + UNLOCK + Unlock this register + 0 + + + LOCK + Disable writes to the VTOR_NS register + 0x1 + + + + + LKSMPU + Lock Secure MPU + 10 + 1 + read-write + oneToSet + + + UNLOCK + Unlock these registers + 0 + + + LOCK + Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state + 0x1 + + + + + LKNSMPU + Lock Nonsecure MPU + 11 + 1 + read-write + oneToSet + + + UNLOCK + Unlock these registers + 0 + + + LOCK + Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + 0x1 + + + + + LKSAU + Lock SAU + 12 + 1 + read-write + oneToSet + + + UNLOCK + Unlock these registers + 0 + + + LOCK + Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + 0x1 + + + + + PCURRNS + Processor current security + 31 + 1 + read-only + + + SECURE + Processor is in Secure state + 0 + + + NONSECURE + Processor is in Nonsecure state + 0x1 + + + + + + + TRDC_FLW_CTL + TRDC FLW Control + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LK + Lock bit + 30 + 1 + read-write + + + UNLOCKED + FLW registers may be modified. + 0 + + + LOCKED + FLW registers are locked until the next reset. + 0x1 + + + + + V + Valid bit + 31 + 1 + read-write + + + INVALID + FLW function is disabled. + 0 + + + VALID + FLW function is enabled. + 0x1 + + + + + + + TRDC_FLW_PBASE + TRDC FLW Physical Base + 0x1E4 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + PBASE + Physical base address + 0 + 32 + read-only + + + + + TRDC_FLW_ABASE + TRDC FLW Array Base + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ABASE_L + Array base address low + 15 + 7 + read-write + + + ABASE_H + Array base address high + 22 + 10 + read-only + + + + + TRDC_FLW_BCNT + TRDC FLW Block Count + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + BCNT + Block Count + 0 + 15 + read-write + + + + + TRDC_FDID + TRDC Fault Domain ID + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FDID + Domain ID of Faulted Access + 0 + 4 + read-write + + + + + 3 + 0x4 + TRDC_DERRLOC[%s] + TRDC Domain Error Location Register + 0x200 + 32 + read-only + 0 + 0xFFFFFFFF + + + mbc0_err_slv + MBC0 ERROR SLAVE + 0 + 4 + read-only + + + mbc1_err_slv + MBC1 ERROR SLAVE + 4 + 4 + read-only + + + mbc2_err_slv + MBC2 ERROR SLAVE + 8 + 4 + read-only + + + mbc3_err_slv + MBC3 ERROR SLAVE + 12 + 4 + read-only + + + MRCINST + MRC instance + 16 + 8 + read-only + + + + + MBC0_DERR_W0 + MBC Domain Error Word0 Register + 0x400 + 32 + read-only + 0 + 0xFFFFFFFF + + + EADDR + Error address + 0 + 32 + read-only + + + + + MBC0_DERR_W1 + MBC Domain Error Word1 Register + 0x404 + 32 + read-only + 0 + 0xFFFFFFFF + + + EDID + Error domain identifier + 0 + 4 + read-only + + + EATR + Error attributes + 8 + 3 + read-only + + + SUI + Secure user mode, instruction fetch access. + 0 + + + SUD + Secure user mode, data access. + 0x1 + + + SPI + Secure privileged mode, instruction fetch access. + 0x2 + + + SPD + Secure privileged mode, data access. + 0x3 + + + NSUI + Nonsecure user mode, instruction fetch access. + 0x4 + + + NSUD + Nonsecure user mode, data access. + 0x5 + + + NSPI + Nonsecure privileged mode, instruction fetch access. + 0x6 + + + NSPD + Nonsecure privileged mode, data access. + 0x7 + + + + + ERW + Error read/write + 11 + 1 + read-only + + + read + Read access + 0 + + + write + Write access + 0x1 + + + + + EPORT + Error port + 24 + 3 + read-only + + + S0 + mbcxslv0 + 0 + + + S1 + mbcxslv1 + 0x1 + + + S2 + mbcxslv2 + 0x2 + + + S3 + mbcxslv3 + 0x3 + + + + + EST + Error state + 30 + 2 + read-only + + + NOVIO0 + No access violation has been detected. + 0 + + + NOVIO1 + No access violation has been detected. + 0x1 + + + SINGLE + A single access violation has been detected. + 0x2 + + + MULTI + Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + 0x3 + + + + + + + MBC0_DERR_W3 + MBC Domain Error Word3 Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECR + Rearm Error Capture Registers + 30 + 2 + read-write + + + + + MBC1_DERR_W0 + MBC Domain Error Word0 Register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + EADDR + Error address + 0 + 32 + read-only + + + + + MBC1_DERR_W1 + MBC Domain Error Word1 Register + 0x414 + 32 + read-only + 0 + 0xFFFFFFFF + + + EDID + Error domain identifier + 0 + 4 + read-only + + + EATR + Error attributes + 8 + 3 + read-only + + + SUI + Secure user mode, instruction fetch access. + 0 + + + SUD + Secure user mode, data access. + 0x1 + + + SPI + Secure privileged mode, instruction fetch access. + 0x2 + + + SPD + Secure privileged mode, data access. + 0x3 + + + NSUI + Nonsecure user mode, instruction fetch access. + 0x4 + + + NSUD + Nonsecure user mode, data access. + 0x5 + + + NSPI + Nonsecure privileged mode, instruction fetch access. + 0x6 + + + NSPD + Nonsecure privileged mode, data access. + 0x7 + + + + + ERW + Error read/write + 11 + 1 + read-only + + + read + Read access + 0 + + + write + Write access + 0x1 + + + + + EPORT + Error port + 24 + 3 + read-only + + + S0 + mbcxslv0 + 0 + + + S1 + mbcxslv1 + 0x1 + + + S2 + mbcxslv2 + 0x2 + + + S3 + mbcxslv3 + 0x3 + + + + + EST + Error state + 30 + 2 + read-only + + + NOVIO0 + No access violation has been detected. + 0 + + + NOVIO1 + No access violation has been detected. + 0x1 + + + SINGLE + A single access violation has been detected. + 0x2 + + + MULTI + Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + 0x3 + + + + + + + MBC1_DERR_W3 + MBC Domain Error Word3 Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECR + Rearm Error Capture Registers + 30 + 2 + read-write + + + + + MBC2_DERR_W0 + MBC Domain Error Word0 Register + 0x420 + 32 + read-only + 0 + 0xFFFFFFFF + + + EADDR + Error address + 0 + 32 + read-only + + + + + MBC2_DERR_W1 + MBC Domain Error Word1 Register + 0x424 + 32 + read-only + 0 + 0xFFFFFFFF + + + EDID + Error domain identifier + 0 + 4 + read-only + + + EATR + Error attributes + 8 + 3 + read-only + + + SUI + Secure user mode, instruction fetch access. + 0 + + + SUD + Secure user mode, data access. + 0x1 + + + SPI + Secure privileged mode, instruction fetch access. + 0x2 + + + SPD + Secure privileged mode, data access. + 0x3 + + + NSUI + Nonsecure user mode, instruction fetch access. + 0x4 + + + NSUD + Nonsecure user mode, data access. + 0x5 + + + NSPI + Nonsecure privileged mode, instruction fetch access. + 0x6 + + + NSPD + Nonsecure privileged mode, data access. + 0x7 + + + + + ERW + Error read/write + 11 + 1 + read-only + + + read + Read access + 0 + + + write + Write access + 0x1 + + + + + EPORT + Error port + 24 + 3 + read-only + + + S0 + mbcxslv0 + 0 + + + S1 + mbcxslv1 + 0x1 + + + S2 + mbcxslv2 + 0x2 + + + S3 + mbcxslv3 + 0x3 + + + + + EST + Error state + 30 + 2 + read-only + + + NOVIO0 + No access violation has been detected. + 0 + + + NOVIO1 + No access violation has been detected. + 0x1 + + + SINGLE + A single access violation has been detected. + 0x2 + + + MULTI + Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + 0x3 + + + + + + + MBC2_DERR_W3 + MBC Domain Error Word3 Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECR + Rearm Error Capture Registers + 30 + 2 + read-write + + + + + MRC0_DERR_W0 + MRC Domain Error Word0 Register + 0x480 + 32 + read-only + 0 + 0xFFFFFFFF + + + EADDR + Error address + 0 + 32 + read-only + + + + + MRC0_DERR_W1 + MRC Domain Error Word1 Register + 0x484 + 32 + read-only + 0 + 0xFFFFFFFF + + + EDID + Error domain identifier + 0 + 4 + read-only + + + EATR + Error attributes + 8 + 3 + read-only + + + SUI + Secure user mode, instruction fetch access. + 0 + + + SUD + Secure user mode, data access. + 0x1 + + + SPI + Secure privileged mode, instruction fetch access. + 0x2 + + + SPD + Secure privileged mode, data access. + 0x3 + + + NSUI + Nonsecure user mode, instruction fetch access. + 0x4 + + + NSUD + Nonsecure user mode, data access. + 0x5 + + + NSPI + Nonsecure privileged mode, instruction fetch access. + 0x6 + + + NSPD + Nonsecure privileged mode, data access. + 0x7 + + + + + ERW + Error read/write + 11 + 1 + read-only + + + read + Read access + 0 + + + write + Write access + 0x1 + + + + + EPORT + Error port + 24 + 3 + read-only + + + EST + Error state + 30 + 2 + read-only + + + NOVIO_0 + No access violation has been detected. + 0 + + + NOVIO_1 + No access violation has been detected. + 0x1 + + + SINGLE + A single access violation has been detected. + 0x2 + + + MULTI + Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + 0x3 + + + + + + + MRC0_DERR_W3 + MRC Domain Error Word3 Register + 0x48C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECR + Rearm Error Capture Registers + 30 + 2 + read-write + + + + + MDA_W0_0_DFMT0 + DAC Master Domain Assignment Register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + DID + Domain identifier + 0 + 4 + read-write + + + DIDS + DID Select + 4 + 2 + read-write + + + zero + Use MDAm[3:0] as the domain identifier. + 0 + + + one + Use the input DID as the domain identifier. + 0x1 + + + two + Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. + 0x2 + + + + + DFMT + Domain format + 29 + 1 + read-only + + + CPU + Processor-core domain assignment + 0 + + + NONCPU + Non-processor domain assignment + 0x1 + + + + + LK1 + 1-bit Lock + 30 + 1 + read-write + + + UNLOCK + Register can be written by any secure privileged write. + 0 + + + LOCKED + Register is locked (read-only) until the next reset. + 0x1 + + + + + VLD + Valid + 31 + 1 + read-write + + + invalid + The Wr domain assignment is invalid. + 0 + + + valid + The Wr domain assignment is valid. + 0x1 + + + + + + + MDA_W0_1_DFMT1 + DAC Master Domain Assignment Register + 0x820 + 32 + read-write + 0x20000000 + 0xFFFFFFFF + + + DID + Domain identifier + 0 + 4 + read-write + + + PA + Privileged attribute + 4 + 2 + read-write + + + zero + Force the bus attribute for this master to user. + 0 + + + one + Force the bus attribute for this master to privileged. + 0x1 + + + two + Use the bus master's privileged/user attribute directly. + 0x2 + + + three + Use the bus master's privileged/user attribute directly. + 0x3 + + + + + SA + Secure attribute + 6 + 2 + read-write + + + zero + Force the bus attribute for this master to secure. + 0 + + + one + Force the bus attribute for this master to nonsecure. + 0x1 + + + two + Use the bus master's secure/nonsecure attribute directly. + 0x2 + + + three + Use the bus master's secure/nonsecure attribute directly. + 0x3 + + + + + DIDB + DID Bypass + 8 + 1 + read-write + oneToSet + + + REG + Use MDAn[3:0] as the domain identifier. + 0 + + + INPUT + Use the DID input as the domain identifier. + 0x1 + + + + + DFMT + Domain format + 29 + 1 + read-only + + + CPU + Processor-core domain assignment + 0 + + + NONCPU + Non-processor domain assignment + 0x1 + + + + + LK1 + 1-bit Lock + 30 + 1 + read-write + + + UNLOCK + Register can be written by any secure privileged write. + 0 + + + LOCKED + Register is locked (read-only) until the next reset. + 0x1 + + + + + VLD + Valid + 31 + 1 + read-write + + + invalid + The Wr domain assignment is invalid. + 0 + + + valid + The Wr domain assignment is valid. + 0x1 + + + + + + + MDA_W0_2_DFMT1 + DAC Master Domain Assignment Register + 0x840 + 32 + read-write + 0x20000000 + 0xFFFFFFFF + + + DID + Domain identifier + 0 + 4 + read-write + + + PA + Privileged attribute + 4 + 2 + read-write + + + zero + Force the bus attribute for this master to user. + 0 + + + one + Force the bus attribute for this master to privileged. + 0x1 + + + two + Use the bus master's privileged/user attribute directly. + 0x2 + + + three + Use the bus master's privileged/user attribute directly. + 0x3 + + + + + SA + Secure attribute + 6 + 2 + read-write + + + zero + Force the bus attribute for this master to secure. + 0 + + + one + Force the bus attribute for this master to nonsecure. + 0x1 + + + two + Use the bus master's secure/nonsecure attribute directly. + 0x2 + + + three + Use the bus master's secure/nonsecure attribute directly. + 0x3 + + + + + DIDB + DID Bypass + 8 + 1 + read-write + oneToSet + + + REG + Use MDAn[3:0] as the domain identifier. + 0 + + + INPUT + Use the DID input as the domain identifier. + 0x1 + + + + + DFMT + Domain format + 29 + 1 + read-only + + + CPU + Processor-core domain assignment + 0 + + + NONCPU + Non-processor domain assignment + 0x1 + + + + + LK1 + 1-bit Lock + 30 + 1 + read-write + + + UNLOCK + Register can be written by any secure privileged write. + 0 + + + LOCKED + Register is locked (read-only) until the next reset. + 0x1 + + + + + VLD + Valid + 31 + 1 + read-write + + + invalid + The Wr domain assignment is invalid. + 0 + + + valid + The Wr domain assignment is valid. + 0x1 + + + + + + + MDA_W0_3_DFMT1 + DAC Master Domain Assignment Register + 0x860 + 32 + read-write + 0x20000000 + 0xFFFFFFFF + + + DID + Domain identifier + 0 + 4 + read-write + + + PA + Privileged attribute + 4 + 2 + read-write + + + zero + Force the bus attribute for this master to user. + 0 + + + one + Force the bus attribute for this master to privileged. + 0x1 + + + two + Use the bus master's privileged/user attribute directly. + 0x2 + + + three + Use the bus master's privileged/user attribute directly. + 0x3 + + + + + SA + Secure attribute + 6 + 2 + read-write + + + zero + Force the bus attribute for this master to secure. + 0 + + + one + Force the bus attribute for this master to nonsecure. + 0x1 + + + two + Use the bus master's secure/nonsecure attribute directly. + 0x2 + + + three + Use the bus master's secure/nonsecure attribute directly. + 0x3 + + + + + DIDB + DID Bypass + 8 + 1 + read-write + oneToSet + + + REG + Use MDAn[3:0] as the domain identifier. + 0 + + + INPUT + Use the DID input as the domain identifier. + 0x1 + + + + + DFMT + Domain format + 29 + 1 + read-only + + + CPU + Processor-core domain assignment + 0 + + + NONCPU + Non-processor domain assignment + 0x1 + + + + + LK1 + 1-bit Lock + 30 + 1 + read-write + + + UNLOCK + Register can be written by any secure privileged write. + 0 + + + LOCKED + Register is locked (read-only) until the next reset. + 0x1 + + + + + VLD + Valid + 31 + 1 + read-write + + + invalid + The Wr domain assignment is invalid. + 0 + + + valid + The Wr domain assignment is valid. + 0x1 + + + + + + + MBC0_MEM0_GLBCFG + MBC Global Configuration Register + 0x1000 + 32 + read-only + 0xC0020 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC0_MEM1_GLBCFG + MBC Global Configuration Register + 0x1004 + 32 + read-only + 0xC0004 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC0_MEM2_GLBCFG + MBC Global Configuration Register + 0x1008 + 32 + read-only + 0xC0001 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC0_MEM3_GLBCFG + MBC Global Configuration Register + 0x100C + 32 + read-only + 0xC000C + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC0_NSE_BLK_INDEX + MBC NonSecure Enable Block Index + 0x1010 + 32 + read-write + 0 + 0xFFFFFFFF + + + WNDX + Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. + 2 + 4 + read-write + + + MEM_SEL + Memory Select + 8 + 4 + read-write + + + DID_SEL0 + DID Select + 16 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + DID_SEL1 + DID Select + 17 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + DID_SEL2 + DID Select + 18 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + AI + Auto Increment + 31 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Add 1 to the WNDX field after the register write. + 0x1 + + + + + + + MBC0_NSE_BLK_SET + MBC NonSecure Enable Block Set + 0x1014 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1SET + Write-1 Set + 0 + 32 + read-write + + + + + MBC0_NSE_BLK_CLR + MBC NonSecure Enable Block Clear + 0x1018 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1CLR + Write-1 Clear + 0 + 32 + read-write + + + + + MBC0_NSE_BLK_CLR_ALL + MBC NonSecure Enable Block Clear All + 0x101C + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMSEL + Memory Select + 8 + 4 + read-write + + + DID_SEL + DID Select + 16 + 3 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Clear all NSE bits for this domain. + 0x1 + + + + + + + MBC0_MEMN_GLBAC0 + MBC Global Access Control + 0x1020 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + + + MBC0_MEMN_GLBAC1 + MBC Global Access Control + 0x1024 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_MEMN_GLBAC2 + MBC Global Access Control + 0x1028 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_MEMN_GLBAC3 + MBC Global Access Control + 0x102C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_MEMN_GLBAC4 + MBC Global Access Control + 0x1030 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_MEMN_GLBAC5 + MBC Global Access Control + 0x1034 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_MEMN_GLBAC6 + MBC Global Access Control + 0x1038 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_MEMN_GLBAC7 + MBC Global Access Control + 0x103C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC0_DOM0_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x1040 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM0_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x1044 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM0_BLK_CFG_W2 + MBC Memory Block Configuration Word + 0x1048 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM0_BLK_CFG_W3 + MBC Memory Block Configuration Word + 0x104C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x1140 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x1180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x11A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x11A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x11C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM3_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x11D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM3_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x11D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM0_MEM3_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x11F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x1240 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM0_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x1244 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM0_BLK_CFG_W2 + MBC Memory Block Configuration Word + 0x1248 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM0_BLK_CFG_W3 + MBC Memory Block Configuration Word + 0x124C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x1340 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x1380 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x13A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x13A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x13C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM3_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x13D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM3_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x13D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM1_MEM3_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x13F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x1440 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM0_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x1444 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM0_BLK_CFG_W2 + MBC Memory Block Configuration Word + 0x1448 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM0_BLK_CFG_W3 + MBC Memory Block Configuration Word + 0x144C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x1540 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x1580 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x15A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x15A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x15C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM3_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x15D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM3_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x15D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC0_DOM2_MEM3_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x15F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_MEM0_GLBCFG + MBC Global Configuration Register + 0x2000 + 32 + read-only + 0xC0002 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC1_MEM1_GLBCFG + MBC Global Configuration Register + 0x2004 + 32 + read-only + 0xC0008 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC1_MEM2_GLBCFG + MBC Global Configuration Register + 0x2008 + 32 + read-only + 0xC0005 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC1_MEM3_GLBCFG + MBC Global Configuration Register + 0x200C + 32 + read-only + 0xC0002 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC1_NSE_BLK_INDEX + MBC NonSecure Enable Block Index + 0x2010 + 32 + read-write + 0 + 0xFFFFFFFF + + + WNDX + Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. + 2 + 4 + read-write + + + MEM_SEL + Memory Select + 8 + 4 + read-write + + + DID_SEL0 + DID Select + 16 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + DID_SEL1 + DID Select + 17 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + DID_SEL2 + DID Select + 18 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + AI + Auto Increment + 31 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Add 1 to the WNDX field after the register write. + 0x1 + + + + + + + MBC1_NSE_BLK_SET + MBC NonSecure Enable Block Set + 0x2014 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1SET + Write-1 Set + 0 + 32 + read-write + + + + + MBC1_NSE_BLK_CLR + MBC NonSecure Enable Block Clear + 0x2018 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1CLR + Write-1 Clear + 0 + 32 + read-write + + + + + MBC1_NSE_BLK_CLR_ALL + MBC NonSecure Enable Block Clear All + 0x201C + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMSEL + Memory Select + 8 + 4 + read-write + + + DID_SEL + DID Select + 16 + 3 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Clear all NSE bits for this domain. + 0x1 + + + + + + + MBC1_MEMN_GLBAC0 + MBC Global Access Control + 0x2020 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + + + MBC1_MEMN_GLBAC1 + MBC Global Access Control + 0x2024 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_MEMN_GLBAC2 + MBC Global Access Control + 0x2028 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_MEMN_GLBAC3 + MBC Global Access Control + 0x202C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_MEMN_GLBAC4 + MBC Global Access Control + 0x2030 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_MEMN_GLBAC5 + MBC Global Access Control + 0x2034 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_MEMN_GLBAC6 + MBC Global Access Control + 0x2038 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_MEMN_GLBAC7 + MBC Global Access Control + 0x203C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC1_DOM0_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x2040 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x2140 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x21A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x21A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x21C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM3_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x21D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM0_MEM3_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x21F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x2240 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x2340 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x2380 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x23A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x23A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x23C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM3_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x23D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM1_MEM3_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x23F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x2440 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x2540 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x2580 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x25A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x25A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x25C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM3_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x25D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC1_DOM2_MEM3_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x25F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_MEM0_GLBCFG + MBC Global Configuration Register + 0x3000 + 32 + read-only + 0xC004F + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC2_MEM1_GLBCFG + MBC Global Configuration Register + 0x3004 + 32 + read-only + 0xC0004 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC2_MEM2_GLBCFG + MBC Global Configuration Register + 0x3008 + 32 + read-only + 0xC0010 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC2_MEM3_GLBCFG + MBC Global Configuration Register + 0x300C + 32 + read-only + 0xC0000 + 0xFFFFFFFF + + + NBLKS + Number of blocks in this memory + 0 + 10 + read-only + + + SIZE_LOG2 + Log2 size per block + 16 + 5 + read-only + + + + + MBC2_NSE_BLK_INDEX + MBC NonSecure Enable Block Index + 0x3010 + 32 + read-write + 0 + 0xFFFFFFFF + + + WNDX + Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. + 2 + 4 + read-write + + + MEM_SEL + Memory Select + 8 + 4 + read-write + + + DID_SEL0 + DID Select + 16 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + DID_SEL1 + DID Select + 17 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + DID_SEL2 + DID Select + 18 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Selects NSE bits for this domain. + 0x1 + + + + + AI + Auto Increment + 31 + 1 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Add 1 to the WNDX field after the register write. + 0x1 + + + + + + + MBC2_NSE_BLK_SET + MBC NonSecure Enable Block Set + 0x3014 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1SET + Write-1 Set + 0 + 32 + read-write + + + + + MBC2_NSE_BLK_CLR + MBC NonSecure Enable Block Clear + 0x3018 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1CLR + Write-1 Clear + 0 + 32 + read-write + + + + + MBC2_NSE_BLK_CLR_ALL + MBC NonSecure Enable Block Clear All + 0x301C + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMSEL + Memory Select + 8 + 4 + read-write + + + DID_SEL + DID Select + 16 + 3 + read-write + + + LOGIC_0 + No effect. + 0 + + + LOGIC_1 + Clear all NSE bits for this domain. + 0x1 + + + + + + + MBC2_MEMN_GLBAC0 + MBC Global Access Control + 0x3020 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + + + MBC2_MEMN_GLBAC1 + MBC Global Access Control + 0x3024 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_MEMN_GLBAC2 + MBC Global Access Control + 0x3028 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_MEMN_GLBAC3 + MBC Global Access Control + 0x302C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_MEMN_GLBAC4 + MBC Global Access Control + 0x3030 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_MEMN_GLBAC5 + MBC Global Access Control + 0x3034 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_MEMN_GLBAC6 + MBC Global Access Control + 0x3038 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_MEMN_GLBAC7 + MBC Global Access Control + 0x303C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCKED + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked and cannot be altered. + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x3040 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x3044 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W2 + MBC Memory Block Configuration Word + 0x3048 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W3 + MBC Memory Block Configuration Word + 0x304C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W4 + MBC Memory Block Configuration Word + 0x3050 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W5 + MBC Memory Block Configuration Word + 0x3054 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W6 + MBC Memory Block Configuration Word + 0x3058 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W7 + MBC Memory Block Configuration Word + 0x305C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W8 + MBC Memory Block Configuration Word + 0x3060 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_CFG_W9 + MBC Memory Block Configuration Word + 0x3064 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x3140 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_NSE_W1 + MBC Memory Block NonSecure Enable Word + 0x3144 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM0_BLK_NSE_W2 + MBC Memory Block NonSecure Enable Word + 0x3148 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x3180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x31A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x31A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM2_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x31AC + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM0_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x31C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x3240 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x3244 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W2 + MBC Memory Block Configuration Word + 0x3248 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W3 + MBC Memory Block Configuration Word + 0x324C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W4 + MBC Memory Block Configuration Word + 0x3250 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W5 + MBC Memory Block Configuration Word + 0x3254 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W6 + MBC Memory Block Configuration Word + 0x3258 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W7 + MBC Memory Block Configuration Word + 0x325C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W8 + MBC Memory Block Configuration Word + 0x3260 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_CFG_W9 + MBC Memory Block Configuration Word + 0x3264 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x3340 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_NSE_W1 + MBC Memory Block NonSecure Enable Word + 0x3344 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM0_BLK_NSE_W2 + MBC Memory Block NonSecure Enable Word + 0x3348 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x3380 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x33A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x33A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM2_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x33AC + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM1_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x33C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x3440 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x3444 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W2 + MBC Memory Block Configuration Word + 0x3448 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W3 + MBC Memory Block Configuration Word + 0x344C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W4 + MBC Memory Block Configuration Word + 0x3450 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W5 + MBC Memory Block Configuration Word + 0x3454 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W6 + MBC Memory Block Configuration Word + 0x3458 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W7 + MBC Memory Block Configuration Word + 0x345C + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W8 + MBC Memory Block Configuration Word + 0x3460 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_CFG_W9 + MBC Memory Block Configuration Word + 0x3464 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x3540 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_NSE_W1 + MBC Memory Block NonSecure Enable Word + 0x3544 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM0_BLK_NSE_W2 + MBC Memory Block NonSecure Enable Word + 0x3548 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM1_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x3580 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM1_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x35A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM2_BLK_CFG_W0 + MBC Memory Block Configuration Word + 0x35A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM2_BLK_CFG_W1 + MBC Memory Block Configuration Word + 0x35AC + 32 + read-write + 0 + 0xFFFFFFFF + + + MBACSEL0 + Memory Block Access Control Select for block B + 0 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE0 + NonSecure Enable for block B + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL1 + Memory Block Access Control Select for block B + 4 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE1 + NonSecure Enable for block B + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL2 + Memory Block Access Control Select for block B + 8 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE2 + NonSecure Enable for block B + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL3 + Memory Block Access Control Select for block B + 12 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE3 + NonSecure Enable for block B + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL4 + Memory Block Access Control Select for block B + 16 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE4 + NonSecure Enable for block B + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL5 + Memory Block Access Control Select for block B + 20 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE5 + NonSecure Enable for block B + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL6 + Memory Block Access Control Select for block B + 24 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE6 + NonSecure Enable for block B + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + MBACSEL7 + Memory Block Access Control Select for block B + 28 + 3 + read-write + + + GLBAC0 + select MBC_MEMN_GLBAC0 access control policy for block B + 0 + + + GLBAC1 + select MBC_MEMN_GLBAC1 access control policy for block B + 0x1 + + + GLBAC2 + select MBC_MEMN_GLBAC2 access control policy for block B + 0x2 + + + GLBAC3 + select MBC_MEMN_GLBAC3 access control policy for block B + 0x3 + + + GLBAC4 + select MBC_MEMN_GLBAC4 access control policy for block B + 0x4 + + + GLBAC5 + select MBC_MEMN_GLBAC5 access control policy for block B + 0x5 + + + GLBAC6 + select MBC_MEMN_GLBAC6 access control policy for block B + 0x6 + + + GLBAC7 + select MBC_MEMN_GLBAC7 access control policy for block B + 0x7 + + + + + NSE7 + NonSecure Enable for block B + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MBC2_DOM2_MEM2_BLK_NSE_W0 + MBC Memory Block NonSecure Enable Word + 0x35C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit b NonSecure Enable [b = 0 - 31] + 0 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT1 + Bit b NonSecure Enable [b = 0 - 31] + 1 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT2 + Bit b NonSecure Enable [b = 0 - 31] + 2 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT3 + Bit b NonSecure Enable [b = 0 - 31] + 3 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT4 + Bit b NonSecure Enable [b = 0 - 31] + 4 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT5 + Bit b NonSecure Enable [b = 0 - 31] + 5 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT6 + Bit b NonSecure Enable [b = 0 - 31] + 6 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT7 + Bit b NonSecure Enable [b = 0 - 31] + 7 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT8 + Bit b NonSecure Enable [b = 0 - 31] + 8 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT9 + Bit b NonSecure Enable [b = 0 - 31] + 9 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT10 + Bit b NonSecure Enable [b = 0 - 31] + 10 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT11 + Bit b NonSecure Enable [b = 0 - 31] + 11 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT12 + Bit b NonSecure Enable [b = 0 - 31] + 12 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT13 + Bit b NonSecure Enable [b = 0 - 31] + 13 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT14 + Bit b NonSecure Enable [b = 0 - 31] + 14 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT15 + Bit b NonSecure Enable [b = 0 - 31] + 15 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT16 + Bit b NonSecure Enable [b = 0 - 31] + 16 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT17 + Bit b NonSecure Enable [b = 0 - 31] + 17 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT18 + Bit b NonSecure Enable [b = 0 - 31] + 18 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT19 + Bit b NonSecure Enable [b = 0 - 31] + 19 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT20 + Bit b NonSecure Enable [b = 0 - 31] + 20 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT21 + Bit b NonSecure Enable [b = 0 - 31] + 21 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT22 + Bit b NonSecure Enable [b = 0 - 31] + 22 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT23 + Bit b NonSecure Enable [b = 0 - 31] + 23 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT24 + Bit b NonSecure Enable [b = 0 - 31] + 24 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT25 + Bit b NonSecure Enable [b = 0 - 31] + 25 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT26 + Bit b NonSecure Enable [b = 0 - 31] + 26 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT27 + Bit b NonSecure Enable [b = 0 - 31] + 27 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT28 + Bit b NonSecure Enable [b = 0 - 31] + 28 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT29 + Bit b NonSecure Enable [b = 0 - 31] + 29 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT30 + Bit b NonSecure Enable [b = 0 - 31] + 30 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + BIT31 + Bit b NonSecure Enable [b = 0 - 31] + 31 + 1 + read-write + + + ALLOWED + Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + 0 + + + NOTALLOWED + Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + 0x1 + + + + + + + MRC0_GLBCFG + MRC Global Configuration Register + 0x4000 + 32 + read-only + 0x8 + 0xFFFFFFFF + + + NRGNS + Number of regions [1-16] + 0 + 5 + read-only + + + + + MRC0_NSE_RGN_INDIRECT + MRC NonSecure Enable Region Indirect + 0x4010 + 32 + read-write + 0 + 0xFFFFFFFF + + + DID_SEL + DID Select + 16 + 8 + read-write + + + + + MRC0_NSE_RGN_SET + MRC NonSecure Enable Region Set + 0x4014 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1SET + Write-1 Set + 0 + 16 + read-write + + + + + MRC0_NSE_RGN_CLR + MRC NonSecure Enable Region Clear + 0x4018 + 32 + read-write + 0 + 0xFFFFFFFF + + + W1CLR + Write-1 Clear + 0 + 16 + read-write + + + + + MRC0_NSE_RGN_CLR_ALL + MRC NonSecure Enable Region Clear All + 0x401C + 32 + read-write + 0 + 0xFFFFFFFF + + + DID_SEL + DID Select + 16 + 8 + read-write + + + + + MRC0_GLBAC0 + MRC Global Access Control + 0x4020 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + + + MRC0_GLBAC1 + MRC Global Access Control + 0x4024 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_GLBAC2 + MRC Global Access Control + 0x4028 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_GLBAC3 + MRC Global Access Control + 0x402C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_GLBAC4 + MRC Global Access Control + 0x4030 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_GLBAC5 + MRC Global Access Control + 0x4034 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_GLBAC6 + MRC Global Access Control + 0x4038 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_GLBAC7 + MRC Global Access Control + 0x403C + 32 + read-write + 0 + 0xFFFFFFFF + + + NUX + NonsecureUser Execute + 0 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure User mode. + 0x1 + + + + + NUW + NonsecureUser Write + 1 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure User mode. + 0x1 + + + + + NUR + NonsecureUser Read + 2 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure User mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure User mode. + 0x1 + + + + + NPX + NonsecurePriv Execute + 4 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPW + NonsecurePriv Write + 5 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + NPR + NonsecurePriv Read + 6 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Nonsecure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Nonsecure Privilege mode. + 0x1 + + + + + SUX + SecureUser Execute + 8 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure User mode. + 0 + + + ALLOWED + Execute access is allowed in Secure User mode. + 0x1 + + + + + SUW + SecureUser Write + 9 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure User mode. + 0 + + + ALLOWED + Write access is allowed in Secure User mode. + 0x1 + + + + + SUR + SecureUser Read + 10 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure User mode. + 0 + + + ALLOWED + Read access is allowed in Secure User mode. + 0x1 + + + + + SPX + SecurePriv Execute + 12 + 1 + read-write + + + NOTALLOWED + Execute access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Execute access is allowed in Secure Privilege mode. + 0x1 + + + + + SPW + SecurePriv Write + 13 + 1 + read-write + + + NOTALLOWED + Write access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Write access is allowed in Secure Privilege mode. + 0x1 + + + + + SPR + SecurePriv Read + 14 + 1 + read-write + + + NOTALLOWED + Read access is not allowed in Secure Privilege mode. + 0 + + + ALLOWED + Read access is allowed in Secure Privilege mode. + 0x1 + + + + + LK + LOCK + 31 + 1 + read-write + + + UNLOCK + This register is not locked and can be altered. + 0 + + + LOCKED + This register is locked (read-only) and cannot be altered. + 0x1 + + + + + + + MRC0_DOM0_RGD0_W0 + MRC Region Descriptor Word 0 + 0x4040 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD0_W1 + MRC Region Descriptor Word 1 + 0x4044 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD1_W0 + MRC Region Descriptor Word 0 + 0x4048 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD1_W1 + MRC Region Descriptor Word 1 + 0x404C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD2_W0 + MRC Region Descriptor Word 0 + 0x4050 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD2_W1 + MRC Region Descriptor Word 1 + 0x4054 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD3_W0 + MRC Region Descriptor Word 0 + 0x4058 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD3_W1 + MRC Region Descriptor Word 1 + 0x405C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD4_W0 + MRC Region Descriptor Word 0 + 0x4060 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD4_W1 + MRC Region Descriptor Word 1 + 0x4064 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD5_W0 + MRC Region Descriptor Word 0 + 0x4068 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD5_W1 + MRC Region Descriptor Word 1 + 0x406C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD6_W0 + MRC Region Descriptor Word 0 + 0x4070 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD6_W1 + MRC Region Descriptor Word 1 + 0x4074 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD7_W0 + MRC Region Descriptor Word 0 + 0x4078 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD7_W1 + MRC Region Descriptor Word 1 + 0x407C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM0_RGD_NSE + MRC Region Descriptor NonSecure Enable + 0x40C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit n NonSecure Enable [n = 0 - 15] + 0 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT1 + Bit n NonSecure Enable [n = 0 - 15] + 1 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT2 + Bit n NonSecure Enable [n = 0 - 15] + 2 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT3 + Bit n NonSecure Enable [n = 0 - 15] + 3 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT4 + Bit n NonSecure Enable [n = 0 - 15] + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT5 + Bit n NonSecure Enable [n = 0 - 15] + 5 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT6 + Bit n NonSecure Enable [n = 0 - 15] + 6 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT7 + Bit n NonSecure Enable [n = 0 - 15] + 7 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + + + MRC0_DOM1_RGD0_W0 + MRC Region Descriptor Word 0 + 0x4140 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD0_W1 + MRC Region Descriptor Word 1 + 0x4144 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD1_W0 + MRC Region Descriptor Word 0 + 0x4148 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD1_W1 + MRC Region Descriptor Word 1 + 0x414C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD2_W0 + MRC Region Descriptor Word 0 + 0x4150 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD2_W1 + MRC Region Descriptor Word 1 + 0x4154 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD3_W0 + MRC Region Descriptor Word 0 + 0x4158 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD3_W1 + MRC Region Descriptor Word 1 + 0x415C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD4_W0 + MRC Region Descriptor Word 0 + 0x4160 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD4_W1 + MRC Region Descriptor Word 1 + 0x4164 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD5_W0 + MRC Region Descriptor Word 0 + 0x4168 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD5_W1 + MRC Region Descriptor Word 1 + 0x416C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD6_W0 + MRC Region Descriptor Word 0 + 0x4170 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD6_W1 + MRC Region Descriptor Word 1 + 0x4174 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD7_W0 + MRC Region Descriptor Word 0 + 0x4178 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD7_W1 + MRC Region Descriptor Word 1 + 0x417C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM1_RGD_NSE + MRC Region Descriptor NonSecure Enable + 0x41C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit n NonSecure Enable [n = 0 - 15] + 0 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT1 + Bit n NonSecure Enable [n = 0 - 15] + 1 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT2 + Bit n NonSecure Enable [n = 0 - 15] + 2 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT3 + Bit n NonSecure Enable [n = 0 - 15] + 3 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT4 + Bit n NonSecure Enable [n = 0 - 15] + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT5 + Bit n NonSecure Enable [n = 0 - 15] + 5 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT6 + Bit n NonSecure Enable [n = 0 - 15] + 6 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT7 + Bit n NonSecure Enable [n = 0 - 15] + 7 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + + + MRC0_DOM2_RGD0_W0 + MRC Region Descriptor Word 0 + 0x4240 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD0_W1 + MRC Region Descriptor Word 1 + 0x4244 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD1_W0 + MRC Region Descriptor Word 0 + 0x4248 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD1_W1 + MRC Region Descriptor Word 1 + 0x424C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD2_W0 + MRC Region Descriptor Word 0 + 0x4250 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD2_W1 + MRC Region Descriptor Word 1 + 0x4254 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD3_W0 + MRC Region Descriptor Word 0 + 0x4258 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD3_W1 + MRC Region Descriptor Word 1 + 0x425C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD4_W0 + MRC Region Descriptor Word 0 + 0x4260 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD4_W1 + MRC Region Descriptor Word 1 + 0x4264 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD5_W0 + MRC Region Descriptor Word 0 + 0x4268 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD5_W1 + MRC Region Descriptor Word 1 + 0x426C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD6_W0 + MRC Region Descriptor Word 0 + 0x4270 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD6_W1 + MRC Region Descriptor Word 1 + 0x4274 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD7_W0 + MRC Region Descriptor Word 0 + 0x4278 + 32 + read-write + 0 + 0xFFFFFFFF + + + MRACSEL + Memory Region Access Control Select + 0 + 3 + read-write + + + SEL0 + Select MRC_GLBAC0 access control policy + 0 + + + SEL1 + Select MRC_GLBAC1 access control policy + 0x1 + + + SEL2 + Select MRC_GLBAC2 access control policy + 0x2 + + + SEL3 + Select MRC_GLBAC3 access control policy + 0x3 + + + SEL4 + Select MRC_GLBAC4 access control policy + 0x4 + + + SEL5 + Select MRC_GLBAC5 access control policy + 0x5 + + + SEL6 + Select MRC_GLBAC6 access control policy + 0x6 + + + SEL7 + Select MRC_GLBAC7 access control policy + 0x7 + + + + + STRT_ADDR + Start Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD7_W1 + MRC Region Descriptor Word 1 + 0x427C + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + NSE + NonSecure Enable + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + END_ADDR + End Address + 12 + 20 + read-write + + + + + MRC0_DOM2_RGD_NSE + MRC Region Descriptor NonSecure Enable + 0x42C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BIT0 + Bit n NonSecure Enable [n = 0 - 15] + 0 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT1 + Bit n NonSecure Enable [n = 0 - 15] + 1 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT2 + Bit n NonSecure Enable [n = 0 - 15] + 2 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT3 + Bit n NonSecure Enable [n = 0 - 15] + 3 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT4 + Bit n NonSecure Enable [n = 0 - 15] + 4 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT5 + Bit n NonSecure Enable [n = 0 - 15] + 5 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT6 + Bit n NonSecure Enable [n = 0 - 15] + 6 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + BIT7 + Bit n NonSecure Enable [n = 0 - 15] + 7 + 1 + read-write + + + SECURE + Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0 + + + NONSEC + Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + 0x1 + + + + + + + + + VBAT0 + VBAT + VBAT + 0x4002B000 + + 0 + 0x33C + registers + + + VBAT + 74 + + + + VERID + Version ID + 0 + 32 + read-only + 0x1000003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + STATUSA + Status A + 0x10 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POR_DET + POR Detect + 0 + 1 + read-write + oneToClear + + + CLR + VBAT domain has not been reset + 0 + + + SET + VBAT domain has been reset + 0x1 + + + + + WAKEUP_FLAG + Wakeup Pin Flag + 1 + 1 + read-write + oneToClear + + + CLR + Wakeup pin not asserted + 0 + + + SET + Wakeup pin asserted + 0x1 + + + + + TIMER0_FLAG + Bandgap Timer 0 + 2 + 1 + read-write + oneToClear + + + CLR + Timeout 0 period not reached + 0 + + + SET + Timeout 0 period reached + 0x1 + + + + + TIMER1_FLAG + Bandgap Timer 1 + 3 + 1 + read-write + oneToClear + + + CLR + Timeout 1 period not reached + 0 + + + SET + Timeout 1 period reached + 0x1 + + + + + LDO_RDY + LDO Ready + 4 + 1 + read-only + + + CLR + LDO is disabled or not ready + 0 + + + SET + LDO is enabled and ready + 0x1 + + + + + + + IRQENA + Interrupt Enable A + 0x18 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POR_DET + POR Detect + 0 + 1 + read-write + + + DISABLE + Interrupt disabled + 0 + + + ENABLE + Interrupt enabled + 0x1 + + + + + WAKEUP_FLAG + Wakeup Pin Flag + 1 + 1 + read-write + + + CLR + Interrupt disabled + 0 + + + SET + Interrupt enabled + 0x1 + + + + + TIMER0_FLAG + Bandgap Timer 0 + 2 + 1 + read-write + + + DISABLE + Interrupt disabled + 0 + + + ENABLE + Interrupt enabled + 0x1 + + + + + TIMER1_FLAG + Bandgap Timer 2 + 3 + 1 + read-write + + + DISABLE + Interrupt disabled + 0 + + + ENABLE + Interrupt enabled + 0x1 + + + + + LDO_RDY + LDO Ready + 4 + 1 + read-write + + + DISABLE + Interrupt disabled + 0 + + + ENABLE + Interrupt enabled + 0x1 + + + + + + + WAKENA + Wakeup Enable A + 0x20 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POR_DET + POR Detect + 0 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + WAKEUP_FLAG + Wakeup Pin Flag + 1 + 1 + read-write + + + CLR + Disabled + 0 + + + SET + Enabled + 0x1 + + + + + TIMER0_FLAG + Bandgap Timer 0 + 2 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + TIMER1_FLAG + Bandgap Timer 2 + 3 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + LDO_RDY + LDO Ready + 4 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + + + LOCKA + Lock A + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + Lock + 0 + 1 + read-write + + + DISABLE + Disables lock + 0 + + + ENABLE + Enables lock. Cleared by VBAT POR. + 0x1 + + + + + + + FROCTLA + FRO16K Control A + 0x200 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + FRO_EN + FRO16K enable bit + 0 + 1 + read-write + + + DISABLE + FRO16K is disabled + 0 + + + ENABLE + FRO16K is enabled + 0x1 + + + + + + + FROLCKA + FRO16K Lock A + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + Lock + 0 + 1 + read-write + + + DISABLE + Disables lock + 0 + + + ENABLE + Enables lock. Cleared by VBAT POR. + 0x1 + + + + + + + FROCLKE + FRO16K Clock Enable + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKE + Clock Enable + 0 + 1 + read-write + + + + + LDOCTLA + LDO_RAM Control A + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + BG_EN + Bandgap Enable + 0 + 1 + read-write + + + DISABLE + Bandgap is disabled + 0 + + + ENABLE + Bandgap is enabled + 0x1 + + + + + LDO_EN + LDO Enable + 1 + 1 + read-write + + + DISABLE + Regulator is disabled + 0 + + + ENABLE + Regulator is enabled + 0x1 + + + + + REFRESH_EN + Refresh Enable + 2 + 1 + read-write + + + DISABLE + Refresh mode is disabled + 0 + + + ENABLE + Refresh mode is enabled + 0x1 + + + + + + + LDOLCKA + LDO_RAM Lock A + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + Lock + 0 + 1 + read-write + + + DISABLE + Disables lock + 0 + + + ENABLE + Enables lock. Cleared by VBAT POR. + 0x1 + + + + + + + LDORAMC + RAM Control + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO + Isolate SRAM + 0 + 1 + read-write + + + DISABLE + SRAM state follows the SoC power modes + 0 + + + ENABLE + SRAM is isolated + 0x1 + + + + + SWI + Switch SRAM + 1 + 1 + read-write + + + DISABLE + SRAM array supply follows the SoC power modes + 0 + + + ENABLE + SRAM array is powered by LDO_RAM + 0x1 + + + + + RET + Retention + 8 + 1 + read-write + + + DISABLE + SRAM array is retained in low power modes + 0 + + + ENABLE + SRAM array is not retained in low power modes + 0x1 + + + + + + + LDOTIMER0 + Bandgap Timer 0 + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMCFG + Timeout Configuration + 0 + 3 + read-write + + + CFG1000 + Timeout every 1 sec + 0 + + + CFG500 + Timeout every 500 ms + 0x1 + + + CFG250 + Timeout every 250 ms + 0x2 + + + CFG125 + Timeout every 125 ms + 0x3 + + + CFG62 + Timeout every 62.5 ms + 0x4 + + + CFG31 + Timeout every 31.25 ms + 0x5 + + + CFG15 + Timeout every 15.625 ms + 0x6 + + + CFG7 + Timeout every 7.8125 ms + 0x7 + + + + + TIMEN + Timeout Enable + 31 + 1 + read-write + + + DISABLE + Timer is disabled + 0 + + + ENABLE + Timer is enabled + 0x1 + + + + + + + LDOTIMER1 + Bandgap Timer 1 + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMCFG + Timeout Configuration + 0 + 24 + read-write + + + TIMEN + Timeout Enable + 31 + 1 + read-write + + + DISABLE + Timer is disabled + 0 + + + ENABLE + Timer is enabled + 0x1 + + + + + + + + + RTC + RTC + RTC + 0x4002C000 + + 0 + 0x808 + registers + + + RTC_Alarm + 32 + + + RTC_Seconds + 33 + + + + TSR + RTC Time Seconds Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSR + Time Seconds Register + 0 + 32 + read-write + + + + + TPR + RTC Time Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPR + Time Prescaler Register + 0 + 16 + read-write + + + + + TAR + RTC Time Alarm Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TAR + Time Alarm Register + 0 + 32 + read-write + + + + + TCR + RTC Time Compensation Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TCR + Time Compensation Register + 0 + 8 + read-write + + + TCR_0 + Time Prescaler Register overflows every 32768 clock cycles. + 0 + + + TCR_1 + Time Prescaler Register overflows every 32767 clock cycles. + 0x1 + + + TCR_126 + Time Prescaler Register overflows every 32642 clock cycles. + 0x7E + + + TCR_127 + Time Prescaler Register overflows every 32641 clock cycles. + 0x7F + + + TCR_128 + Time Prescaler Register overflows every 32896 clock cycles. + 0x80 + + + TCR_129 + Time Prescaler Register overflows every 32895 clock cycles. + 0x81 + + + TCR_255 + Time Prescaler Register overflows every 32769 clock cycles. + 0xFF + + + + + CIR + Compensation Interval Register + 8 + 8 + read-write + + + TCV + Time Compensation Value + 16 + 8 + read-only + + + CIC + Compensation Interval Counter + 24 + 8 + read-only + + + + + CR + RTC Control Register + 0x10 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + SWR + Software Reset + 0 + 1 + read-write + + + SWR_0 + No effect. + 0 + + + SWR_1 + Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it. + 0x1 + + + + + WPE + Wakeup Pin Enable + 1 + 1 + read-write + + + WPE_0 + RTC_WAKEUP pin is disabled. + 0 + + + WPE_1 + RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on. + 0x1 + + + + + UM + Update Mode + 3 + 1 + read-write + + + UM_0 + Registers cannot be written when locked. + 0 + + + UM_1 + Registers can be written when locked under limited conditions. + 0x1 + + + + + CPS + Clock Pin Select + 5 + 1 + read-write + + + CPS_0 + The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. + 0 + + + CPS_1 + The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals. + 0x1 + + + + + CLKO + Clock Output + 9 + 1 + read-write + + + CLKO_0 + The 32 kHz clock is output to other peripherals. + 0 + + + CLKO_1 + The 32 kHz clock is not output to other peripherals. + 0x1 + + + + + CPE + Clock Pin Enable + 24 + 2 + read-write + + + CPE_0 + The RTC_CLKOUT function is disabled. + 0 + + + CPE_1 + Enable RTC_CLKOUT function on RTC_TAMPER[1]. + 0x1 + + + CPE_2 + Enable RTC_CLKOUT function on RTC_TAMPER[2]. + 0x2 + + + CPE_3 + Enable RTC_CLKOUT function on RTC_TAMPER[3]. + 0x3 + + + + + + + SR + RTC Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TIF + Time Invalid Flag + 0 + 1 + read-only + + + TIF_0 + Time is valid. + 0 + + + TIF_1 + Time is invalid and time counter is read as zero. + 0x1 + + + + + TOF + Time Overflow Flag + 1 + 1 + read-only + + + TOF_0 + Time overflow has not occurred. + 0 + + + TOF_1 + Time overflow has occurred and time counter is read as zero. + 0x1 + + + + + TAF + Time Alarm Flag + 2 + 1 + read-only + + + TAF_0 + Time alarm has not occurred. + 0 + + + TAF_1 + Time alarm has occurred. + 0x1 + + + + + MOF + Monotonic Overflow Flag + 3 + 1 + read-only + + + MOF_0 + Monotonic counter overflow has not occurred. + 0 + + + MOF_1 + Monotonic counter overflow has occurred and monotonic counter is read as zero. + 0x1 + + + + + TCE + Time Counter Enable + 4 + 1 + read-write + + + TCE_0 + Time counter is disabled. + 0 + + + TCE_1 + Time counter is enabled. + 0x1 + + + + + TIDF + Tamper Interrupt Detect Flag + 7 + 1 + read-only + + + TIDF_0 + Tamper interrupt has not asserted. + 0 + + + TIDF_1 + Tamper interrupt has asserted. + 0x1 + + + + + + + LR + RTC Lock Register + 0x18 + 32 + read-write + 0xFFFFF + 0xFFFFFFFF + + + TCL + Time Compensation Lock + 3 + 1 + read-write + + + TCL_0 + Time Compensation Register is locked and writes are ignored. + 0 + + + TCL_1 + Time Compensation Register is not locked and writes complete as normal. + 0x1 + + + + + CRL + Control Register Lock + 4 + 1 + read-write + + + CRL_0 + Control Register is locked and writes are ignored. + 0 + + + CRL_1 + Control Register is not locked and writes complete as normal. + 0x1 + + + + + SRL + Status Register Lock + 5 + 1 + read-write + + + SRL_0 + Status Register is locked and writes are ignored. + 0 + + + SRL_1 + Status Register is not locked and writes complete as normal. + 0x1 + + + + + LRL + Lock Register Lock + 6 + 1 + read-write + + + LRL_0 + Lock Register is locked and writes are ignored. + 0 + + + LRL_1 + Lock Register is not locked and writes complete as normal. + 0x1 + + + + + TTSL + Tamper Time Seconds Lock + 8 + 1 + read-write + + + TTSL_0 + Tamper Time Seconds Register is locked and writes are ignored. + 0 + + + TTSL_1 + Tamper Time Seconds Register is not locked and writes complete as normal. + 0x1 + + + + + MEL + Monotonic Enable Lock + 9 + 1 + read-write + + + MEL_0 + Monotonic Enable Register is locked and writes are ignored. + 0 + + + MEL_1 + Monotonic Enable Register is not locked and writes complete as normal. + 0x1 + + + + + MCLL + Monotonic Counter Low Lock + 10 + 1 + read-write + + + MCLL_0 + Monotonic Counter Low Register is locked and writes are ignored. + 0 + + + MCLL_1 + Monotonic Counter Low Register is not locked and writes complete as normal. + 0x1 + + + + + MCHL + Monotonic Counter High Lock + 11 + 1 + read-write + + + MCHL_0 + Monotonic Counter High Register is locked and writes are ignored. + 0 + + + MCHL_1 + Monotonic Counter High Register is not locked and writes complete as normal. + 0x1 + + + + + TDL + Tamper Detect Lock + 13 + 1 + read-write + + + TDL_0 + Tamper Detect Register is locked and writes are ignored. + 0 + + + TDL_1 + Tamper Detect Register is not locked and writes complete as normal. + 0x1 + + + + + TIL + Tamper Interrupt Lock + 15 + 1 + read-write + + + TIL_0 + Tamper Interrupt Register is locked and writes are ignored. + 0 + + + TIL_1 + Tamper Interrupt Register is not locked and writes complete as normal. + 0x1 + + + + + PCL + Pin Configuration Lock + 16 + 4 + read-write + + + + + IER + RTC Interrupt Enable Register + 0x1C + 32 + read-write + 0x7 + 0xFFFFFFFF + + + TIIE + Time Invalid Interrupt Enable + 0 + 1 + read-write + + + TIIE_0 + Time invalid flag does not generate an interrupt. + 0 + + + TIIE_1 + Time invalid flag does generate an interrupt. + 0x1 + + + + + TOIE + Time Overflow Interrupt Enable + 1 + 1 + read-write + + + TOIE_0 + Time overflow flag does not generate an interrupt. + 0 + + + TOIE_1 + Time overflow flag does generate an interrupt. + 0x1 + + + + + TAIE + Time Alarm Interrupt Enable + 2 + 1 + read-write + + + TAIE_0 + Time alarm flag does not generate an interrupt. + 0 + + + TAIE_1 + Time alarm flag does generate an interrupt. + 0x1 + + + + + MOIE + Monotonic Overflow Interrupt Enable + 3 + 1 + read-write + + + MOIE_0 + Monotonic overflow flag does not generate an interrupt. + 0 + + + MOIE_1 + Monotonic overflow flag does generate an interrupt. + 0x1 + + + + + TSIE + Time Seconds Interrupt Enable + 4 + 1 + read-write + + + TSIE_0 + Seconds interrupt is disabled. + 0 + + + TSIE_1 + Seconds interrupt is enabled. + 0x1 + + + + + WPON + Wakeup Pin On + 7 + 1 + read-write + + + WPON_0 + No effect. + 0 + + + WPON_1 + If the RTC_WAKEUP pin is enabled, then the pin will assert. + 0x1 + + + + + TSIC + Timer Seconds Interrupt Configuration + 16 + 3 + read-write + + + TSIC_0 + 1 Hz. + 0 + + + TSIC_1 + 2 Hz. + 0x1 + + + TSIC_2 + 4 Hz. + 0x2 + + + TSIC_3 + 8 Hz. + 0x3 + + + TSIC_4 + 16 Hz. + 0x4 + + + TSIC_5 + 32 Hz. + 0x5 + + + TSIC_6 + 64 Hz. + 0x6 + + + TSIC_7 + 128 Hz. + 0x7 + + + + + + + TTSR + RTC Tamper Time Seconds Register + 0x20 + 32 + read-only + 0 + 0 + + + TTS + Tamper Time Seconds + 0 + 32 + read-only + + + + + MER + RTC Monotonic Enable Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCE + Monotonic Counter Enable + 4 + 1 + read-write + + + MCE_0 + Writes to the monotonic counter load the counter with the value written. + 0 + + + MCE_1 + Writes to the monotonic counter increment the counter. + 0x1 + + + + + + + MCLR + RTC Monotonic Counter Low Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCL + Monotonic Counter Low + 0 + 32 + read-write + + + + + MCHR + RTC Monotonic Counter High Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + MCH + Monotonic Counter High + 0 + 32 + read-write + + + + + TDR + RTC Tamper Detect Register + 0x34 + 32 + read-write + 0x1 + 0xFFFFFFFF + oneToClear + + + LCTF + Loss of Clock Tamper Flag + 4 + 1 + read-write + oneToClear + + + LCTF_0 + Tamper not detected. + 0 + + + LCTF_1 + Loss of Clock tamper detected. + 0x1 + + + + + STF + Security Tamper Flag + 5 + 1 + read-write + oneToClear + + + STF_0 + Tamper not detected. + 0 + + + STF_1 + Security module tamper detected. + 0x1 + + + + + FSF + Flash Security Flag + 6 + 1 + read-write + oneToClear + + + FSF_0 + Tamper not detected. + 0 + + + FSF_1 + Flash security tamper detected. + 0x1 + + + + + TMF + Test Mode Flag + 7 + 1 + read-write + oneToClear + + + TMF_0 + Tamper not detected. + 0 + + + TMF_1 + Test mode tamper detected. + 0x1 + + + + + TPF + Tamper Pin Flag + 16 + 4 + read-write + oneToClear + + + + + TIR + RTC Tamper Interrupt Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + LCIE + Loss of Clock Interrupt Enable + 4 + 1 + read-write + + + LCIE_0 + Interrupt disabled. + 0 + + + LCIE_1 + An interrupt is generated when the loss of clock flag is set. + 0x1 + + + + + SIE + Security Module Interrupt Enable + 5 + 1 + read-write + + + SIE_0 + Interrupt disabled. + 0 + + + SIE_1 + An interrupt is generated when the security module flag is set. + 0x1 + + + + + FSIE + Flash Security Interrupt Enable + 6 + 1 + read-write + + + FSIE_0 + Interrupt disabled. + 0 + + + FSIE_1 + An interrupt is generated when the flash security flag is set. + 0x1 + + + + + TMIE + Test Mode Interrupt Enable + 7 + 1 + read-write + + + TMIE_0 + Interrupt disabled. + 0 + + + TMIE_1 + An interrupt is generated when the test mode flag is set. + 0x1 + + + + + TPIE + Tamper Pin Interrupt Enable + 16 + 4 + read-write + + + TPIE_0 + Interrupt disabled. + 0 + + + TPIE_1 + An interrupt is generated when the corresponding tamper pin flag is set. + 0x1 + + + + + + + 4 + 0x4 + PCR[%s] + RTC Pin Configuration Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPE + Tamper Pull Enable + 24 + 1 + read-write + + + TPE_0 + Pull resistor is disabled on tamper pin. + 0 + + + TPE_1 + Pull resistor is enabled on tamper pin. + 0x1 + + + + + TPS + Tamper Pull Select + 25 + 1 + read-write + + + TPS_0 + Tamper pin pull resistor direction will assert the tamper pin. + 0 + + + TPS_1 + Tamper pin pull resistor direction will negate the tamper pin. + 0x1 + + + + + TFE + Tamper Filter Enable + 26 + 1 + read-write + + + TFE_0 + Input filter is disabled on the tamper pin. + 0 + + + TFE_1 + Input filter is enabled on the tamper pin. + 0x1 + + + + + TPP + Tamper Pin Polarity + 27 + 1 + read-write + + + TPP_0 + Tamper pin is active high. + 0 + + + TPP_1 + Tamper pin is active low. + 0x1 + + + + + TPID + Tamper Pin Input Data + 31 + 1 + read-only + + + TPID_0 + Tamper pin input data is logic zero. + 0 + + + TPID_1 + Tamper pin input data is logic one. + 0x1 + + + + + + + WAR + RTC Write Access Register + 0x800 + 32 + read-write + 0xFFFFF + 0xFFFFFFFF + + + TSRW + Time Seconds Register Write + 0 + 1 + read-write + + + TSRW_0 + Writes to the Time Seconds Register are ignored. + 0 + + + TSRW_1 + Writes to the Time Seconds Register complete as normal. + 0x1 + + + + + TPRW + Time Prescaler Register Write + 1 + 1 + read-write + + + TPRW_0 + Writes to the Time Prescaler Register are ignored. + 0 + + + TPRW_1 + Writes to the Time Prescaler Register complete as normal. + 0x1 + + + + + TARW + Time Alarm Register Write + 2 + 1 + read-write + + + TARW_0 + Writes to the Time Alarm Register are ignored. + 0 + + + TARW_1 + Writes to the Time Alarm Register complete as normal. + 0x1 + + + + + TCRW + Time Compensation Register Write + 3 + 1 + read-write + + + TCRW_0 + Writes to the Time Compensation Register are ignored. + 0 + + + TCRW_1 + Writes to the Time Compensation Register complete as normal. + 0x1 + + + + + CRW + Control Register Write + 4 + 1 + read-write + + + CRW_0 + Writes to the Control Register are ignored. + 0 + + + CRW_1 + Writes to the Control Register complete as normal. + 0x1 + + + + + SRW + Status Register Write + 5 + 1 + read-write + + + SRW_0 + Writes to the Status Register are ignored. + 0 + + + SRW_1 + Writes to the Status Register complete as normal. + 0x1 + + + + + LRW + Lock Register Write + 6 + 1 + read-write + + + LRW_0 + Writes to the Lock Register are ignored. + 0 + + + LRW_1 + Writes to the Lock Register complete as normal. + 0x1 + + + + + IERW + Interrupt Enable Register Write + 7 + 1 + read-write + + + IERW_0 + Writes to the Interrupt Enable Register are ignored. + 0 + + + IERW_1 + Writes to the Interrupt Enable Register complete as normal. + 0x1 + + + + + TTSW + Tamper Time Seconds Write + 8 + 1 + read-write + + + TTSW_0 + Writes to the Tamper Time Seconds Register are ignored. + 0 + + + TTSW_1 + Writes to the Tamper Time Seconds Register complete as normal. + 0x1 + + + + + MERW + Monotonic Enable Register Write + 9 + 1 + read-write + + + MERW_0 + Writes to the Monotonic Enable Register are ignored. + 0 + + + MERW_1 + Writes to the Monotonic Enable Register complete as normal. + 0x1 + + + + + MCLW + Monotonic Counter Low Write + 10 + 1 + read-write + + + MCLW_0 + Writes to the Monotonic Counter Low Register are ignored. + 0 + + + MCLW_1 + Writes to the Monotonic Counter Low Register complete as normal. + 0x1 + + + + + MCHW + Monotonic Counter High Write + 11 + 1 + read-write + + + MCHW_0 + Writes to the Monotonic Counter High Register are ignored. + 0 + + + MCHW_1 + Writes to the Monotonic Counter High Register complete as normal. + 0x1 + + + + + TDRW + Tamper Detect Register Write + 13 + 1 + read-write + + + TDRW_0 + Writes to the Tamper Detect Register are ignored. + 0 + + + TDRW_1 + Writes to the Tamper Detect Register complete as normal. + 0x1 + + + + + TIRW + Tamper Interrupt Register Write + 15 + 1 + read-write + + + TIRW_0 + Writes to the Tamper Interrupt Register are ignored. + 0 + + + TIRW_1 + Writes to the Tamper Interrupt Register complete as normal. + 0x1 + + + + + PCRW + Pin Configuration Register Write + 16 + 4 + read-write + + + + + RAR + RTC Read Access Register + 0x804 + 32 + read-write + 0xFFFFF + 0xFFFFFFFF + + + TSRR + Time Seconds Register Read + 0 + 1 + read-write + + + TSRR_0 + Reads to the Time Seconds Register are ignored. + 0 + + + TSRR_1 + Reads to the Time Seconds Register complete as normal. + 0x1 + + + + + TPRR + Time Prescaler Register Read + 1 + 1 + read-write + + + TPRR_0 + Reads to the Time Pprescaler Register are ignored. + 0 + + + TPRR_1 + Reads to the Time Prescaler Register complete as normal. + 0x1 + + + + + TARR + Time Alarm Register Read + 2 + 1 + read-write + + + TARR_0 + Reads to the Time Alarm Register are ignored. + 0 + + + TARR_1 + Reads to the Time Alarm Register complete as normal. + 0x1 + + + + + TCRR + Time Compensation Register Read + 3 + 1 + read-write + + + TCRR_0 + Reads to the Time Compensation Register are ignored. + 0 + + + TCRR_1 + Reads to the Time Compensation Register complete as normal. + 0x1 + + + + + CRR + Control Register Read + 4 + 1 + read-write + + + CRR_0 + Reads to the Control Register are ignored. + 0 + + + CRR_1 + Reads to the Control Register complete as normal. + 0x1 + + + + + SRR + Status Register Read + 5 + 1 + read-write + + + SRR_0 + Reads to the Status Register are ignored. + 0 + + + SRR_1 + Reads to the Status Register complete as normal. + 0x1 + + + + + LRR + Lock Register Read + 6 + 1 + read-write + + + LRR_0 + Reads to the Lock Register are ignored. + 0 + + + LRR_1 + Reads to the Lock Register complete as normal. + 0x1 + + + + + IERR + Interrupt Enable Register Read + 7 + 1 + read-write + + + IERR_0 + Reads to the Interrupt Enable Register are ignored. + 0 + + + IERR_1 + Reads to the Interrupt Enable Register complete as normal. + 0x1 + + + + + TTSR + Tamper Time Seconds Read + 8 + 1 + read-write + + + TTSR_0 + Reads to the Tamper Time Seconds Register are ignored. + 0 + + + TTSR_1 + Reads to the Tamper Time Seconds Register complete as normal. + 0x1 + + + + + MERR + Monotonic Enable Register Read + 9 + 1 + read-write + + + MERR_0 + Reads to the Monotonic Enable Register are ignored. + 0 + + + MERR_1 + Reads to the Monotonic Enable Register complete as normal. + 0x1 + + + + + MCLR + Monotonic Counter Low Read + 10 + 1 + read-write + + + MCLR_0 + Reads to the Monotonic Counter Low Register are ignored. + 0 + + + MCLR_1 + Reads to the Monotonic Counter Low Register complete as normal. + 0x1 + + + + + MCHR + Monotonic Counter High Read + 11 + 1 + read-write + + + MCHR_0 + Reads to the Monotonic Counter High Register are ignored. + 0 + + + MCHR_1 + Reads to the Monotonic Counter High Register complete as normal. + 0x1 + + + + + TDRR + Tamper Detect Register Read + 13 + 1 + read-write + + + TDRR_0 + Reads to the Tamper Detect Register are ignored. + 0 + + + TDRR_1 + Reads to the Tamper Detect Register complete as normal. + 0x1 + + + + + TIRR + Tamper Interrupt Register Read + 15 + 1 + read-write + + + TIRR_0 + Reads to the Tamper Interrupt Register are ignored. + 0 + + + TIRR_1 + Reads to the Tamper Interrupt Register complete as normal. + 0x1 + + + + + PCRR + Pin Configuration Register Read + 16 + 4 + read-write + + + + + + + LPTMR0 + LPTMR + LPTMR + LPTMR + 0x4002D000 + + 0 + 0x10 + registers + + + LPTMR0 + 34 + + + + CSR + Control Status + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + ten0 + Disable + 0 + + + ten1 + Enable + 0x1 + + + + + TMS + Timer Mode Select + 1 + 1 + read-write + + + tms0 + Time Counter mode + 0 + + + tms1 + Pulse Counter mode + 0x1 + + + + + TFC + Timer Free-Running Counter + 2 + 1 + read-write + + + tfc0 + Reset if TCF set + 0 + + + tfc1 + Reset on overflow + 0x1 + + + + + TPP + Timer Pin Polarity + 3 + 1 + read-write + + + tpp0 + Active-high + 0 + + + tpp1 + Active-low + 0x1 + + + + + TPS + Timer Pin Select + 4 + 2 + read-write + + + tps00 + Input 0 + 0 + + + tps01 + Input 1 + 0x1 + + + tps10 + Input 2 + 0x2 + + + tps11 + Input 3 + 0x3 + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + tie0 + Disable + 0 + + + tie1 + Enable + 0x1 + + + + + TCF + Timer Compare Flag + 7 + 1 + read-write + oneToClear + + + tcf0 + CNR != (CMR + 1) + 0 + + + tcf1 + CNR = (CMR + 1) + 0x1 + + + + + TDRE + Timer DMA Request Enable + 8 + 1 + read-write + + + trde0 + Disable + 0 + + + trde1 + Enable + 0x1 + + + + + + + PSR + Prescale and Glitch Filter + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCS + Prescaler/Glitch Filter Clock Select + 0 + 2 + read-write + + + pcs00 + Clock 0 + 0 + + + pcs01 + Clock 1 + 0x1 + + + pcs10 + Clock 2 + 0x2 + + + pcs11 + Clock 3 + 0x3 + + + + + PBYP + Prescaler/Glitch Filter Bypass + 2 + 1 + read-write + + + pbyp0 + Prescaler/glitch filter enable + 0 + + + pbyp1 + Prescaler/glitch filter bypass + 0x1 + + + + + PRESCALE + Prescale/Glitch Filter Value + 3 + 4 + read-write + + + prescale0000 + Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. + 0 + + + prescale0001 + Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. + 0x1 + + + prescale0010 + Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. + 0x2 + + + prescale0011 + Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. + 0x3 + + + prescale0100 + Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. + 0x4 + + + prescale0101 + Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. + 0x5 + + + prescale0110 + Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. + 0x6 + + + prescale0111 + Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. + 0x7 + + + prescale1000 + Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. + 0x8 + + + prescale1001 + Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. + 0x9 + + + prescale1010 + Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. + 0xA + + + prescale1011 + Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. + 0xB + + + prescale1100 + Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. + 0xC + + + prescale1101 + Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. + 0xD + + + prescale1110 + Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. + 0xE + + + prescale1111 + Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. + 0xF + + + + + + + CMR + Compare + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPARE + Compare Value + 0 + 32 + read-write + + + + + CNR + Counter + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNTER + Counter Value + 0 + 32 + read-write + + + + + + + LPTMR1 + LPTMR + LPTMR + 0x4002E000 + + 0 + 0x10 + registers + + + LPTMR1 + 35 + + + + LPIT0 + LPIT + LPIT + 0x4002F000 + + 0 + 0x5C + registers + + + LPIT0 + 36 + + + + VERID + Version ID + 0 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + FEATURE + Feature Number + 0 + 16 + read-only + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x404 + 0xFFFFFFFF + + + CHANNEL + Number of Timer Channels + 0 + 8 + read-only + + + EXT_TRIG + Number of External Trigger Inputs + 8 + 8 + read-only + + + + + MCR + Module Control + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + M_CEN + Module Clock Enable + 0 + 1 + read-write + + + DISABLE + Disable peripheral clock to timers + 0 + + + ENABLE + Enable peripheral clock to timers + 0x1 + + + + + SW_RST + Software Reset + 1 + 1 + read-write + + + NOT_RESET + Timer channels and registers are not reset + 0 + + + RESET + Reset timer channels and registers + 0x1 + + + + + DOZE_EN + DOZE Mode Enable + 2 + 1 + read-write + + + DISABLE + Stop timer channels in DOZE mode + 0 + + + ENABLE + Allow timer channels to continue to run in DOZE mode + 0x1 + + + + + DBG_EN + Debug Mode Enable + 3 + 1 + read-write + + + DISABLE + Stop timer channels in Debug mode + 0 + + + ENABLE + Allow timer channels to continue to run in Debug mode + 0x1 + + + + + + + MSR + Module Status + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + TIF0 + Channel 0 Timer Interrupt Flag + 0 + 1 + read-write + oneToClear + + + NO_FLAG + Timer has not timed out + 0 + + + FLAG + Timeout has occurred (timer has timed out) + 0x1 + + + + + TIF1 + Channel 1 Timer Interrupt Flag + 1 + 1 + read-write + oneToClear + + + NO_FLAG + Timer has not timed out + 0 + + + FLAG + Timeout has occurred (timer has timed out) + 0x1 + + + + + TIF2 + Channel 2 Timer Interrupt Flag + 2 + 1 + read-write + oneToClear + + + NO_FLAG + Timer has not timed out + 0 + + + FLAG + Timeout has occurred (timer has timed out) + 0x1 + + + + + TIF3 + Channel 3 Timer Interrupt Flag + 3 + 1 + read-write + oneToClear + + + NO_FLAG + Timer has not timed out + 0 + + + FLAG + Timeout has occurred (timer has timed out) + 0x1 + + + + + + + MIER + Module Interrupt Enable + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIE0 + Channel 0 Timer Interrupt Enable + 0 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + TIE1 + Channel 1 Timer Interrupt Enable + 1 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + TIE2 + Channel 2 Timer Interrupt Enable + 2 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + TIE3 + Channel 3 Timer Interrupt Enable + 3 + 1 + read-write + + + DISABLE + Disabled + 0 + + + ENABLE + Enabled + 0x1 + + + + + + + SETTEN + Set Timer Enable + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + oneToSet + + + SET_T_EN_0 + Set Timer 0 Enable + 0 + 1 + read-write + oneToSet + + + DISABLE + No effect + 0 + + + ENABLE + Enables Timer Channel 0 + 0x1 + + + + + SET_T_EN_1 + Set Timer 1 Enable + 1 + 1 + read-write + oneToSet + + + DISABLE + No Effect + 0 + + + ENABLE + Enables Timer Channel 1 + 0x1 + + + + + SET_T_EN_2 + Set Timer 2 Enable + 2 + 1 + read-write + oneToSet + + + DISABLE + No Effect + 0 + + + ENABLE + Enables Timer Channel 2 + 0x1 + + + + + SET_T_EN_3 + Set Timer 3 Enable + 3 + 1 + read-write + oneToSet + + + DISABLE + No effect + 0 + + + ENABLE + Enables Timer Channel 3 + 0x1 + + + + + + + CLRTEN + Clear Timer Enable + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLR_T_EN_0 + Clear Timer 0 Enable + 0 + 1 + read-write + + + DISABLE + No action + 0 + + + ENABLE + Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 + 0x1 + + + + + CLR_T_EN_1 + Clear Timer 1 Enable + 1 + 1 + read-write + + + DISABLE + No Action + 0 + + + ENABLE + Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 + 0x1 + + + + + CLR_T_EN_2 + Clear Timer 2 Enable + 2 + 1 + read-write + + + DISABLE + No Action + 0 + + + ENABLE + Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 + 0x1 + + + + + CLR_T_EN_3 + Clear Timer 3 Enable + 3 + 1 + read-write + + + DISABLE + No Action + 0 + + + ENABLE + Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 + 0x1 + + + + + + + 4 + 0x10 + CHANNEL[%s] + no description available + 0x20 + + TVAL + Timer Value + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TMR_VAL + Timer Value + 0 + 32 + read-write + + + INVALID_COMPARE_MODE_VALUE_0 + Invalid load value in compare mode + 0 + + + INVALID_COMPARE_MODE_VALUE_1 + Invalid load value in compare mode + 0x1 + + + VALUE_2 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x2 + + + VALUE_3 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x3 + + + VALUE_4 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x4 + + + VALUE_5 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x5 + + + VALUE_6 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x6 + + + VALUE_7 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x7 + + + VALUE_8 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x8 + + + VALUE_9 + In compare mode: the value to be loaded; in capture mode, the value of the timer + 0x9 + + + + + + + CVAL + Current Timer Value + 0x4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + TMR_CUR_VAL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL + Timer Control + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + T_EN + Timer Enable + 0 + 1 + read-write + + + DISABLE + Timer Channel is disabled + 0 + + + ENABLE + Timer Channel is enabled + 0x1 + + + + + CHAIN + Chain Channel + 1 + 1 + read-write + + + DISABLE + Channel Chaining is disabled. The channel timer runs independently. + 0 + + + ENABLE + Channel Chaining is enabled. The timer decrements on the previous channel's timeout. + 0x1 + + + + + MODE + Timer Operation Mode + 2 + 2 + read-write + + + CTR_32BIT + 32-bit Periodic Counter + 0 + + + CTR_DUAL_16BIT + Dual 16-bit Periodic Counter + 0x1 + + + TRIG_ACCUM_32BIT + 32-bit Trigger Accumulator + 0x2 + + + TRIG_INPUT_32BIT + 32-bit Trigger Input Capture + 0x3 + + + + + TSOT + Timer Start On Trigger + 16 + 1 + read-write + + + IMMEDIATELY + Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) + 0 + + + RISING_EDGE + Timer starts to decrement when a rising edge on a selected trigger is detected + 0x1 + + + + + TSOI + Timer Stop On Interrupt + 17 + 1 + read-write + + + DISABLE + The channel timer does not stop after timeout + 0 + + + ENABLE + The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. + 0x1 + + + + + TROT + Timer Reload On Trigger + 18 + 1 + read-write + + + DISABLE + Timer will not reload on the selected trigger + 0 + + + ENABLE + Timer will reload on the selected trigger + 0x1 + + + + + TRG_SRC + Trigger Source + 23 + 1 + read-write + + + EXT_TRIG + Selects external triggers + 0 + + + INT_TRIG + Selects internal triggers + 0x1 + + + + + TRG_SEL + Trigger Select + 24 + 4 + read-write + + + TRIG_SOURCE_0 + Timer channel 0 - 3 trigger source is selected + 0 + + + TRIG_SOURCE_1 + Timer channel 0 - 3 trigger source is selected + 0x1 + + + TRIG_SOURCE_2 + Timer channel 0 - 3 trigger source is selected + 0x2 + + + TRIG_SOURCE_3 + Timer channel 0 - 3 trigger source is selected + 0x3 + + + + + + + + + + TSTMR0 + TSTMR + TSTMR0 + 0x40030000 + + 0 + 0x8 + registers + + + + LOW + Time Stamp Timer Register Low + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUE + Time Stamp Timer Low + 0 + 32 + read-only + + + + + HIGH + Time Stamp Timer Register High + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUE + Time Stamp Timer High + 0 + 24 + read-only + + + + + + + TPM0 + TPM + TPM + TPM + 0x40031000 + + 0 + 0x88 + registers + + + TPM0 + 37 + + + + VERID + Version ID + 0 + 32 + read-only + 0x6000007 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + STANDARD + Standard feature set. + 0x1 + + + FILT_COMBINE + Standard feature set with Filter and Combine registers implemented. + 0x3 + + + QUAD + Standard feature set with Quadrature registers implemented. + 0x5 + + + FILT_COMBINE_QUAD + Standard feature set with Filter, Combine and Quadrature registers implemented. + 0x7 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x200406 + 0xFFFFFFFF + + + CHAN + Channel Count + 0 + 8 + read-only + + + TRIG + Trigger Count + 8 + 8 + read-only + + + WIDTH + Counter Width + 16 + 8 + read-only + + + + + GLOBAL + TPM Global + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + NOUPDATE + No Update + 0 + 1 + read-write + + + NOUPDATE_0 + Internal double buffered registers update as normal. + 0 + + + NOUPDATE_1 + Internal double buffered registers do not update. + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + NOT_RESET + Module is not reset. + 0 + + + RESET + Module is reset. + 0x1 + + + + + + + SC + Status and Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Prescale Factor Selection + 0 + 3 + read-write + + + DIV_1 + Divide by 1 + 0 + + + DIV_2 + Divide by 2 + 0x1 + + + DIV_4 + Divide by 4 + 0x2 + + + DIV_8 + Divide by 8 + 0x3 + + + DIV_16 + Divide by 16 + 0x4 + + + DIV_32 + Divide by 32 + 0x5 + + + DIV_64 + Divide by 64 + 0x6 + + + DIV_128 + Divide by 128 + 0x7 + + + + + CMOD + Clock Mode Selection + 3 + 2 + read-write + + + DISABLE + TPM counter is disabled + 0 + + + COUNTER + TPM counter increments on every TPM counter clock + 0x1 + + + EXTCLK + TPM counter increments on rising edge of EXTCLK synchronized to the TPM counter clock + 0x2 + + + TRIG + TPM counter increments on rising edge of the selected external input trigger. + 0x3 + + + + + CPWMS + Center-Aligned PWM Select + 5 + 1 + read-write + + + UP + TPM counter operates in up counting mode. + 0 + + + UP_DOWN + TPM counter operates in up-down counting mode. + 0x1 + + + + + TOIE + Timer Overflow Interrupt Enable + 6 + 1 + read-write + + + DISABLE + Disable TOF interrupts. Use software polling or DMA request. + 0 + + + ENABLE + Enable TOF interrupts. An interrupt is generated when TOF equals one. + 0x1 + + + + + TOF + Timer Overflow Flag + 7 + 1 + read-write + oneToClear + + + NO_OVERFLOW + TPM counter has not overflowed. + 0 + + + OVERFLOW + TPM counter has overflowed. + 0x1 + + + + + DMA + DMA Enable + 8 + 1 + read-write + + + DISABLE + Disables DMA transfers. + 0 + + + ENABLE + Enables DMA transfers. + 0x1 + + + + + + + CNT + Counter + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Counter value + 0 + 32 + read-write + + + + + MOD + Modulo + 0x18 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + MOD + Modulo value + 0 + 32 + read-write + + + + + STATUS + Capture and Compare Status + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + CH0F + Channel 0 Flag + 0 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + CH1F + Channel 1 Flag + 1 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + CH2F + Channel 2 Flag + 2 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + CH3F + Channel 3 Flag + 3 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + CH4F + Channel 4 Flag + 4 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + CH5F + Channel 5 Flag + 5 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + TOF + Timer Overflow Flag + 8 + 1 + read-write + oneToClear + + + NO_OVERFLOW + TPM counter has not overflowed. + 0 + + + OVERFLOW + TPM counter has overflowed. + 0x1 + + + + + + + 6 + 0x8 + CHANNEL[%s] + no description available + 0x20 + + CSC + Channel (n) Status and Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA + DMA Enable + 0 + 1 + read-write + + + DISABLE + Disable DMA transfers. + 0 + + + ENABLE + Enable DMA transfers. + 0x1 + + + + + ELSA + Edge or Level Select + 2 + 1 + read-write + + + ELSB + Edge or Level Select + 3 + 1 + read-write + + + MSA + Channel Mode Select + 4 + 1 + read-write + + + MSB + Channel Mode Select + 5 + 1 + read-write + + + CHIE + Channel Interrupt Enable + 6 + 1 + read-write + + + DISABLE + Disable channel interrupts. + 0 + + + ENABLE + Enable channel interrupts. + 0x1 + + + + + CHF + Channel Flag + 7 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + + + CV + Channel (n) Value + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + Channel Value + 0 + 32 + read-write + + + + + + COMBINE + Combine Channel Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMBINE0 + Combine Channels 0 and 1 + 0 + 1 + read-write + + + NO_COMBINE + Channels 0 and 1 are independent. + 0 + + + COMBINE + Channels 0 and 1 are combined. + 0x1 + + + + + COMSWAP0 + Combine Channel 0 and 1 Swap + 1 + 1 + read-write + + + NO_SWAP + Even channel is used for input capture and 1st compare. + 0 + + + SWAP + Odd channel is used for input capture and 1st compare. + 0x1 + + + + + COMBINE1 + Combine Channels 2 and 3 + 8 + 1 + read-write + + + NO_COMBINE + Channels 2 and 3 are independent. + 0 + + + COMBINE + Channels 2 and 3 are combined. + 0x1 + + + + + COMSWAP1 + Combine Channels 2 and 3 Swap + 9 + 1 + read-write + + + NO_SWAP + Even channel is used for input capture and 1st compare. + 0 + + + SWAP + Odd channel is used for input capture and 1st compare. + 0x1 + + + + + COMBINE2 + Combine Channels 4 and 5 + 16 + 1 + read-write + + + NO_COMBINE + Channels 4 and 5 are independent. + 0 + + + COMBINE + Channels 4 and 5 are combined. + 0x1 + + + + + COMSWAP2 + Combine Channels 4 and 5 Swap + 17 + 1 + read-write + + + NO_SWAP + Even channel is used for input capture and 1st compare. + 0 + + + SWAP + Odd channel is used for input capture and 1st compare. + 0x1 + + + + + + + TRIG + Channel Trigger + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0 + Channel 0 Trigger + 0 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + USE_TRIG + Configures trigger input 0 to be used by channel 0. + 0x1 + + + + + TRIG1 + Channel 1 Trigger + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + USE_TRIG + Configures trigger input 1 to be used by channel 1. + 0x1 + + + + + TRIG2 + Channel 2 Trigger + 2 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + USE_TRIG + Configures trigger input 0 to be used by channel 2. + 0x1 + + + + + TRIG3 + Channel 3 Trigger + 3 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + USE_TRIG + Configures trigger input 1 to be used by channel 3. + 0x1 + + + + + TRIG4 + Channel 4 Trigger + 4 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + USE_TRIG + Configures trigger input 0 to be used by channel 4. + 0x1 + + + + + TRIG5 + Channel 5 Trigger + 5 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + USE_TRIG + Configures trigger input 1 to be used by channel 5. + 0x1 + + + + + + + POL + Channel Polarity + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + POL0 + Channel 0 Polarity + 0 + 1 + read-write + + + HIGH + The channel polarity is active high. + 0 + + + LOW + The channel polarity is active low. + 0x1 + + + + + POL1 + Channel 1 Polarity + 1 + 1 + read-write + + + HIGH + The channel polarity is active high. + 0 + + + LOW + The channel polarity is active low. + 0x1 + + + + + POL2 + Channel 2 Polarity + 2 + 1 + read-write + + + HIGH + The channel polarity is active high. + 0 + + + LOW + The channel polarity is active low. + 0x1 + + + + + POL3 + Channel 3 Polarity + 3 + 1 + read-write + + + HIGH + The channel polarity is active high. + 0 + + + LOW + The channel polarity is active low. + 0x1 + + + + + POL4 + Channel 4 Polarity + 4 + 1 + read-write + + + HIGH + The channel polarity is active high + 0 + + + LOW + The channel polarity is active low. + 0x1 + + + + + POL5 + Channel 5 Polarity + 5 + 1 + read-write + + + HIGH + The channel polarity is active high. + 0 + + + LOW + The channel polarity is active low. + 0x1 + + + + + + + FILTER + Filter Control + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0FVAL + Channel 0 Filter Value + 0 + 4 + read-write + + + CH1FVAL + Channel 1 Filter Value + 4 + 4 + read-write + + + CH2FVAL + Channel 2 Filter Value + 8 + 4 + read-write + + + CH3FVAL + Channel 3 Filter Value + 12 + 4 + read-write + + + CH4FVAL + Channel 4 Filter Value + 16 + 4 + read-write + + + CH5FVAL + Channel 5 Filter Value + 20 + 4 + read-write + + + + + QDCTRL + Quadrature Decoder Control and Status + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + QUADEN + QUADEN + 0 + 1 + read-write + + + DISABLE + Quadrature decoder mode is disabled. + 0 + + + ENABLE + Quadrature decoder mode is enabled. + 0x1 + + + + + TOFDIR + TOFDIR + 1 + 1 + read-only + + + BOTTOM + TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). + 0 + + + TOP + TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). + 0x1 + + + + + QUADIR + Counter Direction in Quadrature Decode Mode + 2 + 1 + read-only + + + DOWN + Counter direction is decreasing (counter decrement). + 0 + + + UP + Counter direction is increasing (counter increment). + 0x1 + + + + + QUADMODE + Quadrature Decoder Mode + 3 + 1 + read-write + + + PHASE + Phase encoding mode. + 0 + + + COUNT_DIR + Count and direction encoding mode. + 0x1 + + + + + + + CONF + Configuration + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOZEEN + Doze Enable + 5 + 1 + read-write + + + COUNT + Internal TPM counter continues. + 0 + + + NO_COUNT + Internal TPM counter is paused and does not increment. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. + 0x1 + + + + + DBGMODE + Debug Mode + 6 + 2 + read-write + + + NO_COUNT + TPM counter is paused and does not increment. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. + 0 + + + COUNT + TPM counter continues. + 0x3 + + + + + GTBSYNC + Global Time Base Synchronization + 8 + 1 + read-write + + + DISABLE + Global timebase synchronization disabled. + 0 + + + ENABLE + Global timebase synchronization enabled. + 0x1 + + + + + GTBEEN + Global time base enable + 9 + 1 + read-write + + + DISABLE + All channels use the internally generated TPM counter as their timebase + 0 + + + ENABLE + All channels use an externally generated global timebase as their timebase + 0x1 + + + + + CSOT + Counter Start on Trigger + 16 + 1 + read-write + + + NO + TPM counter starts to increment immediately, once it is enabled. + 0 + + + YES + TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. + 0x1 + + + + + CSOO + Counter Stop On Overflow + 17 + 1 + read-write + + + NO + TPM counter continues incrementing or decrementing after overflow + 0 + + + YES + TPM counter stops incrementing or decrementing after overflow. + 0x1 + + + + + CROT + Counter Reload On Trigger + 18 + 1 + read-write + + + NO + Counter is not reloaded due to a rising edge on the selected input trigger + 0 + + + YES + Counter is reloaded when a rising edge is detected on the selected input trigger + 0x1 + + + + + CPOT + Counter Pause On Trigger + 19 + 1 + read-write + + + NO + TPM counter continues + 0 + + + YES + TPM counter pauses + 0x1 + + + + + TRGPOL + Trigger Polarity + 22 + 1 + read-write + + + HIGH + Trigger is active high. + 0 + + + LOW + Trigger is active low. + 0x1 + + + + + TRGSRC + Trigger Source + 23 + 1 + read-write + + + EXTERNAL + Trigger source selected by TRGSEL is external. + 0 + + + INTERNAL + Trigger source selected by TRGSEL is internal (channel pin input capture). + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 2 + read-write + + + CH_0 + Channel 0 pin input capture + 0x1 + + + CH_1 + Channel 1 pin input capture + 0x2 + + + CH_0_1 + Channel 0 or Channel 1 pin input capture + 0x3 + + + + + + + + + TPM1 + TPM + TPM + 0x40032000 + + 0 + 0x88 + registers + + + TPM1 + 38 + + + + LPI2C0 + LPI2C + LPI2C + LPI2C + 0x40033000 + + 0 + 0x17C + registers + + + LPI2C0 + 39 + + + + VERID + Version ID + 0 + 32 + read-only + 0x1030003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + MASTER_ONLY + Controller only, with standard feature set + 0x2 + + + MASTER_AND_SLAVE + Controller and target, with standard feature set + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + MTXFIFO + Controller Transmit FIFO Size + 0 + 4 + read-only + + + MRXFIFO + Controller Receive FIFO Size + 8 + 4 + read-only + + + + + MCR + Controller Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Controller Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + NOT_RESET + Not reset + 0 + + + RESET + Reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + ENABLED + Controller is enabled in doze mode + 0 + + + DISABLED + Controller is disabled in doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DISABLED + Controller is disabled in debug mode + 0 + + + ENABLED + Controller is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + NO_EFFECT + No effect + 0 + + + RESET + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + NO_EFFECT + No effect + 0 + + + RESET + Receive FIFO is reset + 0x1 + + + + + + + MSR + Controller Status + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + DISABLED + Transmit data is not requested + 0 + + + ENABLED + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + DISABLED + Receive data is not ready + 0 + + + ENABLED + Receive data is ready + 0x1 + + + + + EPF + End Packet Flag + 8 + 1 + read-write + oneToClear + + + NO_FLAG + Controller has not generated a STOP or Repeated START condition + 0 + + + FLAG + Controller has generated a STOP or Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + NO_FLAG + Controller has not generated a STOP condition + 0 + + + FLAG + Controller has generated a STOP condition + 0x1 + + + + + NDF + NACK Detect Flag + 10 + 1 + read-write + oneToClear + + + NO_FLAG + Unexpected NACK was not detected + 0 + + + FLAG + Unexpected NACK was detected + 0x1 + + + + + ALF + Arbitration Lost Flag + 11 + 1 + read-write + oneToClear + + + NO_FLAG + Controller has not lost arbitration + 0 + + + FLAG + Controller has lost arbitration + 0x1 + + + + + FEF + FIFO Error Flag + 12 + 1 + read-write + oneToClear + + + NO_FLAG + No error + 0 + + + FLAG + Controller sending or receiving data without a START condition + 0x1 + + + + + PLTF + Pin Low Timeout Flag + 13 + 1 + read-write + oneToClear + + + NO_FLAG + Pin low timeout has not occurred or is disabled + 0 + + + FLAG + Pin low timeout has occurred + 0x1 + + + + + DMF + Data Match Flag + 14 + 1 + read-write + oneToClear + + + NO_FLAG + Have not received matching data + 0 + + + FLAG + Have received matching data + 0x1 + + + + + STF + START Flag + 15 + 1 + read-write + oneToClear + + + NO_FLAG + START condition not detected. + 0 + + + FLAG + START condition detected. + 0x1 + + + + + MBF + Controller Busy Flag + 24 + 1 + read-only + + + IDLE + Idle + 0 + + + BUSY + Busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + IDLE + Idle + 0 + + + BUSY + Busy + 0x1 + + + + + + + MIER + Controller Interrupt Enable + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + EPIE + End Packet Interrupt Enable + 8 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + NDIE + NACK Detect Interrupt Enable + 10 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + ALIE + Arbitration Lost Interrupt Enable + 11 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 12 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + PLTIE + Pin Low Timeout Interrupt Enable + 13 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 14 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STIE + START Interrupt Enable + 15 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + + + MDER + Controller DMA Enable + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + + + MCFGR0 + Controller Configuration 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host request enable + 0 + 1 + read-write + + + DISABLED + Host request input is disabled + 0 + + + ENABLED + Host request input is enabled + 0x1 + + + + + HRPOL + Host request polarity + 1 + 1 + read-write + + + ACTIVE_LOW + Active low + 0 + + + ACTIVE_HIGH + Active high + 0x1 + + + + + HRSEL + Host request select + 2 + 1 + read-write + + + ENABLED + Host request input is input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO enable + 8 + 1 + read-write + + + DISABLED + Circular FIFO is disabled + 0 + + + ENABLED + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive data match only + 9 + 1 + read-write + + + DISABLED + Received data is stored in the receive FIFO + 0 + + + ENABLED + Received data is discarded unless the Data Match Flag (MSR[DMF]) is 1. + 0x1 + + + + + RELAX + Relaxed Mode + 16 + 1 + read-write + + + NORMAL_TRANSFER + Normal transfer + 0 + + + RELAXED_TRANSFER + Relaxed transfer + 0x1 + + + + + ABORT + Abort Transfer + 17 + 1 + read-write + + + DISABLED + Normal transfer + 0 + + + ENABLED + Abort existing transfer and do not start new transfer + 0x1 + + + + + + + MCFGR1 + Controller Configuration 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALE + Prescaler + 0 + 3 + read-write + + + DIVIDE_BY_1 + Divide by 1 + 0 + + + DIVIDE_BY_2 + Divide by 2 + 0x1 + + + DIVIDE_BY_4 + Divide by 4 + 0x2 + + + DIVIDE_BY_8 + Divide by 8 + 0x3 + + + DIVIDE_BY_16 + Divide by 16 + 0x4 + + + DIVIDE_BY_32 + Divide by 32 + 0x5 + + + DIVIDE_BY_64 + Divide by 64 + 0x6 + + + DIVIDE_BY_128 + Divide by 128 + 0x7 + + + + + AUTOSTOP + Automatic STOP Generation + 8 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + STOP condition is automatically generated when the transmit FIFO is empty and the LPI2C controller is busy + 0x1 + + + + + IGNACK + Ignore NACK + 9 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + LPI2C controller treats a received NACK as if it (NACK) was an ACK and the NACK Detect Flag is never written 1. + 0x1 + + + + + TIMECFG + Timeout Configuration + 10 + 1 + read-write + + + IF_SCL_LOW + MSR[PLTF] becomes 1 if SCL is low for longer than the configured timeout. + 0 + + + IF_SCL_OR_SDA_LOW + MSR[PLTF] becomes 1 if either SCL or SDA is low for longer than the configured timeout. + 0x1 + + + + + STOPCFG + STOP Configuration + 11 + 1 + read-write + + + ANY_STOP + MSR[SDF] asserts on any STOP condition generated by LPI2C controller. + 0 + + + LAST_STOP + MSR[SDF] asserts on last STOP condition before LPI2C controller is idle (that is, the transmit FIFO is empty at the time of the STOP condition). + 0x1 + + + + + STARTCFG + START Configuration + 12 + 1 + read-write + + + BOTH_I2C_AND_LPI2C_IDLE + MSR[STF] asserts on START condition provided both I2C bus and LPI2C controller are idle (that is, any non-repeated START condition initiated by any other controller on the bus but not the LPI2C controller). + 0 + + + I2C_IDLE + MSR[STF] asserts on START condition provided I2C bus is idle (that is, any non-repeated START condition initiated by any controller on the bus including the LPI2C controller). + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + DISABLED + Match is disabled + 0 + + + FIRST_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 + Match is enabled (first data word equals MDMR[MATCH0] OR MDMR[MATCH1]) + 0x2 + + + ANY_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 + Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) + 0x3 + + + FIRST_DATA_WORD_MATCH0_AND_SECOND_DATA_WORD_MATCH1 + Match is enabled (first data word equals MDMR[MATCH0] AND second data word equals MDMR[MATCH1) + 0x4 + + + ANY_DATA_WORD_MATCH0_NEXT_DATA_WORD_MATCH1 + Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) + 0x5 + + + FIRST_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 + Match is enabled (first data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) + 0x6 + + + ANY_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 + Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 3 + read-write + + + OPEN_DRAIN_2_PIN + Two-pin open drain mode + 0 + + + OUTPUT_2_PIN_ONLY + Two-pin output only mode (ultra-fast mode) + 0x1 + + + PUSH_PULL_2_PIN + Two-pin push-pull mode + 0x2 + + + PUSH_PULL_4_PIN + Four-pin push-pull mode + 0x3 + + + OPEN_DRAIN_2_PIN_W_LPI2C_SLAVE + Two-pin open drain mode with separate LPI2C target + 0x4 + + + OUTPUT_2_PIN_ONLY_W_LPI2C_SLAVE + Two-pin output only mode (ultra-fast mode) with separate LPI2C target + 0x5 + + + PUSH_PULL_2_PIN_W_LPI2C_SLAVE + Two-pin push-pull mode with separate LPI2C target + 0x6 + + + PUSH_PULL_4_PIN_W_LPI2C_SLAVE + Four-pin push-pull mode (inverted outputs) + 0x7 + + + + + FRCHS + Force HS mode + 27 + 1 + read-write + + + DISABLED + No effect + 0 + + + ENABLED + LPI2C pin state forced into HS mode. + 0x1 + + + + + + + MCFGR2 + Controller Configuration 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUSIDLE + Bus Idle Timeout + 0 + 12 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + MCFGR3 + Controller Configuration 3 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PINLOW + Pin low timeout + 8 + 12 + read-write + + + + + MDMR + Controller Data Match + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 8 + read-write + + + MATCH1 + Match 1 Value + 16 + 8 + read-write + + + + + MCCR0 + Controller Clock Configuration 0 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MCCR1 + Controller Clock Configuration 1 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MFCR + Controller FIFO Control + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 2 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 2 + read-write + + + + + MFSR + Controller FIFO Status + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 3 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 3 + read-only + + + + + MTDR + Controller Transmit Data + 0x60 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + CMD + Command Data + 8 + 3 + write-only + + + TRANSMIT_DATA_7_THROUGH_0 + Transmit DATA[7:0] + 0 + + + RECEIVE_DATA_7_THROUGH_0_PLUS_ONE + Receive (DATA[7:0] + 1) bytes + 0x1 + + + GENERATE_STOP_CONDITION + Generate STOP condition + 0x2 + + + RECEIVE_AND_DISCARD_DATA_7_THROUGH_0_PLUS_ONE + Receive and discard (DATA[7:0] + 1) bytes + 0x3 + + + GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0 + Generate (repeated) START and transmit address in DATA[7:0] + 0x4 + + + GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_EXPECT_NACK + Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + 0x5 + + + GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_USING_HIGH_SPEED_MODE + Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode + 0x6 + + + GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_USING_HIGH_SPEED_MODE_EXPECT_NACK + Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode. This transfer expects a NACK to be returned. + 0x7 + + + + + + + MRDR + Controller Receive Data + 0x70 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + Receive Empty + 14 + 1 + read-only + + + NOT_EMPTY + Receive FIFO is not empty + 0 + + + EMPTY + Receive FIFO is empty + 0x1 + + + + + + + MRDROR + Controller Receive Data Read Only + 0x78 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + NOT_EMPTY + Receive FIFO is not empty + 0 + + + EMPTY + Receive FIFO is empty + 0x1 + + + + + + + SCR + Target Control + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEN + Target Enable + 0 + 1 + read-write + + + DISABLED + I2C Target mode is disabled + 0 + + + ENABLED + I2C Target mode is enabled + 0x1 + + + + + RST + Software reset + 1 + 1 + read-write + + + NOT_RESET + Target mode logic is not reset + 0 + + + RESET + Target mode logic is reset + 0x1 + + + + + FILTEN + Filter enable + 4 + 1 + read-write + + + DISABLE + Disable digital filter and output delay counter for target mode + 0 + + + ENABLE + Enable digital filter and output delay counter for target mode + 0x1 + + + + + FILTDZ + Filter doze enable + 5 + 1 + read-write + + + FILTER_ENABLED + Filter remains enabled in Doze mode + 0 + + + FILTER_DISABLED + Filter is disabled in Doze mode + 0x1 + + + + + RTF + Reset transmit FIFO + 8 + 1 + read-write + + + NO_EFFECT + No effect + 0 + + + NOW_EMPTY + Transmit Data Register is now empty. + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + NO_EFFECT + No effect + 0 + + + NOW_EMPTY + Receive Data Register is now empty. + 0x1 + + + + + + + SSR + Target Status + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDF + Transmit data flag + 0 + 1 + read-only + + + NO_FLAG + Transmit data not requested + 0 + + + FLAG + Transmit data is requested + 0x1 + + + + + RDF + Receive data flag + 1 + 1 + read-only + + + NOT_READY + Receive data is not ready + 0 + + + READY + Receive data is ready + 0x1 + + + + + AVF + Address valid flag + 2 + 1 + read-only + + + NOT_VALID + Address Status Register is not valid + 0 + + + VALID + Address Status Register is valid + 0x1 + + + + + TAF + Transmit ACK flag + 3 + 1 + read-only + + + NOT_REQUIRED + Transmit ACK/NACK is not required + 0 + + + REQUIRED + Transmit ACK/NACK is required + 0x1 + + + + + RSF + Repeated start flag + 8 + 1 + read-write + oneToClear + + + NO_FLAG + Target has not detected a Repeated START condition + 0 + + + FLAG + Target has detected a Repeated START condition + 0x1 + + + + + SDF + STOP detect flag + 9 + 1 + read-write + oneToClear + + + NO_FLAG + Target has not detected a STOP condition + 0 + + + FLAG + Target has detected a STOP condition + 0x1 + + + + + BEF + Bit error flag + 10 + 1 + read-write + oneToClear + + + NO_FLAG + Target has not detected a bit error + 0 + + + FLAG + Target has detected a bit error + 0x1 + + + + + FEF + FIFO error flag + 11 + 1 + read-write + oneToClear + + + NO_FLAG + FIFO underflow or overflow was not detected + 0 + + + FLAG + FIFO underflow or overflow was detected + 0x1 + + + + + AM0F + Address match 0 flag + 12 + 1 + read-only + + + NO_FLAG + ADDR0 matching address not received + 0 + + + FLAG + ADDR0 matching address received + 0x1 + + + + + AM1F + Address match 1 flag + 13 + 1 + read-only + + + NO_FLAG + ADDR1 or ADDR0/ADDR1 range matching address not received + 0 + + + FLAG + ADDR1 or ADDR0/ADDR1 range matching address received + 0x1 + + + + + GCF + General call flag + 14 + 1 + read-only + + + NO_FLAG + Target has not detected the General Call Address or the General Call Address is disabled + 0 + + + FLAG + Target has detected the General Call Address + 0x1 + + + + + SARF + SMBus alert response flag + 15 + 1 + read-only + + + NO_FLAG + SMBus alert response is disabled or not detected + 0 + + + FLAG + SMBus alert response is enabled and detected + 0x1 + + + + + SBF + Target busy flag + 24 + 1 + read-only + + + IDLE + Idle + 0 + + + BUSY + Busy + 0x1 + + + + + BBF + Bus busy flag + 25 + 1 + read-only + + + IDLE + Idle + 0 + + + BUSY + Busy + 0x1 + + + + + + + SIER + Target interrupt enable + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit data interrupt enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RDIE + Receive data interrupt enable + 1 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + AVIE + Address valid interrupt enable + 2 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + TAIE + Transmit ACK interrupt enable + 3 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RSIE + Repeated start interrupt enable + 8 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + SDIE + STOP detect interrupt enable + 9 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + BEIE + Bit error interrupt enable + 10 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FEIE + FIFO error interrupt enable + 11 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + AM0IE + Address match 0 interrupt enable + 12 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + AM1IE + Address match 1 interrupt enable + 13 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + GCIE + General call interrupt enable + 14 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + SARIE + SMBus alert response interrupt enable + 15 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + + + SDER + Target DMA Enable + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit data DMA enable + 0 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + RDDE + Receive data DMA enable + 1 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + AVDE + Address valid DMA enable + 2 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + RSDE + Repeated start DMA enable + 8 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + SDDE + Stop detect DMA enable + 9 + 1 + read-write + + + DISABLED + DMA request is disabled + 0 + + + ENABLED + DMA request is enabled + 0x1 + + + + + + + SCFGR0 + Target Configuration 0 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDREQ + Read Request + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RDACK + Read Acknowledge + 1 + 1 + read-only + + + NOT_ACKNOWLEDGED + Read Request not acknowledged + 0 + + + ACKNOWLEDGED + Read Request acknowledged + 0x1 + + + + + + + SCFGR1 + Target Configuration 1 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADRSTALL + Address SCL stall + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RXSTALL + RX SCL stall + 1 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + TXDSTALL + Transmit data SCL stall + 2 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + ACKSTALL + ACK SCL stall + 3 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RXNACK + Receive NACK + 4 + 1 + read-write + + + SET_BY_TXNACK + ACK/NACK always written 1 by TXNACK + 0 + + + ALWAYS_GENERATED_ON_ADDRESS_OR_RECEIVE_DATA_OVERRUN + NACK always generated on address overrun or receive data overrun, otherwise ACK/NACK is written 1 by TXNACK. + 0x1 + + + + + GCEN + General call enable + 8 + 1 + read-write + + + DISABLED + General Call address is disabled + 0 + + + ENABLED + General Call address is enabled + 0x1 + + + + + SAEN + SMBus alert enable + 9 + 1 + read-write + + + DISABLE + Disables match on SMBus Alert + 0 + + + ENABLE + Enables match on SMBus Alert + 0x1 + + + + + TXCFG + Transmit flag configuration + 10 + 1 + read-write + + + ASSERTS_DURING_SLAVE_TRANSMIT_TRANSFER_WHEN_TX_DATA_EMPTY + MSR[TDF] becomes 1 only during a target-transmit transfer when the Transmit Data register is empty + 0 + + + ASSERTS_WHEN_TX_DATA_EMPTY + MSR[TDF] becomes 1 whenever the Transmit Data register is empty + 0x1 + + + + + RXCFG + Receive Data Configuration + 11 + 1 + read-write + + + RETURNS_RECEIVED_DATA_AND_CLEARS_RX_DATA_FLAG + Reading the Receive Data register returns received data and writes 0 to the Receive Data flag. + 0 + + + WHEN_ADDRESS_VALID_FLAG_SET_RETURNS_ADDRESS_STATUS_AND_CLEARS_ADDRESS_VALID_FLAG + Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is 1, returns the Address Status register and writes 0 to SSR[AVF]. Reading the Receive Data register when SSR[AVF] is 0, returns received data and writes 0 to the Receive Data flag (MSR[RDF]). + 0x1 + + + + + IGNACK + Ignore NACK + 12 + 1 + read-write + + + ENDS_TRANSFER_ON_NACK + Target ends transfer when NACK is detected + 0 + + + DOES_NOT_END_TRANSFER_ON_NACK + Target does not end transfer when NACK detected + 0x1 + + + + + HSMEN + High-speed mode enable + 13 + 1 + read-write + + + DISABLED + Disable + 0 + + + ENABLED + Enable + 0x1 + + + + + ADDRCFG + Address configuration + 16 + 3 + read-write + + + ADDRESS_MATCH0_7_BIT + Address match 0 (7-bit) + 0 + + + ADDRESS_MATCH0_10_BIT + Address match 0 (10-bit) + 0x1 + + + ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_7_BIT + Address match 0 (7-bit) or Address match 1 (7-bit) + 0x2 + + + ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_10_BIT + Address match 0 (10-bit) or Address match 1 (10-bit) + 0x3 + + + ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_10_BIT + Address match 0 (7-bit) or Address match 1 (10-bit) + 0x4 + + + ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_7_BIT + Address match 0 (10-bit) or Address match 1 (7-bit) + 0x5 + + + FROM_ADDRESS_MATCH0_7_BIT_TO_ADDRESS_MATCH1_7_BIT + From Address match 0 (7-bit) to Address match 1 (7-bit) + 0x6 + + + FROM_ADDRESS_MATCH0_10_BIT_TO_ADDRESS_MATCH1_10_BIT + From Address match 0 (10-bit) to Address match 1 (10-bit) + 0x7 + + + + + RXALL + Receive all + 24 + 1 + read-write + + + DISABLED + Receive all disabled + 0 + + + ENABLED + Receive all enabled + 0x1 + + + + + RSCFG + Repeated start configuration + 25 + 1 + read-write + + + ANY_REPEATED_START_AFTER_ADDRESS_MATCH + Any repeated START condition following an address match + 0 + + + ANY_REPEATED_START + Any repeated START condition + 0x1 + + + + + SDCFG + Stop Detect Configuration + 26 + 1 + read-write + + + ANY_STOP_AFTER_ADDRESS_MATCH + Any STOP condition following an address match + 0 + + + ANY_STOP + Any STOP condition + 0x1 + + + + + + + SCFGR2 + Target Configuration 2 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKHOLD + Clock hold time + 0 + 4 + read-write + + + DATAVD + Data valid delay + 8 + 6 + read-write + + + FILTSCL + Glitch filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch filter SDA + 24 + 4 + read-write + + + + + SAMR + Target Address Match + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0 + Address 0 value + 1 + 10 + read-write + + + ADDR1 + Address 1 value + 17 + 10 + read-write + + + + + SASR + Target Address Status + 0x150 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + RADDR + Received Address + 0 + 11 + read-only + + + ANV + Address not valid + 14 + 1 + read-only + + + VALID + Received Address (RADDR) is valid + 0 + + + NOT_VALID + Received Address (RADDR) is not valid + 0x1 + + + + + + + STAR + Target Transmit ACK + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXNACK + Transmit NACK + 0 + 1 + read-write + + + TRANSMIT_ACK + Write a Transmit ACK for each received word + 0 + + + TRANSMIT_NACK + Write a Transmit NACK for each received word + 0x1 + + + + + + + STDR + Target Transmit Data + 0x160 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit data + 0 + 8 + write-only + + + + + SRDR + Target Receive Data + 0x170 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive data + 0 + 8 + read-only + + + RADDR + Received address + 8 + 3 + read-only + + + RXEMPTY + Receive empty + 14 + 1 + read-only + + + NOT_EMPTY + The Receive Data Register is not empty + 0 + + + EMPTY + The Receive Data Register is empty + 0x1 + + + + + SOF + Start of frame + 15 + 1 + read-only + + + NOT_FIRST_DATA_WORD + Not the first data word since a (repeated) START or STOP condition + 0 + + + FIRST_DATA_WORD + Is the first data word since a (repeated) START or STOP condition + 0x1 + + + + + + + SRDROR + Target Receive Data Read Only + 0x178 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive data + 0 + 8 + read-only + + + RADDR + Received address + 8 + 3 + read-only + + + RXEMPTY + Receive empty + 14 + 1 + read-only + + + NOT_EMPTY + The Receive Data Register is not empty + 0 + + + EMPTY + The Receive Data Register is empty + 0x1 + + + + + SOF + Start of frame + 15 + 1 + read-only + + + NOT_FIRST_DATA_WORD + Is not the first data word since a (repeated) START or STOP condition + 0 + + + FIRST_DATA_WORD + Is the first data word since a (repeated) START or STOP condition + 0x1 + + + + + + + + + LPI2C1 + LPI2C + LPI2C + 0x40034000 + + 0 + 0x17C + registers + + + LPI2C1 + 40 + + + + I3C + I3C + I3C + 0x40035000 + + 0 + 0x1000 + registers + + + I3C0 + 41 + + + + MCONFIG + Master Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFB + + + MSTENA + Master enable + 0 + 2 + read-write + + + MASTER_OFF + MASTER_OFF + 0 + + + MASTER_ON + MASTER_ON + 0x1 + + + MASTER_CAPABLE + MASTER_CAPABLE + 0x2 + + + + + DISTO + Disable Timeout + 3 + 1 + read-write + + + HKEEP + High-Keeper + 4 + 2 + read-write + + + NONE + NONE + 0 + + + WIRED_IN + WIRED_IN + 0x1 + + + PASSIVE_SDA + PASSIVE_SDA + 0x2 + + + PASSIVE_ON_SDA_SCL + PASSIVE_ON_SDA_SCL + 0x3 + + + + + ODSTOP + Open drain stop + 6 + 1 + read-write + + + PPBAUD + Push-pull baud rate + 8 + 4 + read-write + + + PPLOW + Push-Pull low + 12 + 4 + read-write + + + ODBAUD + Open drain baud rate + 16 + 8 + read-write + + + ODHPP + Open drain high push-pull + 24 + 1 + read-write + + + SKEW + Skew + 25 + 3 + read-write + + + I2CBAUD + I2C baud rate + 28 + 4 + read-write + + + + + SCONFIG + Slave Configuration Register + 0x4 + 32 + read-write + 0 + 0xFEFF037F + + + SLVENA + Slave enable + 0 + 1 + read-write + + + NACK + Not acknowledge + 1 + 1 + read-write + + + MATCHSS + Match START or STOP + 2 + 1 + read-write + + + S0IGNORE + S0/S1 errors ignore + 3 + 1 + read-write + + + DDROK + Double Data Rate OK + 4 + 1 + read-write + + + IDRAND + ID random + 8 + 1 + read-write + + + OFFLINE + Offline + 9 + 1 + read-write + + + BAMATCH + Bus available match + 16 + 8 + read-write + + + SADDR + Static address + 25 + 7 + read-write + + + + + SSTATUS + Slave Status Register + 0x8 + 32 + read-write + 0x1000 + 0xFBC7FF7F + + + STNOTSTOP + Status not stop + 0 + 1 + read-only + + + STMSG + Status message + 1 + 1 + read-only + + + STCCCH + Status Common Command Code Handler + 2 + 1 + read-only + + + STREQRD + Status required + 3 + 1 + read-only + + + STREQWR + Status request write + 4 + 1 + read-only + + + STDAA + Status Dynamic Address Assignment + 5 + 1 + read-only + + + STHDR + Status High Data Rate + 6 + 1 + read-only + + + START + Start + 8 + 1 + read-write + + + MATCHED + Matched + 9 + 1 + read-write + + + STOP + Stop + 10 + 1 + read-write + + + RX_PEND + Received message pending + 11 + 1 + read-only + + + TXNOTFULL + Transmit buffer is not full + 12 + 1 + read-only + + + DACHG + DACHG + 13 + 1 + read-write + + + CCC + Common Command Code + 14 + 1 + read-write + + + ERRWARN + Error warning + 15 + 1 + read-only + + + HDRMATCH + High Data Rate command match + 16 + 1 + read-write + + + CHANDLED + Common-Command-Code handled + 17 + 1 + read-write + + + EVENT + Event + 18 + 1 + read-write + + + EVDET + Event details + 20 + 2 + read-only + + + NONE + NONE + 0 + + + NO_REQUEST + NO_REQUEST + 0x1 + + + NACKED + NACKED + 0x2 + + + ACKED + ACKED + 0x3 + + + + + IBIDIS + In-Band Interrupts are disabled + 24 + 1 + read-only + + + MRDIS + Master requests are disabled + 25 + 1 + read-only + + + HJDIS + Hot-Join is disabled + 27 + 1 + read-only + + + ACTSTATE + Activity state from Common Command Codes (CCC) + 28 + 2 + read-only + + + NO_LATENCY + NO_LATENCY + 0 + + + LATENCY_1MS + LATENCY_1MS + 0x1 + + + LATENCY_100MS + LATENCY_100MS + 0x2 + + + LATENCY_10S + LATENCY_10S + 0x3 + + + + + TIMECTRL + Time control + 30 + 2 + read-only + + + NO_TIME_CONTROL + NO_TIME_CONTROL + 0 + + + ASYNC_MODE + ASYNC_MODE + 0x2 + + + + + + + SCTRL + Slave Control Register + 0xC + 32 + read-write + 0 + 0xFF3FFF03 + + + EVENT + EVENT + 0 + 2 + read-write + + + NORMAL_MODE + NORMAL_MODE + 0 + + + IBI + IBI + 0x1 + + + MASTER_REQUEST + MASTER_REQUEST + 0x2 + + + HOT_JOIN_REQUEST + HOT_JOIN_REQUEST + 0x3 + + + + + IBIDATA + In-Band Interrupt Data + 8 + 8 + read-write + + + PENDINT + Pending interrupt + 16 + 4 + read-write + + + ACTSTATE + Activity state (of slave) + 20 + 2 + read-write + + + VENDINFO + Vendor information + 24 + 8 + read-write + + + + + SINTSET + Slave Interrupt Set Register + 0x10 + 32 + read-write + 0 + 0x7FF00 + + + START + Start interrupt enable + 8 + 1 + read-write + + + MATCHED + Match interrupt enable + 9 + 1 + read-write + + + STOP + Stop interrupt enable + 10 + 1 + read-write + + + RXPEND + Receive interrupt enable + 11 + 1 + read-write + + + TXSEND + Transmit interrupt enable + 12 + 1 + read-write + + + DACHG + Dynamic address change interrupt enable + 13 + 1 + read-write + + + CCC + Common Command Code (CCC) (that was not handled by I3C module) interrupt enable + 14 + 1 + read-write + + + ERRWARN + Error/warning interrupt enable + 15 + 1 + read-write + + + DDRMATCHED + Double Data Rate (DDR) interrupt enable + 16 + 1 + read-write + + + CHANDLED + Common Command Code (CCC) (that was handled by I3C module) interrupt enable + 17 + 1 + read-write + + + EVENT + Event interrupt enable + 18 + 1 + read-write + + + + + SINTCLR + Slave Interrupt Clear Register + 0x14 + 32 + read-write + 0 + 0 + oneToClear + + + START + START interrupt enable clear + 8 + 1 + read-write + oneToClear + + + MATCHED + MATCHED interrupt enable clear + 9 + 1 + read-write + oneToClear + + + STOP + STOP interrupt enable clear + 10 + 1 + read-write + oneToClear + + + RXPEND + RXPEND interrupt enable clear + 11 + 1 + read-write + oneToClear + + + TXSEND + TXSEND interrupt enable clear + 12 + 1 + read-write + oneToClear + + + DACHG + DACHG interrupt enable clear + 13 + 1 + read-write + oneToClear + + + CCC + CCC interrupt enable clear + 14 + 1 + read-write + oneToClear + + + ERRWARN + ERRWARN interrupt enable clear + 15 + 1 + read-write + oneToClear + + + DDRMATCHED + DDRMATCHED interrupt enable clear + 16 + 1 + read-write + oneToClear + + + CHANDLED + CHANDLED interrupt enable clear + 17 + 1 + read-write + oneToClear + + + EVENT + EVENT interrupt enable clear + 18 + 1 + read-write + oneToClear + + + + + SINTMASKED + Slave Interrupt Mask Register + 0x18 + 32 + read-only + 0x1000 + 0x7FF00 + + + START + START interrupt mask + 8 + 1 + read-only + + + MATCHED + MATCHED interrupt mask + 9 + 1 + read-only + + + STOP + STOP interrupt mask + 10 + 1 + read-only + + + RXPEND + RXPEND interrupt mask + 11 + 1 + read-only + + + TXSEND + TXSEND interrupt mask + 12 + 1 + read-only + + + DACHG + DACHG interrupt mask + 13 + 1 + read-only + + + CCC + CCC interrupt mask + 14 + 1 + read-only + + + ERRWARN + ERRWARN interrupt mask + 15 + 1 + read-only + + + DDRMATCHED + DDRMATCHED interrupt mask + 16 + 1 + read-only + + + CHANDLED + CHANDLED interrupt mask + 17 + 1 + read-only + + + EVENT + EVENT interrupt mask + 18 + 1 + read-only + + + + + SERRWARN + Slave Errors and Warnings Register + 0x1C + 32 + read-write + 0 + 0x30F1F + + + ORUN + Overrun error + 0 + 1 + read-write + + + URUN + Underrun error + 1 + 1 + read-write + + + URUNNACK + Underrun and Not Acknowledged (NACKed) error + 2 + 1 + read-write + + + TERM + Terminated error + 3 + 1 + read-write + + + INVSTART + Invalid start error + 4 + 1 + read-write + + + SPAR + SDR parity error + 8 + 1 + read-write + + + HPAR + HDR parity error + 9 + 1 + read-write + + + HCRC + HDR-DDR CRC error + 10 + 1 + read-write + + + S0S1 + S0 or S1 error + 11 + 1 + read-write + + + OREAD + Over-read error + 16 + 1 + read-write + + + OWRITE + Over-write error + 17 + 1 + read-write + + + + + SDMACTRL + Slave DMA Control Register + 0x20 + 32 + read-write + 0x10 + 0x3F + + + DMAFB + DMA Read (From-bus) trigger + 0 + 2 + read-write + + + NOT_USED + DMA not used + 0 + + + ENABLE_ONE_FRAME + DMA is enabled for 1 frame + 0x1 + + + ENABLE + DMA enable + 0x2 + + + + + DMATB + DMA Write (To-bus) trigger + 2 + 2 + read-write + + + NOT_USED + NOT_USED + 0 + + + ENABLE_ONE_FRAME + ENABLE_ONE_FRAME + 0x1 + + + ENABLE + ENABLE + 0x2 + + + + + DMAWIDTH + Width of DMA operations + 4 + 2 + read-write + + + BYTE + BYTE + 0 + + + BYTE_AGAIN + BYTE_AGAIN + 0x1 + + + HALF_WORD + HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO. + 0x2 + + + + + + + SDATACTRL + Slave Data Control Register + 0x2C + 32 + read-write + 0x80000030 + 0xDF1F00F7 + + + FLUSHTB + Flush the to-bus buffer/FIFO + 0 + 1 + write-only + + + FLUSHFB + Flushes the from-bus buffer/FIFO + 1 + 1 + write-only + + + UNLOCK + Unlock + 3 + 1 + write-only + + + TXTRIG + Trigger level for TX FIFO emptiness + 4 + 2 + read-write + + + TRIGGREMPTY + Trigger on empty + 0 + + + TRIGGRONEFOURTH + Trigger on full or less + 0x1 + + + TRIGGRONEHALF + Trigger on .5 full or less + 0x2 + + + TRIGGRONELESS + Trigger on 1 less than full or less (Default) + 0x3 + + + + + RXTRIG + Trigger level for RX FIFO fullness + 6 + 2 + read-write + + + TRIGGRNOTEMPTY + Trigger on not empty + 0 + + + TRIGGRONEFOURTH + Trigger on or more full + 0x1 + + + TRIGGRONEHALF + Trigger on .5 or more full + 0x2 + + + TRIGGRTHREEFOURTHS + Trigger on 3/4 or more full + 0x3 + + + + + TXCOUNT + Count of bytes in TX + 16 + 5 + read-only + + + RXCOUNT + Count of bytes in RX + 24 + 5 + read-only + + + TXFULL + TX is full + 30 + 1 + read-only + + + TXISNOTFULL + TX is not full + 0 + + + TXISFULL + TX is full + 0x1 + + + + + RXEMPTY + RX is empty + 31 + 1 + read-only + + + RXISNOTEMPTY + RX is not empty + 0 + + + RXISEMPTY + RX is empty + 0x1 + + + + + + + SWDATAB + Slave Write Data Byte Register + 0x30 + 32 + write-only + 0 + 0 + + + DATA + The data byte to send to the master + 0 + 8 + write-only + + + END + End + 8 + 1 + write-only + + + END_ALSO + End also + 16 + 1 + write-only + + + + + SWDATABE + Slave Write Data Byte End + 0x34 + 32 + write-only + 0 + 0 + + + DATA + The data byte to send to the master + 0 + 8 + write-only + + + + + SWDATAH + Slave Write Data Half-word Register + 0x38 + 32 + write-only + 0 + 0 + + + DATA0 + The 1st byte to send to the master + 0 + 8 + write-only + + + DATA1 + The 2nd byte to send to the master + 8 + 8 + write-only + + + END + End of message + 16 + 1 + write-only + + + + + SWDATAHE + Slave Write Data Half-word End Register + 0x3C + 32 + write-only + 0 + 0 + + + DATA0 + The 1st byte to send to the master + 0 + 8 + write-only + + + DATA1 + The 2nd byte to send to the master + 8 + 8 + write-only + + + + + SRDATAB + Slave Read Data Byte Register + 0x40 + 32 + read-only + 0 + 0xFF + + + DATA0 + Byte read from the master + 0 + 8 + read-only + + + + + SRDATAH + Slave Read Data Half-word Register + 0x48 + 32 + read-only + 0 + 0xFFFF + + + LSB + The 1st byte read from the slave + 0 + 8 + read-only + + + MSB + The 2nd byte read from the slave + 8 + 8 + read-only + + + + + SCAPABILITIES + Slave Capabilities Register + 0x60 + 32 + read-only + 0xE83FFE78 + 0xFFFFFFFF + + + IDENA + ID 48b handler + 0 + 2 + read-only + + + APPLICATION + APPLICATION + 0 + + + HW + HW + 0x1 + + + HW_BUT + HW_BUT + 0x2 + + + PARTNO + PARTNO + 0x3 + + + + + IDREG + ID register + 2 + 4 + read-only + + + HDRSUPP + HDR support + 6 + 3 + read-only + + + MASTER + Master + 9 + 1 + read-only + + + MASTERNOTSUPPORTED + MASTERNOTSUPPORTED + 0 + + + MASTERSUPPORTED + MASTERSUPPORTED + 0x1 + + + + + SADDR + Static address + 10 + 2 + read-only + + + NO_STATIC + NO_STATIC + 0 + + + STATIC + STATIC + 0x1 + + + HW_CONTROL + HW_CONTROL + 0x2 + + + CONFIG + CONFIG + 0x3 + + + + + CCCHANDLE + Common Command Codes (CCC) handling + 12 + 4 + read-only + + + IBI_MR_HJ + In-Band Interrupts, Master Requests, Hot Join events + 16 + 5 + read-only + + + TIMECTRL + Time control + 21 + 1 + read-only + + + NO_TIME_CONTROL_TYPE + NO_TIME_CONTROL_TYPE + 0 + + + ATLEAST1_TIME_CONTROL + NO_TIME_CONTROL_TYPE + 0x1 + + + + + EXTFIFO + External FIFO + 23 + 3 + read-only + + + NO_EXT_FIFO + NO_EXT_FIFO + 0 + + + STD_EXT_FIFO + STD_EXT_FIFO: + 0x1 + + + REQUEST_EXT_FIFO + REQUEST_EXT_FIFO + 0x2 + + + + + FIFOTX + FIFO transmit + 26 + 2 + read-only + + + FIFO_2BYTE + FIFO_2BYTE + 0 + + + FIFO_4BYTE + FIFO_4BYTE + 0x1 + + + FIFO_8BYTE + FIFO_8BYTE + 0x2 + + + FIFO_16BYTE + FIFO_16BYTE + 0x3 + + + + + FIFORX + FIFO receive + 28 + 2 + read-only + + + FIFO_2BYTE + FIFO_2BYTE + 0 + + + FIFO_4BYTE + FIFO_4BYTE + 0x1 + + + FIFO_8BYTE + FIFO_8BYTE + 0x2 + + + FIFO_16BYTE + FIFO_16BYTE + 0x3 + + + + + INT + Interrupt + 30 + 1 + read-only + + + INTERRUPTSNO + Interrupts are not supported + 0 + + + INTERRUPTSYES + Interrupts are supported. + 0x1 + + + + + DMA + DMA + 31 + 1 + read-only + + + DMANO + DMA is not supported + 0 + + + DMAYES + DMA is supported + 0x1 + + + + + + + SDYNADDR + Slave Dynamic Address Register + 0x64 + 32 + read-write + 0 + 0xFFFF00FF + + + DAVALID + DAVALID + 0 + 1 + read-write + + + DANOTASSIGNED + DANOTASSIGNED + 0 + + + DAASSIGNED + DAASSIGNED + 0x1 + + + + + DADDR + Dynamic address + 1 + 7 + read-write + + + MAPIDX + Mapped Dynamic Address + 8 + 4 + write-only + + + MAPSA + Map a Static Address + 12 + 1 + write-only + + + KEY + Key + 16 + 16 + read-write + + + + + SMAXLIMITS + Slave Maximum Limits Register + 0x68 + 32 + read-write + 0 + 0xFFF0FFF0 + + + MAXRD + Maximum read length + 0 + 12 + read-write + + + MAXWR + Maximum write length + 16 + 12 + read-write + + + + + SIDPARTNO + Slave ID Part Number Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + PARTNO + Part number + 0 + 32 + read-write + + + + + SIDEXT + Slave ID Extension Register + 0x70 + 32 + read-write + 0 + 0xFFFF0F + + + DCR + Device Characteristic Register + 8 + 8 + read-write + + + BCR + Bus Characteristics Register + 16 + 8 + read-write + + + + + SVENDORID + Slave Vendor ID Register + 0x74 + 32 + read-write + 0x11B + 0x7FFF + + + VID + Vendor ID + 0 + 15 + read-write + + + + + STCCLOCK + Slave Time Control Clock Register + 0x78 + 32 + read-write + 0x214 + 0xFFFF + + + ACCURACY + Clock accuracy + 0 + 8 + read-write + + + FREQ + Clock frequency + 8 + 8 + read-write + + + + + SMSGMAPADDR + Slave Message-Mapped Address Register + 0x7C + 32 + read-only + 0x214 + 0xFFFF + + + MAPLAST + Matched address index + 0 + 4 + read-only + + + MAPLASTM1 + Previous match index 1 + 8 + 4 + read-only + + + MAPLASTM2 + Previous match index 2 + 16 + 4 + read-only + + + + + MCTRL + Master Main Control Register + 0x84 + 32 + read-write + 0 + 0xFFFFF7 + + + REQUEST + Request + 0 + 3 + read-write + + + NONE + NONE + 0 + + + EMITSTARTADDR + EMITSTARTADDR + 0x1 + + + EMITSTOP + EMITSTOP + 0x2 + + + IBIACKNACK + IBIACKNACK + 0x3 + + + PROCESSDAA + PROCESSDAA + 0x4 + + + FORCEEXIT + FORCEEXIT and IBHR + 0x6 + + + AUTOIBI + AUTOIBI + 0x7 + + + + + TYPE + Bus type with START + 4 + 2 + read-write + + + I3C + I3C + 0 + + + I2C + I2C + 0x1 + + + DDR + DDR + 0x2 + + + FORCEDIBHR + For ForcedExit, this is forced IBHR. + 0x3 + + + + + IBIRESP + In-Band Interrupt (IBI) response + 6 + 2 + read-write + + + ACK + ACK + 0 + + + NACK + NACK + 0x1 + + + ACK_WITH_MANDATORY + ACK_WITH_MANDATORY + 0x2 + + + MANUAL + MANUAL + 0x3 + + + + + DIR + DIR + 8 + 1 + read-write + + + DIRWRITE + DIRWRITE: Write + 0 + + + DIRREAD + DIRREAD: Read + 0x1 + + + + + ADDR + ADDR + 9 + 7 + read-write + + + RDTERM + Read terminate + 16 + 8 + read-write + + + + + MSTATUS + Master Status Register + 0x88 + 32 + read-write + 0x1000 + 0xFF08BFF7 + + + STATE + State of the master + 0 + 3 + read-only + + + IDLE + IDLE + 0 + + + SLVREQ + SLVREQ + 0x1 + + + MSGSDR + MSGSDR + 0x2 + + + NORMACT + NORMACT + 0x3 + + + DDR + MSGDDR + 0x4 + + + DAA + DAA + 0x5 + + + IBIACK + IBIACK + 0x6 + + + IBIRCV + IBIRCV + 0x7 + + + + + BETWEEN + Between + 4 + 1 + read-only + + + INACTIVE + Inactive + 0 + + + ACTIVE + Active + 0x1 + + + + + NACKED + Not acknowledged + 5 + 1 + read-only + + + IBITYPE + In-Band Interrupt (IBI) type + 6 + 2 + read-only + + + NONE + NONE + 0 + + + IBI + IBI + 0x1 + + + MR + MR + 0x2 + + + HJ + HJ + 0x3 + + + + + SLVSTART + Slave start + 8 + 1 + read-write + + + MCTRLDONE + Master control done + 9 + 1 + read-write + + + COMPLETE + COMPLETE + 10 + 1 + read-write + + + RXPEND + RXPEND + 11 + 1 + read-only + + + TXNOTFULL + TX buffer/FIFO not yet full + 12 + 1 + read-only + + + IBIWON + In-Band Interrupt (IBI) won + 13 + 1 + read-write + + + ERRWARN + Error or warning + 15 + 1 + read-only + + + NOWMASTER + Now master (now this module is a master) + 19 + 1 + read-write + + + IBIADDR + IBI address + 24 + 7 + read-only + + + + + MIBIRULES + Master In-band Interrupt Registry and Rules Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0 + ADDR0 + 0 + 6 + read-write + + + ADDR1 + ADDR1 + 6 + 6 + read-write + + + ADDR2 + ADDR2 + 12 + 6 + read-write + + + ADDR3 + ADDR3 + 18 + 6 + read-write + + + ADDR4 + ADDR4 + 24 + 6 + read-write + + + MSB0 + Set Most Significant address Bit to 0 + 30 + 1 + read-write + + + NOBYTE + No IBI byte + 31 + 1 + read-write + + + + + MINTSET + Master Interrupt Set Register + 0x90 + 32 + read-write + 0 + 0x8BF00 + + + SLVSTART + Slave start interrupt enable + 8 + 1 + read-write + + + MCTRLDONE + Master control done interrupt enable + 9 + 1 + read-write + + + COMPLETE + Completed message interrupt enable + 10 + 1 + read-write + + + RXPEND + RX pending interrupt enable + 11 + 1 + read-write + + + TXNOTFULL + TX buffer/FIFO is not full interrupt enable + 12 + 1 + read-write + + + IBIWON + In-Band Interrupt (IBI) won interrupt enable + 13 + 1 + read-write + + + ERRWARN + Error or warning (ERRWARN) interrupt enable + 15 + 1 + read-write + + + NOWMASTER + Now master (now this I3C module is a master) interrupt enable + 19 + 1 + read-write + + + + + MINTCLR + Master Interrupt Clear Register + 0x94 + 32 + write-only + 0 + 0 + + + SLVSTART + SLVSTART interrupt enable clear + 8 + 1 + write-only + + + MCTRLDONE + MCTRLDONE interrupt enable clear + 9 + 1 + write-only + + + COMPLETE + COMPLETE interrupt enable clear + 10 + 1 + write-only + + + RXPEND + RXPEND interrupt enable clear + 11 + 1 + write-only + + + TXNOTFULL + TXNOTFULL interrupt enable clear + 12 + 1 + write-only + + + IBIWON + IBIWON interrupt enable clear + 13 + 1 + write-only + + + ERRWARN + ERRWARN interrupt enable clear + 15 + 1 + write-only + + + NOWMASTER + NOWMASTER interrupt enable clear + 19 + 1 + write-only + + + + + MINTMASKED + Master Interrupt Mask Register + 0x98 + 32 + read-only + 0x1000 + 0x8BF00 + + + SLVSTART + SLVSTART interrupt mask + 8 + 1 + read-only + + + MCTRLDONE + MCTRLDONE interrupt mask + 9 + 1 + read-only + + + COMPLETE + COMPLETE interrupt mask + 10 + 1 + read-only + + + RXPEND + RXPEND interrupt mask + 11 + 1 + read-only + + + TXNOTFULL + TXNOTFULL interrupt mask + 12 + 1 + read-only + + + IBIWON + IBIWON interrupt mask + 13 + 1 + read-only + + + ERRWARN + ERRWARN interrupt mask + 15 + 1 + read-only + + + NOWMASTER + NOWMASTER interrupt mask + 19 + 1 + read-only + + + + + MERRWARN + Master Errors and Warnings Register + 0x9C + 32 + read-write + 0 + 0x1F061C + + + NACK + Not acknowledge (NACK) error + 2 + 1 + read-write + + + WRABT + WRABT (Write abort) error + 3 + 1 + read-write + + + TERM + Terminate error + 4 + 1 + read-write + + + HPAR + High data rate parity + 9 + 1 + read-write + + + HCRC + High data rate CRC error + 10 + 1 + read-write + + + OREAD + Over-read error + 16 + 1 + read-write + + + OWRITE + Over-write error + 17 + 1 + read-write + + + MSGERR + Message error + 18 + 1 + read-write + + + INVREQ + Invalid request error + 19 + 1 + read-write + + + TIMEOUT + TIMEOUT error + 20 + 1 + read-write + + + + + MDMACTRL + Master DMA Control Register + 0xA0 + 32 + read-write + 0x10 + 0x3F + + + DMAFB + DMA from bus + 0 + 2 + read-write + + + NOT_USED + NOT_USED. DMA is not used + 0 + + + ENABLE_ONE_FRAME + ENABLE_ONE_FRAME + 0x1 + + + ENABLE + ENABLE + 0x2 + + + + + DMATB + DMA to bus + 2 + 2 + read-write + + + NOT_USED + NOT_USED. DMA is not used + 0 + + + ENABLE_ONE_FRAME + ENABLE_ONE_FRAME + 0x1 + + + ENABLE + ENABLE + 0x2 + + + + + DMAWIDTH + DMA width + 4 + 2 + read-write + + + BYTE + BYTE + 0 + + + BYTE_AGAIN + BYTE_AGAIN + 0x1 + + + HALF_WORD + HALF_WORD + 0x2 + + + + + + + MDATACTRL + Master Data Control Register + 0xAC + 32 + read-write + 0x80000030 + 0xDF1F00F7 + + + FLUSHTB + Flush to-bus buffer/FIFO + 0 + 1 + write-only + + + FLUSHFB + Flush from-bus buffer/FIFO + 1 + 1 + write-only + + + UNLOCK + Unlock + 3 + 1 + write-only + + + TXTRIG + TX trigger level + 4 + 2 + read-write + + + RXTRIG + RX trigger level + 6 + 2 + read-write + + + TXCOUNT + TX byte count + 16 + 5 + read-only + + + RXCOUNT + RX byte count + 24 + 5 + read-only + + + TXFULL + TX is full + 30 + 1 + read-only + + + RXEMPTY + RX is empty + 31 + 1 + read-only + + + + + MWDATAB + Master Write Data Byte Register + 0xB0 + 32 + write-only + 0 + 0 + + + VALUE + Data byte + 0 + 8 + write-only + + + END + End of message + 8 + 1 + write-only + + + END_ALSO + End of message also + 16 + 1 + write-only + + + + + MWDATABE + Master Write Data Byte End Register + 0xB4 + 32 + write-only + 0 + 0 + + + VALUE + Data + 0 + 8 + write-only + + + + + MWDATAH + Master Write Data Half-word Register + 0xB8 + 32 + write-only + 0 + 0 + + + DATA0 + Data byte 0 + 0 + 8 + write-only + + + DATA1 + Data byte 1 + 8 + 8 + write-only + + + END + End of message + 16 + 1 + write-only + + + + + MWDATAHE + Master Write Data Byte End Register + 0xBC + 32 + write-only + 0 + 0 + + + DATA0 + DATA 0 + 0 + 8 + write-only + + + DATA1 + DATA 1 + 8 + 8 + write-only + + + + + MRDATAB + Master Read Data Byte Register + 0xC0 + 32 + read-only + 0 + 0xFF + + + VALUE + VALUE + 0 + 8 + read-only + + + + + MRDATAH + Master Read Data Half-word Register + 0xC8 + 32 + read-only + 0 + 0xFFFF + + + LSB + LSB + 0 + 8 + read-only + + + MSB + MSB + 8 + 8 + read-only + + + + + MWDATAB1 + Write Byte Data 1 (to bus) + 0xCC + 32 + write-only + 0 + 0xFFFFFFFF + + + VALUE + Value + 0 + 8 + write-only + + + + + MWMSG_SDR_CONTROL + Master Write Message in SDR mode + MWMSG_SDR + 0xD0 + 32 + write-only + 0 + 0 + + + DIR + Direction + 0 + 1 + write-only + + + WRITE + Write + 0 + + + READ + Read + 0x1 + + + + + ADDR + Address to be written to + 1 + 7 + write-only + + + END + End of SDR message + 8 + 1 + write-only + + + I2C + I2C + 10 + 1 + write-only + + + I3CMESSAGE + I3C message + 0 + + + I2CMESSAGE + I2C message + 0x1 + + + + + LEN + Length + 11 + 5 + write-only + + + + + MWMSG_SDR_DATA + Master Write Message Data in SDR mode + MWMSG_SDR + 0xD0 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA16B + Data + 0 + 16 + write-only + + + END + End of message + 16 + 1 + write-only + + + + + MRMSG_SDR + Master Read Message in SDR mode + 0xD4 + 32 + read-only + 0 + 0xFFFF + + + DATA + Data + 0 + 16 + read-only + + + + + MWMSG_DDR_CONTROL + Master Write Message in DDR mode + MWMSG_DDR + 0xD8 + 32 + write-only + 0 + 0 + + + LEN + Length of message + 0 + 10 + write-only + + + END + End of message + 14 + 1 + write-only + + + + + MWMSG_DDR_DATA + Master Write Message Data in DDR mode + MWMSG_DDR + 0xD8 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA16B + Data + 0 + 16 + write-only + + + END + End of message + 16 + 1 + write-only + + + + + MRMSG_DDR + Master Read Message in DDR mode + 0xDC + 32 + read-write + 0 + 0x3FFFFFF + + + DATA + Data + 0 + 16 + read-write + + + CLEN + Current length + 16 + 10 + read-write + + + + + MDYNADDR + Master Dynamic Address Register + 0xE4 + 32 + read-write + 0 + 0xFF + + + DAVALID + Dynamic address valid + 0 + 1 + read-write + + + DADDR + Dynamic address + 1 + 7 + read-write + + + + + SID + Slave Module ID + 0xFFC + 32 + read-only + 0 + 0 + + + ID + ID + 0 + 32 + read-only + + + + + + + LPSPI0 + LPSPI + LPSPI + LPSPI + 0x40036000 + + 0 + 0x800 + registers + + + LPSPI0 + 42 + + + + VERID + Version ID + 0 + 32 + read-only + 0x2000004 + 0xFFFFFFFF + + + FEATURE + Module Identification Number + 0 + 16 + read-only + + + STANDARD + Standard feature set supporting a 32-bit shift register. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x40303 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + PCSNUM + PCS Number + 16 + 8 + read-only + + + + + CR + Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Module Enable + 0 + 1 + read-write + + + DISABLED + Disable + 0 + + + ENABLED + Enable + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + NOT_RESET + Not reset + 0 + + + RESET + Reset + 0x1 + + + + + DOZEN + Doze Mode Enable + 2 + 1 + read-write + + + ENABLED + Enable + 0 + + + DISABLED + Disable + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DISABLED + Disable + 0 + + + ENABLED + Enable + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + NO_EFFECT + No effect + 0 + + + TXFIFO_RST + Reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + NO_EFFECT + No effect + 0 + + + RXFIFO_RST + Reset + 0x1 + + + + + + + SR + Status + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TXDATA_NOT_REQST + Transmit data not requested + 0 + + + TXDATA_REQST + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + NOTREADY + Receive data not ready + 0 + + + READY + Receive data is ready + 0x1 + + + + + WCF + Word Complete Flag + 8 + 1 + read-write + oneToClear + + + NOT_COMPLETED + Not complete + 0 + + + COMPLETED + Complete + 0x1 + + + + + FCF + Frame Complete Flag + 9 + 1 + read-write + oneToClear + + + NOT_COMPLETED + Not complete + 0 + + + COMPLETED + Complete + 0x1 + + + + + TCF + Transfer Complete Flag + 10 + 1 + read-write + oneToClear + + + NOT_COMPLETED + Not complete + 0 + + + COMPLETED + Complete + 0x1 + + + + + TEF + Transmit Error Flag + 11 + 1 + read-write + oneToClear + + + NO_UNDERRUN + No underrun + 0 + + + UNDERRUN + Underrun + 0x1 + + + + + REF + Receive Error Flag + 12 + 1 + read-write + oneToClear + + + NOT_OVERFLOWED + No overflow + 0 + + + OVERFLOWED + Overflow + 0x1 + + + + + DMF + Data Match Flag + 13 + 1 + read-write + oneToClear + + + NO_MATCH + No match + 0 + + + MATCH + Match + 0x1 + + + + + MBF + Module Busy Flag + 24 + 1 + read-only + + + IDLE + LPSPI is idle + 0 + + + BUSY + LPSPI is busy + 0x1 + + + + + + + IER + Interrupt Enable + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + WCIE + Word Complete Interrupt Enable + 8 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FCIE + Frame Complete Interrupt Enable + 9 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TCIE + Transfer Complete Interrupt Enable + 10 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TEIE + Transmit Error Interrupt Enable + 11 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + REIE + Receive Error Interrupt Enable + 12 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 13 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + + + DER + DMA Enable + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FCDE + Frame Complete DMA Enable + 9 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + + + CFGR0 + Configuration 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + DISABLED + Active high + 0 + + + ENABLED + Active low + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HREQPIN + HREQ pin + 0 + + + INPUT_TRIGGER + Input trigger + 0x1 + + + + + HRDIR + Host Request Direction + 3 + 1 + read-write + + + INPUT + Input + 0 + + + OUTPUT + Output + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + STORED + Disable + 0 + + + DISCARDED + Enable + 0x1 + + + + + + + CFGR1 + Configuration 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER + Master Mode + 0 + 1 + read-write + + + SLAVE_MODE + Slave mode + 0 + + + MASTER_MODE + Master mode + 0x1 + + + + + SAMPLE + Sample Point + 1 + 1 + read-write + + + ON_SCK_EDGE + SCK edge + 0 + + + ON_DELAYED_SCK_EDGE + Delayed SCK edge + 0x1 + + + + + AUTOPCS + Automatic PCS + 2 + 1 + read-write + + + DISABLED + Disable + 0 + + + ENABLED + Enable + 0x1 + + + + + NOSTALL + No Stall + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + PARTIAL + Partial Enable + 4 + 1 + read-write + + + DISCARDED + Discard + 0 + + + STORED + Store + 0x1 + + + + + PCSPOL + Peripheral Chip Select Polarity + 8 + 4 + read-write + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + DISABLED + Match is disabled + 0 + + + ENABLED_FIRSTDATAMATCH + Match first data word with compare word + 0x2 + + + ENABLED_ANYDATAMATCH + Match any data word with compare word + 0x3 + + + ENABLED_DATAMATCH_100 + Sequential match, first data word + 0x4 + + + ENABLED_DATAMATCH_101 + Sequential match, any data word + 0x5 + + + ENABLED_DATAMATCH_110 + Match first data word (masked) with compare word (masked) + 0x6 + + + ENABLED_DATAMATCH_111 + Match any data word (masked) with compare word (masked) + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 2 + read-write + + + SIN_IN_SOUT_OUT + SIN is used for input data; SOUT is used for output data. + 0 + + + SIN_BOTH_IN_OUT + SIN is used for both input and output data. Only half-duplex serial transfers are supported. + 0x1 + + + SOUT_BOTH_IN_OUT + SOUT is used for both input and output data. Only half-duplex serial transfers are supported. + 0x2 + + + SOUT_IN_SIN_OUT + SOUT is used for input data; SIN is used for output data. + 0x3 + + + + + OUTCFG + Output Configuration + 26 + 1 + read-write + + + RETAIN_LASTVALUE + Output data retains last value. + 0 + + + TRISTATED + Output data is 3-stated. + 0x1 + + + + + PCSCFG + Peripheral Chip Select Configuration + 27 + 1 + read-write + + + CHIP_SELECT + PCS[3:2] are configured for chip select function + 0 + + + HALFDUPLEX4BIT + PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + 0x1 + + + + + + + DMR0 + Data Match 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 32 + read-write + + + + + DMR1 + Data Match 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH1 + Match 1 Value + 0 + 32 + read-write + + + + + CCR + Clock Configuration + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCKDIV + SCK Divider + 0 + 8 + read-write + + + DBT + Delay Between Transfers + 8 + 8 + read-write + + + PCSSCK + PCS-to-SCK Delay + 16 + 8 + read-write + + + SCKPCS + SCK-to-PCS Delay + 24 + 8 + read-write + + + + + CCR1 + Clock Configuration 1 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCKSET + SCK Setup + 0 + 8 + read-write + + + SCKHLD + SCK Hold + 8 + 8 + read-write + + + PCSPCS + PCS to PCS delay + 16 + 8 + read-write + + + SCKSCK + SCK Inter-Frame Delay + 24 + 8 + read-write + + + + + FCR + FIFO Control + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 3 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 3 + read-write + + + + + FSR + FIFO Status + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 4 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 4 + read-only + + + + + TCR + Transmit Command + 0x60 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + FRAMESZ + Frame Size + 0 + 12 + read-write + + + WIDTH + Transfer Width + 16 + 2 + read-write + + + ONEBIT + 1-bit transfer + 0 + + + TWOBIT + 2-bit transfer + 0x1 + + + FOURBIT + 4-bit transfer + 0x2 + + + + + TXMSK + Transmit Data Mask + 18 + 1 + read-write + + + NORMAL + Normal transfer + 0 + + + MASK + Mask transmit data + 0x1 + + + + + RXMSK + Receive Data Mask + 19 + 1 + read-write + + + NORMAL + Normal transfer + 0 + + + MASK + Receive data is masked + 0x1 + + + + + CONTC + Continuing Command + 20 + 1 + read-write + + + START + Command word for start of new transfer + 0 + + + CONTINUE + Command word for continuing transfer + 0x1 + + + + + CONT + Continuous Transfer + 21 + 1 + read-write + + + DISABLED + Continuous transfer is disabled + 0 + + + ENABLED + Continuous transfer is enabled + 0x1 + + + + + BYSW + Byte Swap + 22 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + LSBF + LSB First + 23 + 1 + read-write + + + MSB_FIRST + Data is transferred MSB first + 0 + + + LSB_FIRST + Data is transferred LSB first + 0x1 + + + + + PCS + Peripheral Chip Select + 24 + 2 + read-write + + + TX_PCS0 + Transfer using PCS[0] + 0 + + + TX_PCS1 + Transfer using PCS[1] + 0x1 + + + TX_PCS2 + Transfer using PCS[2] + 0x2 + + + TX_PCS3 + Transfer using PCS[3] + 0x3 + + + + + PRESCALE + Prescaler Value + 27 + 3 + read-write + + + DIVIDEBY1 + Divide by 1 + 0 + + + DIVIDEBY2 + Divide by 2 + 0x1 + + + DIVIDEBY4 + Divide by 4 + 0x2 + + + DIVIDEBY8 + Divide by 8 + 0x3 + + + DIVIDEBY16 + Divide by 16 + 0x4 + + + DIVIDEBY32 + Divide by 32 + 0x5 + + + DIVIDEBY64 + Divide by 64 + 0x6 + + + DIVIDEBY128 + Divide by 128 + 0x7 + + + + + CPHA + Clock Phase + 30 + 1 + read-write + + + CAPTURED + Captured + 0 + + + CHANGED + Changed + 0x1 + + + + + CPOL + Clock Polarity + 31 + 1 + read-write + + + INACTIVE_LOW + Inactive low + 0 + + + INACTIVE_HIGH + Inactive high + 0x1 + + + + + + + TDR + Transmit Data + 0x64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 32 + write-only + + + + + RSR + Receive Status + 0x70 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + SOF + Start Of Frame + 0 + 1 + read-only + + + NEXT_DATAWORD + Subsequent data word + 0 + + + FIRST_DATAWORD + First data word + 0x1 + + + + + RXEMPTY + RX FIFO Empty + 1 + 1 + read-only + + + NOT_EMPTY + Not empty + 0 + + + EMPTY + Empty + 0x1 + + + + + + + RDR + Receive Data + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 32 + read-only + + + + + RDROR + Receive Data Read Only + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 32 + read-only + + + + + TCBR + Transmit Command Burst + 0x3FC + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Command Data + 0 + 32 + write-only + + + + + 128 + 0x4 + TDBR[%s] + Transmit Data Burst + 0x400 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Data + 0 + 32 + write-only + + + + + 128 + 0x4 + RDBR[%s] + Receive Data Burst + 0x600 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Data + 0 + 32 + read-only + + + + + + + LPSPI1 + LPSPI + LPSPI + 0x40037000 + + 0 + 0x800 + registers + + + LPSPI1 + 43 + + + + LPUART0 + LPUART + LPUART + LPUART + 0x40038000 + + 0 + 0x34 + registers + + + LPUART0 + 44 + + + + VERID + Version ID + 0 + 32 + read-only + 0x4030003 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + STANDARD + Standard feature set + 0x1 + + + MODEM + Standard feature set with MODEM and IrDA support + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x303 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + + + GLOBAL + Global + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST + Software Reset + 1 + 1 + read-write + + + NO_EFFECT + Not reset + 0 + + + RESET + Reset + 0x1 + + + + + + + PINCFG + Pin Configuration + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRGSEL + Trigger Select + 0 + 2 + read-write + + + DISABLED + Input trigger disabled + 0 + + + TRG_RXD + Input trigger used instead of the RXD pin input + 0x1 + + + TRG_CTS + Input trigger used instead of the CTS_B pin input + 0x2 + + + TRG_TXD + Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + 0x3 + + + + + + + BAUD + Baud Rate + 0x10 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + ONE + One stop bit + 0 + + + TWO + Two stop bits + 0x1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + DISABLE + Disables hardware interrupts from STAT[RXEDGIF] + 0 + + + ENABLE + Requests hardware interrupts when STAT[RXEDGIF] is 1 + 0x1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + DISABLE + Disables hardware interrupts from STAT[LBKDIF] (uses polling) + 0 + + + ENABLE + Requests hardware interrupt when STAT[LBKDIF] is 1 + 0x1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + RESYNC + Enables resynchronization + 0 + + + NO_RESYNC + Disables resynchronization + 0x1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + DISABLED + Receiver samples input data using the rising edge of the baud rate clock + 0 + + + ENABLED + Receiver samples input data using the rising and falling edges of the baud rate clock + 0x1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + ADDR_MATCH + Address match wakeup + 0 + + + IDLE_MATCH + Idle match wakeup + 0x1 + + + ONOFF_MATCH + Match on and match off + 0x2 + + + RWU_MATCH + Enables RWU on data match and match on/off for the transmitter CTS input + 0x3 + + + + + RIDMAE + Receiver Idle DMA Enable + 20 + 1 + read-write + + + DISABLED + DMA request disabled + 0 + + + ENABLED + DMA request enabled + 0x1 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + DISABLED + Disables DMA request + 0 + + + ENABLED + Enables DMA request + 0x1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + DISABLED + Disables DMA request + 0 + + + ENABLED + Enables DMA request + 0x1 + + + + + OSR + Oversampling Ratio (OSR) + 24 + 5 + read-write + + + DEFAULT + Results in an OSR of 16 + 0 + + + OSR_4 + Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + 0x3 + + + OSR_5 + Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + 0x4 + + + OSR_6 + Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + 0x5 + + + OSR_7 + Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + 0x6 + + + OSR_8 + Results in an OSR of 8 + 0x7 + + + OSR_9 + Results in an OSR of 9 + 0x8 + + + OSR_10 + Results in an OSR of 10 + 0x9 + + + OSR_11 + Results in an OSR of 11 + 0xA + + + OSR_12 + Results in an OSR of 12 + 0xB + + + OSR_13 + Results in an OSR of 13 + 0xC + + + OSR_14 + Results in an OSR of 14 + 0xD + + + OSR_15 + Results in an OSR of 15 + 0xE + + + OSR_16 + Results in an OSR of 16 + 0xF + + + OSR_17 + Results in an OSR of 17 + 0x10 + + + OSR_18 + Results in an OSR of 18 + 0x11 + + + OSR_19 + Results in an OSR of 19 + 0x12 + + + OSR_20 + Results in an OSR of 20 + 0x13 + + + OSR_21 + Results in an OSR of 21 + 0x14 + + + OSR_22 + Results in an OSR of 22 + 0x15 + + + OSR_23 + Results in an OSR of 23 + 0x16 + + + OSR_24 + Results in an OSR of 24 + 0x17 + + + OSR_25 + Results in an OSR of 25 + 0x18 + + + OSR_26 + Results in an OSR of 26 + 0x19 + + + OSR_27 + Results in an OSR of 27 + 0x1A + + + OSR_28 + Results in an OSR of 28 + 0x1B + + + OSR_29 + Results in an OSR of 29 + 0x1C + + + OSR_30 + Results in an OSR of 30 + 0x1D + + + OSR_31 + Results in an OSR of 31 + 0x1E + + + OSR_32 + Results in an OSR of 32 + 0x1F + + + + + M10 + 10-Bit Mode Select + 29 + 1 + read-write + + + DISABLED + Receiver and transmitter use 7-bit to 9-bit data characters + 0 + + + ENABLED + Receiver and transmitter use 10-bit data characters + 0x1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + + + STAT + Status + 0x14 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + LBKFE + LIN Break Flag Enable + 0 + 1 + read-write + + + DISABLED + Disables LIN break detect + 0 + + + ENABLED + Enables LIN break detect + 0x1 + + + + + AME + Address Mark Enable + 1 + 1 + read-write + + + DISABLED + Address mark in character is MSB + 0 + + + ENABLED + Address mark in character is the last bit before the stop bit (or parity bit when enabled) + 0x1 + + + + + MA2F + Match 2 Flag + 14 + 1 + read-write + oneToClear + + + NOMATCH + Not equal to MA2 + 0 + + + MATCH + Equal to MA2 + 0x1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + oneToClear + + + NOMATCH + Not equal to MA1 + 0 + + + MATCH + Equal to MA1 + 0x1 + + + + + PF + Parity Error Flag (PF) + 16 + 1 + read-write + oneToClear + + + NOPARITY + No parity error detected + 0 + + + PARITY + Parity error detected + 0x1 + + + + + FE + Framing Error Flag (FE) + 17 + 1 + read-write + oneToClear + + + NOERROR + No framing error detected (this does not guarantee that the framing is correct) + 0 + + + ERROR + Framing error detected + 0x1 + + + + + NF + Noise Flag (NF) + 18 + 1 + read-write + oneToClear + + + NONOISE + No noise detected + 0 + + + NOISE + Noise detected + 0x1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + oneToClear + + + NO_OVERRUN + No overrun + 0 + + + OVERRUN + Receive overrun (new LPUART data lost) + 0x1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + oneToClear + + + NOIDLE + No idle line detected + 0 + + + IDLE + Idle line detected + 0x1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + NO_RXDATA + Less than watermark + 0 + + + RXDATA + Equal to or greater than watermark + 0x1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + ACTIVE + Transmitter active (sending data, a preamble, or a break) + 0 + + + COMPLETE + Transmitter idle (transmission activity complete) + 0x1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + TXDATA + Greater than watermark + 0 + + + NO_TXDATA + Equal to or less than watermark + 0x1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + IDLE + Idle, waiting for a start bit + 0 + + + ACTIVE + Receiver active (RXD pin input not idle) + 0x1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + SHORT + 9 to 13 bit times + 0 + + + LONG + 12 to 15 bit times + 0x1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + IDLE_NOTSET + STAT[IDLE] does not become 1 + 0 + + + IDLE_SET + STAT[IDLE] becomes 1 + 0x1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + NOT_INVERTED + Inverted + 0 + + + INVERTED + Not inverted + 0x1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + LSB_FIRST + LSB + 0 + + + MSB_FIRST + MSB + 0x1 + + + + + RXEDGIF + RXD Pin Active Edge Interrupt Flag + 30 + 1 + read-write + oneToClear + + + NO_EDGE + Not occurred + 0 + + + EDGE + Occurred + 0x1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + oneToClear + + + NOT_DETECTED + Not detected + 0 + + + DETECTED + Detected + 0x1 + + + + + + + CTRL + Control + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + EVEN + Even parity + 0 + + + ODD + Odd parity + 0x1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + FROM_START + After the start bit + 0 + + + FROM_STOP + After the stop bit + 0x1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + IDLE + Configures CTRL[RWU] for idle-line wakeup + 0 + + + MARK + Configures CTRL[RWU] with address-mark wakeup + 0x1 + + + + + M + 9-Bit Or 8-Bit Mode Select + 4 + 1 + read-write + + + DATA8 + 8-bit data characters + 0 + + + DATA9 + 9-bit data characters + 0x1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + NO_EFFECT + Internal Loopback mode + 0 + + + ONEWIRE + Single-wire mode + 0x1 + + + + + DOZEEN + Enables LPUART in Doze mode. If this field is 1, LPUART remains active when not in Doze mode. + 6 + 1 + read-write + + + ENABLED + Enables + 0 + + + DISABLED + Disables + 0x1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + NOFFECT + Normal operation: RXD and TXD use separate pins + 0 + + + LOOPBACK + Loop mode or Single-Wire mode + 0x1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + IDLE_1 + 1 + 0 + + + IDLE_2 + 2 + 0x1 + + + IDLE_4 + 4 + 0x2 + + + IDLE_8 + 8 + 0x3 + + + IDLE_16 + 16 + 0x4 + + + IDLE_32 + 32 + 0x5 + + + IDLE_64 + 64 + 0x6 + + + IDLE_128 + 128 + 0x7 + + + + + M7 + 7-Bit Mode Select + 11 + 1 + read-write + + + NO_EFFECT + 8-bit to 10-bit data characters + 0 + + + DATA7 + 7-bit data characters + 0x1 + + + + + MA2IE + Match 2 (MA2F) Interrupt Enable + 14 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + MA1IE + Match 1 (MA1F) Interrupt Enable + 15 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + NO_EFFECT + Normal transmitter operation + 0 + + + TX_BREAK + Queue break character(s) to be sent + 0x1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + NO_EFFECT + Normal receiver operation + 0 + + + RX_WAKEUP + LPUART receiver in standby, waiting for a wakeup condition + 0x1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + DISABLED + Disables hardware interrupts from STAT[IDLE]; use polling + 0 + + + ENABLED + Enables hardware interrupts when STAT[IDLE] = 1 + 0x1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TCIE + Transmission Complete Interrupt Enable + 22 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + NOT_INVERTED + Not inverted + 0 + + + INVERTED + Inverted + 0x1 + + + + + TXDIR + TXD Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + TX_INPUT + TXD pin is an input in Single-Wire mode + 0 + + + TX_OUTPUT + TXD pin is an output in Single-Wire mode + 0x1 + + + + + R9T8 + Receive Bit 9 Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + Data + 0x1C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0 + 0 + 1 + read-write + + + R1T1 + Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1 + 1 + 1 + read-write + + + R2T2 + Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2 + 2 + 1 + read-write + + + R3T3 + Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3 + 3 + 1 + read-write + + + R4T4 + Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4 + 4 + 1 + read-write + + + R5T5 + Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5 + 5 + 1 + read-write + + + R6T6 + Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6 + 6 + 1 + read-write + + + R7T7 + Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7 + 7 + 1 + read-write + + + R8T8 + Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8 + 8 + 1 + read-write + + + R9T9 + Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9 + 9 + 1 + read-write + + + LINBRK + LIN Break + 10 + 1 + read-only + + + NO_BREAK + LIN break not detected or LIN break detect circuitry disabled + 0 + + + BREAK + LIN break detected + 0x1 + + + + + IDLINE + Idle Line + 11 + 1 + read-only + + + NO_IDLE + Received was not idle + 0 + + + IDLE + Receiver was idle + 0x1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + NOT_EMPTY + Contains valid data + 0 + + + EMPTY + Contains invalid data and is empty + 0x1 + + + + + FRETSC + Frame Error Transmit Special Character + 13 + 1 + read-write + + + NO_ERROR + Received without a frame error on reads or transmits a normal character on writes + 0 + + + ERROR + Received with a frame error on reads or transmits an idle or break character on writes + 0x1 + + + + + PARITYE + Parity Error + 14 + 1 + read-only + + + NO_PARITY + Received without a parity error + 0 + + + PARITY + Received with a parity error + 0x1 + + + + + NOISY + Noisy Data Received + 15 + 1 + read-only + + + NO_NOISE + Received without noise + 0 + + + NOISE + Received with noise + 0x1 + + + + + + + MATCH + Match Address + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + MODEM IrDA + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter CTS Enable + 0 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TXRTSE + Transmitter RTS Enable + 1 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TXRTSPOL + Transmitter RTS Polarity + 2 + 1 + read-write + + + LOW + Transmitter RTS is active low + 0 + + + HIGH + Transmitter RTS is active high + 0x1 + + + + + RXRTSE + Receiver RTS Enable + 3 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + START + Sampled at the start of each character + 0 + + + IDLE + Sampled when the transmitter is idle + 0x1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + CTS + The CTS_B pin + 0 + + + MATCH + An internal connection to the receiver address match result + 0x1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 3 + read-write + + + TNP + Transmitter Narrow Pulse + 16 + 2 + read-write + + + ONE_SAMPLE + 1 / OSR + 0 + + + TWO_SAMPLE + 2 / OSR + 0x1 + + + THREE_SAMPLE + 3 / OSR + 0x2 + + + FOUR_SAMPLE + 4 / OSR + 0x3 + + + + + IREN + IR Enable + 18 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + + + FIFO + FIFO + 0x28 + 32 + read-write + 0xC00022 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO Buffer Depth + 0 + 3 + read-only + + + FIFO_1 + Receive FIFO buffer depth = 1 dataword + 0 + + + FIFO_4 + Receive FIFO buffer depth = 4 datawords + 0x1 + + + FIFO_8 + Receive FIFO buffer depth = 8 datawords + 0x2 + + + FIFO_16 + Receive FIFO buffer depth = 16 datawords + 0x3 + + + FIFO_32 + Receive FIFO buffer depth = 32 datawords + 0x4 + + + FIFO_64 + Receive FIFO buffer depth = 64 datawords + 0x5 + + + FIFO_128 + Receive FIFO buffer depth = 128 datawords + 0x6 + + + FIFO_256 + Receive FIFO buffer depth = 256 datawords + 0x7 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + DISABLED + Disables; buffer depth is 1 + 0 + + + ENABLED + Enables; FIFO[RXFIFOSIZE] indicates the buffer depth + 0x1 + + + + + TXFIFOSIZE + Transmit FIFO Buffer Depth + 4 + 3 + read-only + + + FIFO_1 + Transmit FIFO buffer depth = 1 dataword + 0 + + + FIFO_4 + Transmit FIFO buffer depth = 4 datawords + 0x1 + + + FIFO_8 + Transmit FIFO buffer depth = 8 datawords + 0x2 + + + FIFO_16 + Transmit FIFO buffer depth = 16 datawords + 0x3 + + + FIFO_32 + Transmit FIFO buffer depth = 32 datawords + 0x4 + + + FIFO_64 + Transmit FIFO buffer depth = 64 datawords + 0x5 + + + FIFO_128 + Transmit FIFO buffer depth = 128 datawords + 0x6 + + + FIFO_256 + Transmit FIFO buffer depth = 256 datawords + 0x7 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + DISABLED + Disables; buffer depth is 1 + 0 + + + ENABLED + Enables; FIFO[TXFIFOSIZE] indicates the buffer depth + 0x1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + DISABLED + Disables + 0 + + + ENABLED + Enables + 0x1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + DISABLED + Disables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + 0 + + + IDLE_1 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + 0x1 + + + IDLE_2 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + 0x2 + + + IDLE_4 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + 0x3 + + + IDLE_8 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + 0x4 + + + IDLE_16 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + 0x5 + + + IDLE_32 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + 0x6 + + + IDLE_64 + Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + 0x7 + + + + + RXFLUSH + Receive FIFO Flush + 14 + 1 + read-write + + + NO_EFFECT + No effect + 0 + + + RXFIFO_RST + All data is flushed out + 0x1 + + + + + TXFLUSH + Transmit FIFO Flush + 15 + 1 + read-write + + + NO_EFFECT + No effect + 0 + + + TXFIFO_RST + All data is flushed out + 0x1 + + + + + RXUF + Receiver FIFO Underflow Flag + 16 + 1 + read-write + oneToClear + + + NO_UNDERFLOW + No underflow + 0 + + + UNDERFLOW + Underflow + 0x1 + + + + + TXOF + Transmitter FIFO Overflow Flag + 17 + 1 + read-write + oneToClear + + + NO_OVERFLOW + No overflow + 0 + + + OVERFLOW + Overflow + 0x1 + + + + + RXEMPT + Receive FIFO Or Buffer Empty + 22 + 1 + read-only + + + NOT_EMPTY + Not empty + 0 + + + EMPTY + Empty + 0x1 + + + + + TXEMPT + Transmit FIFO Or Buffer Empty + 23 + 1 + read-only + + + NOT_EMPTY + Not empty + 0 + + + EMPTY + Empty + 0x1 + + + + + + + WATER + Watermark + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 3 + read-write + + + TXCOUNT + Transmit Counter + 8 + 4 + read-only + + + RXWATER + Receive Watermark + 16 + 3 + read-write + + + RXCOUNT + Receive Counter + 24 + 4 + read-only + + + + + DATARO + Data Read-Only + 0x30 + 32 + read-only + 0x1000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 16 + read-only + + + + + + + LPUART1 + LPUART + LPUART + 0x40039000 + + 0 + 0x34 + registers + + + LPUART1 + 45 + + + + FLEXIO0 + FLEXIO + FLEXIO + 0x4003A000 + + 0 + 0x920 + registers + + + FLEXIO0 + 46 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x2010003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + standard + Standard features implemented. + 0 + + + state_logic_parallel + Supports state, logic, and parallel modes. + 0x1 + + + pinctrl + Supports pin control registers. + 0x2 + + + state_logic_parallel_pinctrl + Supports state, logic, and parallel modes; plus pin control registers. + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x4200808 + 0xFFFFFFFF + + + SHIFTER + Shifter Number + 0 + 8 + read-only + + + TIMER + Timer Number + 8 + 8 + read-only + + + PIN + Pin Number + 16 + 8 + read-only + + + TRIGGER + Trigger Number + 24 + 8 + read-only + + + + + CTRL + FlexIO Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXEN + FlexIO Enable + 0 + 1 + read-write + + + disable + FlexIO module is disabled. + 0 + + + enable + FlexIO module is enabled. + 0x1 + + + + + SWRST + Software Reset + 1 + 1 + read-write + + + disable + Software reset is disabled + 0 + + + enable + Software reset is enabled, all FlexIO registers except the Control Register are reset. + 0x1 + + + + + FASTACC + Fast Access + 2 + 1 + read-write + + + normal + Configures for normal register accesses to FlexIO + 0 + + + fast + Configures for fast register accesses to FlexIO + 0x1 + + + + + DBGE + Debug Enable + 30 + 1 + read-write + + + disable + FlexIO is disabled in debug modes. + 0 + + + emable + FlexIO is enabled in debug modes + 0x1 + + + + + DOZEN + Doze Enable + 31 + 1 + read-write + + + enable + FlexIO enabled in Doze modes. + 0 + + + disable + FlexIO disabled in Doze modes. + 0x1 + + + + + + + PIN + Pin State Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Pin Data Input + 0 + 32 + read-only + + + + + SHIFTSTAT + Shifter Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + SSF + Shifter Status Flag + 0 + 8 + read-write + oneToClear + + + + + SHIFTERR + Shifter Error Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + SEF + Shifter Error Flags + 0 + 8 + read-write + oneToClear + + + + + TIMSTAT + Timer Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + TSF + Timer Status Flags + 0 + 8 + read-write + oneToClear + + + + + SHIFTSIEN + Shifter Status Interrupt Enable + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIE + Shifter Status Interrupt Enable + 0 + 8 + read-write + + + + + SHIFTEIEN + Shifter Error Interrupt Enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEIE + Shifter Error Interrupt Enable + 0 + 8 + read-write + + + + + TIMIEN + Timer Interrupt Enable Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIE + Timer Status Interrupt Enable + 0 + 8 + read-write + + + + + SHIFTSDEN + Shifter Status DMA Enable + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSDE + Shifter Status DMA Enable + 0 + 8 + read-write + + + + + TIMERSDEN + Timer Status DMA Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSDE + Timer Status DMA Enable + 0 + 8 + read-write + + + + + SHIFTSTATE + Shifter State Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STATE + Current State Pointer + 0 + 3 + read-write + + + + + TRGSTAT + Trigger Status Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + ETSF + External Trigger Status Flags + 0 + 4 + read-write + oneToClear + + + + + TRIGIEN + External Trigger Interrupt Enable Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIE + External Trigger Interrupt Enable + 0 + 4 + read-write + + + + + PINSTAT + Pin Status Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + PSF + Pin Status Flags + 0 + 32 + read-write + oneToClear + + + + + PINIEN + Pin Interrupt Enable Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + PSIE + Pin Status Interrupt Enable + 0 + 32 + read-write + + + + + PINREN + Pin Rising Edge Enable Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE + Pin Rising Edge + 0 + 32 + read-write + + + + + PINFEN + Pin Falling Edge Enable Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + PFE + Pin Falling Edge + 0 + 32 + read-write + + + + + PINOUTD + Pin Output Data Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTD + Output Data + 0 + 32 + read-write + + + + + PINOUTE + Pin Output Enable Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTE + Output Enable + 0 + 32 + read-write + + + + + PINOUTDIS + Pin Output Disable Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTDIS + Output Disable + 0 + 32 + read-write + + + + + PINOUTCLR + Pin Output Clear Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTCLR + Output Clear + 0 + 32 + read-write + + + + + PINOUTSET + Pin Output Set Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTSET + Output Set + 0 + 32 + read-write + + + + + PINOUTTOG + Pin Output Toggle Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTTOG + Output Toggle + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTCTL[%s] + Shifter Control N Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMOD + Shifter Mode + 0 + 3 + read-write + + + disable + Disabled. + 0 + + + receive + Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + 0x1 + + + transmit + Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + 0x2 + + + matchstore + Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + 0x4 + + + matchcont + Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + 0x5 + + + state + State mode. SHIFTBUF contents are used for storing programmable state attributes. + 0x6 + + + logic + Logic mode. SHIFTBUF contents are used for implementing programmable logic lookup table. + 0x7 + + + + + PINPOL + Shifter Pin Polarity + 7 + 1 + read-write + + + active_high + Pin is active high + 0 + + + active_low + Pin is active low + 0x1 + + + + + PINSEL + Shifter Pin Select + 8 + 5 + read-write + + + PINCFG + Shifter Pin Configuration + 16 + 2 + read-write + + + disable + Shifter pin output disabled + 0 + + + opend_bidirouten + Shifter pin open drain or bidirectional output enable + 0x1 + + + bidir_outdata + Shifter pin bidirectional output data + 0x2 + + + output + Shifter pin output + 0x3 + + + + + TIMPOL + Timer Polarity + 23 + 1 + read-write + + + posedge + Shift on posedge of Shift clock + 0 + + + negedge + Shift on negedge of Shift clock + 0x1 + + + + + TIMSEL + Timer Select + 24 + 3 + read-write + + + + + 8 + 0x4 + SHIFTCFG[%s] + Shifter Configuration N Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSTART + Shifter Start bit + 0 + 2 + read-write + + + value00 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + 0 + + + value01 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + 0x1 + + + value10 + Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + 0x2 + + + value11 + Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + 0x3 + + + + + SSTOP + Shifter Stop bit + 4 + 2 + read-write + + + value00 + Stop bit disabled for transmitter/receiver/match store + 0 + + + value01 + Stop bit disabled for transmitter/receiver/match store, receiver/match store will store receive data on the configured shift edge when timer in stop condition + 0x1 + + + value10 + Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0, receiver/match store will also store receive data on the configured shift edge when timer in stop condition + 0x2 + + + value11 + Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1, receiver/match store will also store receive data on the configured shift edge when timer in stop condition + 0x3 + + + + + INSRC + Input Source + 8 + 1 + read-write + + + pin + Pin + 0 + + + shifter_nplus1 + Shifter N+1 Output + 0x1 + + + + + LATST + Late Store + 9 + 1 + read-write + + + preshift + Shift register stores the pre-shift register state. + 0 + + + postshift + Shift register stores the post-shift register state. + 0x1 + + + + + SSIZE + Shifter Size + 12 + 1 + read-write + + + width32 + Shift register is 32-bit. + 0 + + + width24 + Shift register is 24-bit. + 0x1 + + + + + PWIDTH + Parallel Width + 16 + 5 + read-write + + + + + 8 + 0x4 + SHIFTBUF[%s] + Shifter Buffer N Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUF + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFBIS[%s] + Shifter Buffer N Bit Swapped Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBIS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFBYS[%s] + Shifter Buffer N Byte Swapped Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBYS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFBBS[%s] + Shifter Buffer N Bit Byte Swapped Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBBS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + TIMCTL[%s] + Timer Control N Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMOD + Timer Mode + 0 + 3 + read-write + + + disable + Timer Disabled. + 0 + + + dual8bit_baud + Dual 8-bit counters baud mode. + 0x1 + + + dual8bit_pwm_h + Dual 8-bit counters PWM high mode. + 0x2 + + + single16bit + Single 16-bit counter mode. + 0x3 + + + single16bit_disable + Single 16-bit counter disable mode. + 0x4 + + + dual8bit_word + Dual 8-bit counters word mode. + 0x5 + + + dual8bit_pwm_l + Dual 8-bit counters PWM low mode. + 0x6 + + + single16bit_in_capture + Single 16-bit input capture mode. + 0x7 + + + + + ONETIM + Timer One Time Operation + 5 + 1 + read-write + + + not_blocked + The timer enable event is generated as normal. + 0 + + + blocked + The timer enable event is blocked unless timer status flag is clear. + 0x1 + + + + + PININS + Timer Pin Input Select + 6 + 1 + read-write + + + pinsel + Timer pin input and output are selected by PINSEL. + 0 + + + pinselplus1 + Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL. + 0x1 + + + + + PINPOL + Timer Pin Polarity + 7 + 1 + read-write + + + active_high + Pin is active high + 0 + + + active_low + Pin is active low + 0x1 + + + + + PINSEL + Timer Pin Select + 8 + 5 + read-write + + + PINCFG + Timer Pin Configuration + 16 + 2 + read-write + + + outdisable + Timer pin output disabled + 0 + + + opend_bidirouten + Timer pin open drain or bidirectional output enable + 0x1 + + + bidir_outdata + Timer pin bidirectional output data + 0x2 + + + output + Timer pin output + 0x3 + + + + + TRGSRC + Trigger Source + 22 + 1 + read-write + + + ext_trig + External trigger selected + 0 + + + internal_trig + Internal trigger selected + 0x1 + + + + + TRGPOL + Trigger Polarity + 23 + 1 + read-write + + + active_high + Trigger active high + 0 + + + active_low + Trigger active low + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 6 + read-write + + + + + 8 + 0x4 + TIMCFG[%s] + Timer Configuration N Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSTART + Timer Start Bit + 1 + 1 + read-write + + + disable + Start bit disabled + 0 + + + enable + Start bit enabled + 0x1 + + + + + TSTOP + Timer Stop Bit + 4 + 2 + read-write + + + stop_disable + Stop bit disabled + 0 + + + enable_tmrcmp + Stop bit is enabled on timer compare + 0x1 + + + enable_tmrdisable + Stop bit is enabled on timer disable + 0x2 + + + enable_tmr_cmp_dis + Stop bit is enabled on timer compare and timer disable + 0x3 + + + + + TIMENA + Timer Enable + 8 + 3 + read-write + + + enable + Timer always enabled + 0 + + + tmr_nminus1_en + Timer enabled on Timer N-1 enable + 0x1 + + + tmr_trighi_en + Timer enabled on Trigger high + 0x2 + + + tmr_trig_pin_hi_en + Timer enabled on Trigger high and Pin high + 0x3 + + + tmr_pinrise_en + Timer enabled on Pin rising edge + 0x4 + + + tmr_pinrise_trighi_en + Timer enabled on Pin rising edge and Trigger high + 0x5 + + + tmr_trigrise_en + Timer enabled on Trigger rising edge + 0x6 + + + tmr_trigedge_en + Timer enabled on Trigger rising or falling edge + 0x7 + + + + + TIMDIS + Timer Disable + 12 + 3 + read-write + + + never + Timer never disabled + 0 + + + tmr_nminus1 + Timer disabled on Timer N-1 disable + 0x1 + + + tmr_cmp + Timer disabled on Timer compare (upper 8-bits match and decrement) + 0x2 + + + tmr_cmp_triglow + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + 0x3 + + + pin_edge + Timer disabled on Pin rising or falling edge + 0x4 + + + pin_edge_trighi + Timer disabled on Pin rising or falling edge provided Trigger is high + 0x5 + + + trig_falledge + Timer disabled on Trigger falling edge + 0x6 + + + + + TIMRST + Timer Reset + 16 + 3 + read-write + + + never + Timer never reset + 0 + + + tmr_out_hi + Timer reset on Timer Output high. + 0x1 + + + pin_eq_tmr_out + Timer reset on Timer Pin equal to Timer Output + 0x2 + + + trig_eq_tmr_out + Timer reset on Timer Trigger equal to Timer Output + 0x3 + + + pin_rise_edge + Timer reset on Timer Pin rising edge + 0x4 + + + trig_rise_edge + Timer reset on Trigger rising edge + 0x6 + + + trig_edge + Timer reset on Trigger rising or falling edge + 0x7 + + + + + TIMDEC + Timer Decrement + 20 + 3 + read-write + + + flexio_clk_shiftclk_tmr_out + Decrement counter on FlexIO clock, Shift clock equals Timer output. + 0 + + + trig_edge_shiftclk_tmr_out + Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + 0x1 + + + pin_edge_shiftclk_tmr_out + Decrement counter on Pin input (both edges), Shift clock equals Pin input. + 0x2 + + + trig_edge_shiftclk_trig_in + Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + 0x3 + + + flexio_clk_div16_shiftclk_tmr_out + Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. + 0x4 + + + flexio_clk_div256_shiftclk_tmr_out + Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. + 0x5 + + + pin_rise_shiftclk_pin_in + Decrement counter on Pin input (rising edge), Shift clock equals Pin input. + 0x6 + + + trig_rise_shiftclk_trig_in + Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input. + 0x7 + + + + + TIMOUT + Timer Output + 24 + 2 + read-write + + + one + Timer output is logic one when enabled and is not affected by timer reset + 0 + + + zero + Timer output is logic zero when enabled and is not affected by timer reset + 0x1 + + + one_tmrreset + Timer output is logic one when enabled and on timer reset + 0x2 + + + zero_tmrreset + Timer output is logic zero when enabled and on timer reset + 0x3 + + + + + + + 8 + 0x4 + TIMCMP[%s] + Timer Compare N Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP + Timer Compare Value + 0 + 16 + read-write + + + + + 8 + 0x4 + SHIFTBUFNBS[%s] + Shifter Buffer N Nibble Byte Swapped Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNBS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFHWS[%s] + Shifter Buffer N Half Word Swapped Register + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHWS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFNIS[%s] + Shifter Buffer N Nibble Swapped Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNIS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFOES[%s] + Shifter Buffer N Odd Even Swapped Register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFOES + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFEOS[%s] + Shifter Buffer N Even Odd Swapped Register + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFEOS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFHBS[%s] + Shifter Buffer N Halfword Byte Swapped Register + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHBS + Shift Buffer + 0 + 32 + read-write + + + + + + + SEMA42 + SEMA42 + SEMA42 + 0x4003F000 + + 0 + 0x44 + registers + + + + GATE3 + Gate + 0 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE2 + Gate + 0x1 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE1 + Gate + 0x2 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE0 + Gate + 0x3 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE7 + Gate + 0x4 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE6 + Gate + 0x5 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE5 + Gate + 0x6 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE4 + Gate + 0x7 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE11 + Gate + 0x8 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE10 + Gate + 0x9 + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE9 + Gate + 0xA + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE8 + Gate + 0xB + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE15 + Gate + 0xC + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE14 + Gate + 0xD + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE13 + Gate + 0xE + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + GATE12 + Gate + 0xF + 8 + read-write + 0 + 0xFF + + + GTFSM + Gate Finite State Machine + 0 + 4 + read-write + + + UNLOCKED + The gate is unlocked (free). + 0 + + + LOCKED_BY_D0 + Domain 0 locked the gate. + 0x1 + + + LOCKED_BY_D1 + Domain 1 locked the gate. + 0x2 + + + LOCKED_BY_D2 + Domain 2 locked the gate. + 0x3 + + + LOCKED_BY_D3 + Domain 3 locked the gate. + 0x4 + + + LOCKED_BY_D4 + Domain 4 locked the gate. + 0x5 + + + LOCKED_BY_D5 + Domain 5 locked the gate. + 0x6 + + + LOCKED_BY_D6 + Domain 6 locked the gate. + 0x7 + + + LOCKED_BY_D7 + Domain 7 locked the gate. + 0x8 + + + LOCKED_BY_D8 + Domain 8 locked the gate. + 0x9 + + + LOCKED_BY_D9 + Domain 9 locked the gate. + 0xA + + + LOCKED_BY_D10 + Domain 10 locked the gate. + 0xB + + + LOCKED_BY_D11 + Domain 11 locked the gate. + 0xC + + + LOCKED_BY_D12 + Domain 12 locked the gate. + 0xD + + + LOCKED_BY_D13 + Domain 13 locked the gate. + 0xE + + + LOCKED_BY_D14 + Domain 14 locked the gate. + 0xF + + + + + + + RSTGT_R + Reset Gate Read + RSTGT + 0x42 + 16 + read-only + 0 + 0xFFFF + + + RSTGTN + Reset Gate Number + 0 + 8 + read-only + + + RSTGMS + Reset Gate Domain + 8 + 4 + read-only + + + RSTGSM + Reset Gate Finite State Machine + 12 + 2 + read-only + + + IDLE + Idle, waiting for the first data pattern write. + 0 + + + WAITING + Waiting for the second data pattern write + 0x1 + + + TWO_WRITE_DONE + The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. + 0x2 + + + + + + + RSTGT_W + Reset Gate Write + RSTGT + 0x42 + 16 + write-only + 0 + 0 + + + RSTGTN + Reset Gate Number + 0 + 8 + write-only + + + RSTGDP + Reset Gate Data Pattern + 8 + 8 + write-only + + + + + + + RFMC + RFMC + RFMC + 0x40040000 + + 0 + 0x48 + registers + + + RF_IMU0 + 48 + + + RF_IMU1 + 49 + + + RF_Generic + 54 + + + RF_BRIC + 55 + + + RF_LANT_SW + 56 + + + RFMC + 57 + + + + VERID + RFMC Version ID Register + 0 + 32 + read-only + 0x2004500 + 0xFFFFFFFF + + + RADIO_ID + Radio Identification Number + 0 + 16 + read-only + + + MINOR + Minor RFMC Version Number + 16 + 8 + read-only + + + MAJOR + Major RFMC Version Number + 24 + 8 + read-only + + + + + PARAM + RFMC Parameter Register + 0x4 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + RF2p4GHz_EN + Indicates whether 2 + 0 + 1 + read-only + + + RF2p4GHz_EN_0 + 2.4GHz radio disabled + 0 + + + RF2p4GHz_EN_1 + 2.4GHz radio enabled + 0x1 + + + + + + + CTRL + RFMC Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST_MSK + Reset Mask + 30 + 1 + read-write + + + RFMC_RST + S/W System Reset for RFMC + 31 + 1 + read-write + + + RFMC_RST_0 + Release the RFMC from reset + 0 + + + RFMC_RST_1 + Hold the RFMC in reset + 0x1 + + + + + + + XO_CTRL + XO Control Register + 0xC + 32 + read-write + 0x220000 + 0xFFFFFFFF + + + RDY_IE + XTAL Ready Interrupt Enable + 0 + 1 + read-write + + + RDY_IE_0 + XTAL ready interrupt disabled + 0 + + + RDY_IE_1 + XTAL ready interrupt enabled + 0x1 + + + + + INT_IE + XO Internal Request Interrupt Enable + 1 + 1 + read-write + + + INT_IE_0 + XO internal request interrupt disabled + 0 + + + INT_IE_1 + XO internal request interrupt enabled + 0x1 + + + + + EXT_IE + XO External Request Interrupt Enable + 2 + 1 + read-write + + + EXT_IE_0 + XO external request interrupt disabled + 0 + + + EXT_IE_1 + XO external request interrupt enabled + 0x1 + + + + + XTAL_OUT_EN + XTAL_OUT Output Pin Enable + 4 + 1 + read-write + + + XTAL_OUT_EN_0 + XTAL_OUT output disabled + 0 + + + XTAL_OUT_EN_1 + XTAL_OUT output enabled + 0x1 + + + + + XTAL_REQ_OBE + XTAL_REQ Output Pin Enable + 5 + 1 + read-write + + + XTAL_REQ_OBE_0 + XTAL_REQ output pin disabled + 0 + + + XTAL_REQ_OBE_1 + XTAL_REQ output pin enabled + 0x1 + + + + + XTAL_EN_IBE + XTAL_OUT_EN Input Pin Enable + 6 + 1 + read-write + + + XTAL_EN_IBE_0 + XTAL_OUT_EN input pin disabled + 0 + + + XTAL_EN_IBE_1 + XTAL_OUT_EN input pin enabled + 0x1 + + + + + WKUP_OFFSET + XO Wakeup Offset + 8 + 6 + read-write + + + RDY_CNT + XTAL Ready Count + 16 + 2 + read-write + + + RDY_CNT_0 + 1024 + 0 + + + RDY_CNT_1 + 2048 + 0x1 + + + RDY_CNT_2 + 4096 + 0x2 + + + RDY_CNT_3 + 8192 + 0x3 + + + + + RDY_CNT_OFF + XTAL Ready Count Disable + 18 + 1 + read-write + + + RDY_CNT_OFF_0 + XTAL Ready Count Enabled + 0 + + + RDY_CNT_OFF_1 + XTAL Ready Count Disabled + 0x1 + + + + + XTAL_OUT_INV + XO Clock Output Invert + 19 + 1 + read-write + + + XTAL_OUT_INV_0 + XTAL_OUT not inverted + 0 + + + XTAL_OUT_INV_1 + XTAL_OUT inverted + 0x1 + + + + + LDO_BYPASS + XO LDO Bypass + 20 + 1 + read-write + + + EXT_MODE + External Clock Mode + 21 + 1 + read-write + + + EXT_MODE_0 + DC coupled external clock mode (amplifier powered down). + 0 + + + EXT_MODE_1 + AC coupled external clock mode or crystal mode (amplifier powered up). + 0x1 + + + + + XTAL_RDY_OVR_EN + XTAL Ready Override Enable + 22 + 1 + read-write + + + XTAL_RDY_OVR + XTAL Ready Override + 23 + 1 + read-write + + + SPARE + XO Spare Registers + 24 + 4 + read-write + + + XO_LDO_OVR + XO LDO Enable Override + 28 + 1 + read-write + + + XO_LDO_OVR_0 + XO LDO enable not overridden + 0 + + + XO_LDO_OVR_1 + XO LDO enable overridden by XO_LDO_EN bit + 0x1 + + + + + XO_LDO_EN + XO LDO Enable + 29 + 1 + read-write + + + XO_LDO_EN_0 + XO LDO disabled + 0 + + + XO_LDO_EN_1 + XO LDO enabled + 0x1 + + + + + XO_ANA_OVR + XO Analog Enable Override + 30 + 1 + read-write + + + XO_ANA_OVR_0 + XO analog enable not overridden + 0 + + + XO_ANA_OVR_1 + XO analog enable overridden by XO_ANA_EN bit + 0x1 + + + + + XO_ANA_EN + XO Analog Enable + 31 + 1 + read-write + + + XO_ANA_EN_0 + XO analog disabled + 0 + + + XO_ANA_EN_1 + XO analog enabled + 0x1 + + + + + + + XO_STAT + XO Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDY_FLAG + XTAL Ready Flag + 0 + 1 + read-write + oneToClear + + + INT_FLAG + XO Internal Request Flag + 1 + 1 + read-write + oneToClear + + + EXT_FLAG + XO External Request Flag + 2 + 1 + read-write + oneToClear + + + XTAL_RDY + XTAL Ready + 4 + 1 + read-only + + + XO_EN + XO_EN + 5 + 1 + read-only + + + + + XO_TEST + XO Test Register + 0x14 + 32 + read-write + 0x61E5 + 0xFFFFFFFF + + + ISEL + XO Amplifier Current Select + 0 + 4 + read-write + + + ISEL_0 + 40uA (min) + 0 + + + ISEL_1 + 80uA + 0x1 + + + ISEL_5 + 240uA (default) + 0x5 + + + ISEL_15 + 640uA (max) + 0xF + + + + + CDAC + XO On-chip Load Capacitor Trim + 4 + 6 + read-write + + + CDAC_0 + 6pF + 0 + + + CDAC_63 + 11pF + 0x3F + + + + + CAP_OFF + XO Load Capacitor Disable + 10 + 1 + read-write + + + AUX_PD + XO CLK_AUX_DRV Powerdown + 11 + 1 + read-write + + + AMP_FORCE + XO Amplifier Force PTAT Startup + 12 + 1 + read-write + + + DYN_ISEL + XO Amplifier: enable current switching during startup + 13 + 1 + read-write + + + DYN_CAP + XO On-chip Load Capacitor: enable switching during startup + 14 + 1 + read-write + + + LDO_TRIM + XO LDO Output Voltage Trim + 16 + 2 + read-write + + + LDO_TRIM_0 + 0.92V + 0 + + + LDO_TRIM_1 + 0.885V + 0x1 + + + LDO_TRIM_2 + 0.955V + 0x2 + + + LDO_TRIM_3 + 1.011V + 0x3 + + + + + LDO_BUMP + XO LDO PTAT Current Bump + 18 + 2 + read-write + + + LDO_BUMP_0 + PTAT current bump default + 0 + + + LDO_BUMP_1 + PTAT current boost: +30% + 0x1 + + + + + LDO_FORCE + XO LDO Force PTAT Startup + 20 + 1 + read-write + + + + + RF2p4GHz_CTRL + 2.4GHz Radio Control Register + 0x18 + 32 + read-write + 0x20000F00 + 0xFFFFFFFF + + + WOR_WKUP_IE + WOR Wakeup Interrupt Enable + 0 + 1 + read-write + + + WOR_WKUP_IE_0 + WOR wakeup interrupt disabled + 0 + + + WOR_WKUP_IE_1 + WOR wakeup interrupt enabled + 0x1 + + + + + MAN_WKUP_IE + MAN Wakeup Interrupt Enable + 1 + 1 + read-write + + + MAN_WKUP_IE_0 + MAN wakeup interrupt disabled + 0 + + + MAN_WKUP_IE_1 + MAN wakeup interrupt enabled + 0x1 + + + + + BLE_WKUP_IE + Bluetooth LE Wakeup Interrupt Enable + 2 + 1 + read-write + + + BLE_WKUP_IE_0 + Bluetooth LE wakeup interrupt disabled + 0 + + + BLE_WKUP_IE_1 + Bluetooth LE wakeup interrupt enabled + 0x1 + + + + + RFACT_IE + RF_ACTIVE Interrupt Enable + 3 + 1 + read-write + + + RFACT_IE_0 + RF_ACTIVE interrupt disabled + 0 + + + RFACT_IE_1 + RF_ACTIVE interrupt enabled + 0x1 + + + + + LP_WKUP_IE + Low Power Wakeup Interrupt Enable + 4 + 1 + read-write + + + LP_WKUP_IE_0 + Low Power wakeup interrupt disabled + 0 + + + LP_WKUP_IE_1 + Low Power wakeup interrupt enabled + 0x1 + + + + + BLE_WKUP + Bluetooth LE Wakeup + 5 + 1 + read-write + + + BLE_WKUP_0 + Bluetooth LE low power mode wakeup deasserted + 0 + + + BLE_WKUP_1 + Bluetooth LE low power mode wakeup asserted + 0x1 + + + + + BLE_LP_EN + Bluetooth LE Low Power Enable + 6 + 1 + read-write + + + BLE_LP_EN_0 + Bluetooth LE wakeup request disabled + 0 + + + BLE_LP_EN_1 + Bluetooth LE wakeup request enabled + 0x1 + + + + + LP_ENTER + S/W Low Power Entry Request + 7 + 1 + read-write + + + LP_ENTER_0 + Deassert S/W request for low power mode entry + 0 + + + LP_ENTER_1 + Assert S/W request for low power mode entry + 0x1 + + + + + LP_MODE + Radio Low Power Mode + 8 + 4 + read-write + + + LP_MODE_0 + Active: clock gating only (only intended for debug) + 0 + + + LP_MODE_1 + Sleep: clock gating, PMC in low power mode(only intended for debug) + 0x1 + + + LP_MODE_3 + Deep Sleep: low power static mode with retention of digital logic and SRAMs. + 0x3 + + + LP_MODE_7 + Power Down: power down of radio digital logic, optional SRAM retention. + 0x7 + + + LP_MODE_15 + Deep Power Down: power down of radio digital logic and SRAMs. + 0xF + + + + + LP_WKUP_DLY + LP Wakeup Delay + 12 + 6 + read-write + + + SFA_TRIG_EN + SFA Trigger Enable + 18 + 3 + read-write + + + SFA_TRIG_EN_0 + MAN Low Power Controller is not allowed to cause an SFA trigger. + #xx0 + + + SFA_TRIG_EN_1 + MAN Low Power Controller is allowed to cause an SFA trigger. + #xx1 + + + + + LP_STOP_REQ_GLITCH_DIS + LP_STOP_REQ Glitch Disable for 2.4GHz Radio + 21 + 1 + read-write + + + XO_EN_GLITCH_DIS + XO_EN Glitch Disable for 2.4GHz Radio + 22 + 1 + read-write + + + XO_EN + XO Enable for 2.4GHz Radio + 23 + 1 + read-write + + + XO_EN_0 + XO software enable deasserted + 0 + + + XO_EN_1 + XO software enable asserted + 0x1 + + + + + CLK_OVR + Clock Gating Override + 24 + 4 + read-write + + + CLK_OVR_0 + TIMER clock only enabled when TIM_EN=1 + #xxx0 + + + CLK_OVR_1 + TIMER clock always enabled + #xxx1 + + + + + CPU_RST_LOCK + LOCK for CPU_RST + 28 + 1 + read-write + + + CPU_RST_LOCK_0 + CPU_RST bit is not locked + 0 + + + CPU_RST_LOCK_1 + CPU_RST bit is locked + 0x1 + + + + + CPU_RST + S/W Reset for 2.4GHz Radio CPU + 29 + 1 + read-write + + + CPU_RST_0 + Release the 2.4GHz radio CPU from reset + 0 + + + CPU_RST_1 + Hold the 2.4GHz radio CPU in reset + 0x1 + + + + + RF_POR + S/W Power-on-Reset for 2.4GHz Radio + 30 + 1 + read-write + + + RF_POR_0 + Release the 2.4GHz radio from power-on-reset + 0 + + + RF_POR_1 + Hold the 2.4GHz radio in power-on-reset + 0x1 + + + + + RST + S/W Reset for 2.4GHz Radio + 31 + 1 + read-write + + + RST_0 + Release the 2.4GHz radio from reset + 0 + + + RST_1 + Hold the 2.4GHz radio in reset + 0x1 + + + + + + + RF2p4GHz_STAT + 2.4GHz Radio Status Register + 0x1C + 32 + read-write + 0x400 + 0xFFFFFFFF + + + WOR_WKUP_FLAG + WOR Wakeup Flag + 0 + 1 + read-write + oneToClear + + + MAN_WKUP_FLAG + MAN Wakeup Flag + 1 + 1 + read-write + oneToClear + + + BLE_WKUP_FLAG + Bluetooth LE Wakeup Flag + 2 + 1 + read-write + oneToClear + + + RFACT_FLAG + RF_ACTIVE Flag + 3 + 1 + read-write + oneToClear + + + LP_WKUP_FLAG + Low Power Wakeup Flag + 4 + 1 + read-write + oneToClear + + + SLP_RDY_STAT + RF_CMC Sleep Ready Status + 5 + 1 + read-only + + + RST_STAT + Reset Status + 6 + 1 + read-only + + + RST_STAT_0 + Reset is not asserted. + 0 + + + RST_STAT_1 + Reset is asserted. + 0x1 + + + + + FRO_CLK_VLD_STAT + FRO Clock Valid Status + 7 + 1 + read-only + + + LP_REQ_STAT + Low Power Request Status + 8 + 1 + read-only + + + LP_ACK_STAT + Low Power Acknowledge Status + 9 + 1 + read-only + + + BLE_WKUP_STAT + Bluetooth LE Wakeup Status + 10 + 1 + read-only + + + WOR_STATE + WOR Low Power State + 12 + 3 + read-only + + + WOR_STATE_0 + RESET state (WOR_EN=0). + 0 + + + WOR_STATE_1 + ACTIVE state (XO enabled, RF_ACTIVE asserted, LP request deasserted). + 0x1 + + + WOR_STATE_2 + SLEEP state (XO disabled, RF_ACTIVE deasserted, LP request asserted). + 0x2 + + + WOR_STATE_3 + WAKEUP state (XO enabled, RF_ACTIVE asserted after RFACT_WKUP_DLY, LP request deasserted after LP_WKUP_DLY). + 0x3 + + + + + MAN_STATE + MAN Low Power State + 15 + 3 + read-only + + + MAN_STATE_0 + RESET state (MAN_EN=0). + 0 + + + MAN_STATE_1 + ACTIVE state (XO enabled, RF_ACTIVE asserted, LP request deasserted). + 0x1 + + + MAN_STATE_2 + SLEEP state (XO disabled, RF_ACTIVE deasserted, LP request asserted). + 0x2 + + + MAN_STATE_3 + WAKEUP state (XO enabled, RF_ACTIVE asserted after RFACT_WKUP_DLY, LP request deasserted after LP_WKUP_DLY). + 0x3 + + + + + BLE_STATE + Bluetooth LE Low Power State + 18 + 3 + read-only + + + BLE_STATE_0 + RESET state (BLE_LP_EN=0). + 0 + + + BLE_STATE_1 + ACTIVE state (XO enabled, RF_ACTIVE asserted, LP request deasserted). + 0x1 + + + BLE_STATE_2 + SLEEP state (XO disabled, RF_ACTIVE deasserted, LP request asserted). + 0x2 + + + BLE_STATE_3 + WAKEUP state (XO enabled, RF_ACTIVE asserted after RFACT_WKUP_DLY, LP request deasserted after LP_WKUP_DLY). + 0x3 + + + + + + + RF2p4GHz_COEXT + 2.4GHz Radio Coexistence Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFGPO_OBE + RF_GPO Output Buffer Enable + 0 + 8 + read-write + + + RFGPO_SRC + RF_GPO Source + 8 + 3 + read-write + + + RFGPO_SRC_0 + RF_GPO[7:0] = {coext[3:0], fem_ctrl[3:0]} + 0 + + + RFGPO_SRC_1 + RF_GPO[7:0] = {fem_ctrl[3:0], coext[3:0]} + 0x1 + + + RFGPO_SRC_2 + RF_GPO[7:0] = {lant_lut_gpio[3:0], fem_ctrl[3:0]} + 0x2 + + + RFGPO_SRC_3 + RF_GPO[7:0] = {fem_ctrl[3:0], lant_lut_gpio[3:0]} + 0x3 + + + RFGPO_SRC_4 + RF_GPO[7:0] = {lant_lut_gpio[3:0], coext[3:0]} + 0x4 + + + RFGPO_SRC_5 + RF_GPO[7:0] = {coext[3:0], lant_lut_gpio[3:0]} + 0x5 + + + + + PORTA_PWR + PORTA Power + 11 + 1 + read-write + + + PORTA_PWR_0 + PORTA pins do not remain powered (default behavior) + 0 + + + PORTA_PWR_1 + PORTA pins remain powered + 0x1 + + + + + RFACT_SRC + RF_ACTIVE Source + 12 + 2 + read-write + + + RFACT_SRC_0 + RF_ACTIVE is driven by the RFMC + 0 + + + RFACT_SRC_1 + RF_ACTIVE is driven by the TSM/LL + 0x1 + + + RFACT_SRC_2 + RF_ACTIVE is driven by the Bluetooth LE wakeup request (bt_clk_req) + 0x2 + + + + + RFACT_IDIS + RF_ACTIVE Idle Disable + 14 + 1 + read-write + + + RFACT_IDIS_0 + RF_ACTIVE does not deassert when TSM is idle (will deassert on next low power mode entry) + 0 + + + RFACT_IDIS_1 + RF_ACTIVE will deassert when TSM is idle + 0x1 + + + + + RFACT_EN + S/W Enable of RF_ACTIVE pin + 15 + 1 + read-write + + + RFACT_EN_0 + Take no action + 0 + + + RFACT_EN_1 + Assert RF_ACTIVE pin + 0x1 + + + + + RFACT_WKUP_DLY + RF_ACTIVE Wakeup Delay + 16 + 6 + read-write + + + QREQ_SRC + QUIET_REQ Source + 24 + 1 + read-write + + + QREQ_SRC_0 + QUIET_REQ is driven by the RFMC + 0 + + + QREQ_SRC_1 + QUIET_REQ is driven by the TSM/LL + 0x1 + + + + + QREQ_SOC_EN + QUIET_REQ Enable for SOC Core Flash + 25 + 1 + read-write + + + QREQ_SOC_EN_0 + QUIET_REQ is not enabled for SOC Core Flash + 0 + + + QREQ_SOC_EN_1 + QUIET_REQ is enabled for SOC Core Flash + 0x1 + + + + + QREQ_RF_EN + QUIET_REQ Enable for Radio CPU Flash + 26 + 1 + read-write + + + QREQ_RF_EN_0 + QUIET_REQ is not enabled for Radio CPU Flash + 0 + + + QREQ_RF_EN_1 + QUIET_REQ is enabled for Radio CPU Flash + 0x1 + + + + + RFNA_IBE + RF_NOT_ALLOWED Input Buffer Enables + 28 + 3 + read-write + + + RFNA_IBE_0 + RF_NOT_ALLOWED input pin disabled + 0 + + + RFNA_IBE_1 + RF_NOT_ALLOWED input pin uses PTA16 + 0x1 + + + RFNA_IBE_2 + RF_NOT_ALLOWED input pin uses PTA17 + 0x2 + + + RFNA_IBE_3 + RF_NOT_ALLOWED input pin uses PTA22 + 0x3 + + + RFNA_IBE_4 + RF_NOT_ALLOWED input pin uses PTC7 + 0x4 + + + RFNA_IBE_5 + RF_NOT_ALLOWED input pin uses PTD6 + 0x5 + + + + + + + RF2p4GHz_TIMER + 2.4GHz TIMER Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME + Timer Count + 0 + 24 + read-only + + + TIM_CLR + Timer Clear + 30 + 1 + read-write + + + TIM_CLR_0 + Timer not cleared + 0 + + + TIM_CLR_1 + Timer cleared + 0x1 + + + + + TIM_EN + Timer Enable + 31 + 1 + read-write + + + TIM_EN_0 + Timer disabled + 0 + + + TIM_EN_1 + Timer enabled + 0x1 + + + + + + + RF2p4GHz_WOR1 + 2.4GHz WOR Register 1 + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + DURATION_TGT + WOR Low Power Duration Target + 0 + 24 + read-only + + + ENTER_REQ + WOR Low Power Entry Request + 31 + 1 + read-only + + + ENTER_REQ_0 + WOR low power mode request deasserted + 0 + + + ENTER_REQ_1 + WOR low power mode request asserted + 0x1 + + + + + + + RF2p4GHz_WOR2 + 2.4GHz WOR Register 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + DURATION + WOR Low Power Duration + 0 + 24 + read-only + + + WOR_WKUP + WOR Wakeup + 30 + 1 + read-write + + + WOR_WKUP_0 + WOR low power mode wakeup deasserted + 0 + + + WOR_WKUP_1 + WOR low power mode wakeup asserted + 0x1 + + + + + WOR_EN + WOR Enable + 31 + 1 + read-write + + + WOR_EN_0 + WOR low power mode entry/wakeup disabled + 0 + + + WOR_EN_1 + WOR low power mode entry/wakeup enabled + 0x1 + + + + + + + RF2p4GHz_MAN1 + 2.4GHz MAN Register 1 + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENTER_TIME + MAN Low Power Entry Time Stamp + 0 + 24 + read-only + + + ENTER_REQ + MAN Low Power Entry Request + 31 + 1 + read-only + + + ENTER_REQ_0 + MAN low power mode request deasserted + 0 + + + ENTER_REQ_1 + MAN low power mode request asserted + 0x1 + + + + + + + RF2p4GHz_MAN2 + 2.4GHz MAN Register 2 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + WKUP_TIME + MAN Low Power Wakeup Time Stamp + 0 + 24 + read-only + + + MAN_WKUP + MAN Wakeup + 30 + 1 + read-write + + + MAN_WKUP_0 + MAN low power mode wakeup deasserted + 0 + + + MAN_WKUP_1 + MAN low power mode wakeup asserted + 0x1 + + + + + MAN_EN + MAN Enable + 31 + 1 + read-write + + + MAN_EN_0 + MAN low power mode entry/wakeup disabled + 0 + + + MAN_EN_1 + MAN low power mode entry/wakeup enabled + 0x1 + + + + + + + RF2p4GHz_MAN3 + 2.4GHz MAN Register 3 + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENTER_TIME_CAPT + MAN Low Power Entry Time Captured + 0 + 24 + read-only + + + + + RF2p4GHz_MAN4 + 2.4GHz MAN Register 4 + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + WKUP_TIME_CAPT + MAN Low Power Wakeup Time Captured + 0 + 24 + read-only + + + + + + + DSB0 + DSB + DSB + 0x40041000 + + 0 + 0x400 + registers + + + DSB + 58 + + + + CSR + Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFTRST + Soft Reset + 0 + 1 + read-write + + + false + No operation. + 0 + + + true + Reset the data stream buffer. + 0x1 + + + + + DSB_EN + Data Stream Buffer Enable + 1 + 1 + read-write + + + false + Buffer is disabled. + 0 + + + true + Buffer is enabled. + 0x1 + + + + + DMA_EN + DMA Transfer Enable + 2 + 1 + read-write + + + false + DMA transfers are disabled. + 0 + + + true + DMA transfers are enabled. + 0x1 + + + + + INT_EN + Interrupt Request Enable + 3 + 1 + read-write + + + false + Interrupt requests on data ready or DMA done are disabled. + 0 + + + true + Interrupt requests on data ready or DMA done are enabled. + 0x1 + + + + + ERR_EN + Error Interrupt Request Enable + 4 + 1 + read-write + + + false + Error interrupt requests on overflow, underrun, or bus error are disabled. + 0 + + + true + Error interrupt requests on overflow, underrun, or bus error are enabled. + 0x1 + + + + + CBT_EN + Continuous Burst Transfer Enable + 5 + 1 + read-write + + + DISABLE + Continuous burst transfer mode is disabled. + 0 + + + ENABLE + Continuous burst transfer mode is enabled. + 0x1 + + + + + + + INT + Interrupt Request Status Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRDY + Data Ready + 0 + 1 + read-only + + + false + No data to read (watermark has not been reached) + 0 + + + true + Data is ready to read (watermark has been reached) + 0x1 + + + + + OVRF + Overflow Error + 1 + 1 + read-write + oneToClear + + + false + No overflow error + 0 + + + true + The last recorded error is a buffer overflow + 0x1 + + + + + UNDR + Underrun Error + 2 + 1 + read-write + oneToClear + + + false + No underrun error + 0 + + + true + The last recorded error is an underrun on a read + 0x1 + + + + + DBE + Destination Bus Error + 3 + 1 + read-write + oneToClear + + + false + No destination bus error + 0 + + + true + The last recorded error is bus error on a write + 0x1 + + + + + DONE + DMA Packet Transfer Complete + 4 + 1 + read-write + oneToClear + + + false + Packet transfer not done; CCNT less than TCNT + 0 + + + true + Packet transfer is done; TCNT 32-bit words transferred + 0x1 + + + + + + + WMC + Watermark Configuration Register + 0x8 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + WMRK + Watermark + 0 + 4 + read-write + + + CNT + FIFO Count + 16 + 5 + read-only + + + SIZE + FIFO size + 24 + 5 + read-only + + + + + RDATA + FIFO Read Data Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + FIFO Data + 0 + 32 + read-only + + + + + DADDR + DMA Destination Address Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + XCR + DMA Transfer Count Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCNT + Total Transfer Count + 0 + 16 + read-write + + + CCNT + Current Transfer Count + 16 + 16 + read-only + + + + + + + PORTA + PORT + PORT + 0x40042000 + + 0 + 0xDC + registers + + + PORTA_EFT + 67 + + + + VERID + Version ID + 0 + 32 + read-only + 0x2000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + feature0 + Basic implementation + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + GPCLR + Global Pin Control Low + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE0 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + GPCHR + Global Pin Control High + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE16 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE17 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE18 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE19 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE20 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE21 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE22 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE23 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE24 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE25 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE26 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE27 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE28 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE29 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE30 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE31 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + CONFIG + Configuration + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RANGE + Port Voltage Range + 0 + 1 + read-write + + + range0 + 1.71 V-3.6 V + 0 + + + range1 + 2.70 V-3.6 V + 0x1 + + + + + + + EDFR + EFT Detect Flag + 0x40 + 32 + read-only + 0 + 0 + + + EDF0 + EFT Detect Flag + 0 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF1 + EFT Detect Flag + 1 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF2 + EFT Detect Flag + 2 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF3 + EFT Detect Flag + 3 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF4 + EFT Detect Flag + 4 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF5 + EFT Detect Flag + 5 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + Reserved6 + Reserved + 6 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved8 + Reserved + 8 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved9 + Reserved + 9 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + EDF16 + EFT Detect Flag + 16 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF17 + EFT Detect Flag + 17 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF18 + EFT Detect Flag + 18 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF19 + EFT Detect Flag + 19 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF20 + EFT Detect Flag + 20 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF21 + EFT Detect Flag + 21 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF22 + EFT Detect Flag + 22 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDIER + EFT Detect Interrupt Enable + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDIE0 + EFT Detect Interrupt Enable + 0 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE1 + EFT Detect Interrupt Enable + 1 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE2 + EFT Detect Interrupt Enable + 2 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE3 + EFT Detect Interrupt Enable + 3 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE4 + EFT Detect Interrupt Enable + 4 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE5 + EFT Detect Interrupt Enable + 5 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + Reserved6 + Reserved + 6 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved8 + Reserved + 8 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved9 + Reserved + 9 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + EDIE16 + EFT Detect Interrupt Enable + 16 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE17 + EFT Detect Interrupt Enable + 17 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE18 + EFT Detect Interrupt Enable + 18 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE19 + EFT Detect Interrupt Enable + 19 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE20 + EFT Detect Interrupt Enable + 20 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE21 + EFT Detect Interrupt Enable + 21 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE22 + EFT Detect Interrupt Enable + 22 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDCR + EFT Detect Clear + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDHC + EFT Detect High Clear + 0 + 1 + read-write + + + edhc0 + Does not clear + 0 + + + edhc1 + Clears + 0x1 + + + + + EDLC + EFT Detect Low Clear + 1 + 1 + read-write + + + edlc0 + Does not clear + 0 + + + edlc1 + Clears + 0x1 + + + + + + + PCR0 + Pin Control 0 + 0x80 + 32 + read-write + 0x703 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR1 + Pin Control 1 + 0x84 + 32 + read-write + 0x702 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR2 + Pin Control 2 + 0x88 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR3 + Pin Control 3 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR4 + Pin Control 4 + 0x90 + 32 + read-write + 0x702 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR5 + Pin Control 5 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR16 + Pin Control 16 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR17 + Pin Control 17 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR18 + Pin Control 18 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR19 + Pin Control 19 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR20 + Pin Control 20 + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR21 + Pin Control 21 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR22 + Pin Control 22 + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + + + PORTB + PORT + PORT + 0x40043000 + + 0 + 0x98 + registers + + + PORTB_EFT + 68 + + + + VERID + Version ID + 0 + 32 + read-only + 0x2000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + feature0 + Basic implementation + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + GPCLR + Global Pin Control Low + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE0 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + GPCHR + Global Pin Control High + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE16 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE17 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE18 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE19 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE20 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE21 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE22 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE23 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE24 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE25 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE26 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE27 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE28 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE29 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE30 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE31 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + CONFIG + Configuration + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RANGE + Port Voltage Range + 0 + 1 + read-write + + + range0 + 1.71 V-3.6 V + 0 + + + range1 + 2.70 V-3.6 V + 0x1 + + + + + + + EDFR + EFT Detect Flag + 0x40 + 32 + read-only + 0 + 0 + + + EDF0 + EFT Detect Flag + 0 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF1 + EFT Detect Flag + 1 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF2 + EFT Detect Flag + 2 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF3 + EFT Detect Flag + 3 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF4 + EFT Detect Flag + 4 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF5 + EFT Detect Flag + 5 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + Reserved6 + Reserved + 6 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved8 + Reserved + 8 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved9 + Reserved + 9 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved16 + Reserved + 16 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved17 + Reserved + 17 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved18 + Reserved + 18 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved19 + Reserved + 19 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved20 + Reserved + 20 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved21 + Reserved + 21 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved22 + Reserved + 22 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDIER + EFT Detect Interrupt Enable + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDIE0 + EFT Detect Interrupt Enable + 0 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE1 + EFT Detect Interrupt Enable + 1 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE2 + EFT Detect Interrupt Enable + 2 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE3 + EFT Detect Interrupt Enable + 3 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE4 + EFT Detect Interrupt Enable + 4 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE5 + EFT Detect Interrupt Enable + 5 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + Reserved6 + Reserved + 6 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved8 + Reserved + 8 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved9 + Reserved + 9 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved16 + Reserved + 16 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved17 + Reserved + 17 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved18 + Reserved + 18 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved19 + Reserved + 19 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved20 + Reserved + 20 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved21 + Reserved + 21 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved22 + Reserved + 22 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDCR + EFT Detect Clear + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDHC + EFT Detect High Clear + 0 + 1 + read-write + + + edhc0 + Does not clear + 0 + + + edhc1 + Clears + 0x1 + + + + + EDLC + EFT Detect Low Clear + 1 + 1 + read-write + + + edlc0 + Does not clear + 0 + + + edlc1 + Clears + 0x1 + + + + + + + PCR0 + Pin Control 0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR1 + Pin Control 1 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR2 + Pin Control 2 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR3 + Pin Control 3 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR4 + Pin Control 4 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR5 + Pin Control 5 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + mux1011 + Alternative 11 (chip-specific) + 0xB + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + + + PORTC + PORT + PORT + 0x40044000 + + 0 + 0xA8 + registers + + + PORTC_EFT + 69 + + + + VERID + Version ID + 0 + 32 + read-only + 0x2000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + feature0 + Basic implementation + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + GPCLR + Global Pin Control Low + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE0 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + GPCHR + Global Pin Control High + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE16 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE17 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE18 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE19 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE20 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE21 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE22 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE23 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE24 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE25 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE26 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE27 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE28 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE29 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE30 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE31 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + CONFIG + Configuration + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RANGE + Port Voltage Range + 0 + 1 + read-write + + + range0 + 1.71 V-3.6 V + 0 + + + range1 + 2.70 V-3.6 V + 0x1 + + + + + + + EDFR + EFT Detect Flag + 0x40 + 32 + read-only + 0 + 0 + + + EDF0 + EFT Detect Flag + 0 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF1 + EFT Detect Flag + 1 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF2 + EFT Detect Flag + 2 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF3 + EFT Detect Flag + 3 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF4 + EFT Detect Flag + 4 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF5 + EFT Detect Flag + 5 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF6 + EFT Detect Flag + 6 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + EDF8 + EFT Detect Flag + 8 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF9 + EFT Detect Flag + 9 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved16 + Reserved + 16 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved17 + Reserved + 17 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved18 + Reserved + 18 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved19 + Reserved + 19 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved20 + Reserved + 20 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved21 + Reserved + 21 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved22 + Reserved + 22 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDIER + EFT Detect Interrupt Enable + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDIE0 + EFT Detect Interrupt Enable + 0 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE1 + EFT Detect Interrupt Enable + 1 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE2 + EFT Detect Interrupt Enable + 2 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE3 + EFT Detect Interrupt Enable + 3 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE4 + EFT Detect Interrupt Enable + 4 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE5 + EFT Detect Interrupt Enable + 5 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE6 + EFT Detect Interrupt Enable + 6 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + EDIE8 + EFT Detect Interrupt Enable + 8 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE9 + EFT Detect Interrupt Enable + 9 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved16 + Reserved + 16 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved17 + Reserved + 17 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved18 + Reserved + 18 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved19 + Reserved + 19 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved20 + Reserved + 20 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved21 + Reserved + 21 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved22 + Reserved + 22 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDCR + EFT Detect Clear + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDHC + EFT Detect High Clear + 0 + 1 + read-write + + + edhc0 + Does not clear + 0 + + + edhc1 + Clears + 0x1 + + + + + EDLC + EFT Detect Low Clear + 1 + 1 + read-write + + + edlc0 + Does not clear + 0 + + + edlc1 + Clears + 0x1 + + + + + + + PCR0 + Pin Control 0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR1 + Pin Control 1 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR2 + Pin Control 2 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR3 + Pin Control 3 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR4 + Pin Control 4 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR5 + Pin Control 5 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + DSE1 + Drive Strength Enable + 7 + 1 + read-write + + + dse10 + Normal + 0 + + + dse11 + Double + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR6 + Pin Control 6 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR7 + Pin Control 7 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR8 + Pin Control 8 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR9 + Pin Control 9 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + SRE + Slew Rate Enable + 3 + 1 + read-write + + + sre0 + Fast + 0 + + + sre1 + Slow + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + dse0 + Low + 0 + + + dse1 + High + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + mux1010 + Alternative 10 (chip-specific) + 0xA + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + + + PORTD + PORT + PORT + 0x40045000 + + 0 + 0x9C + registers + + + PORTD_EFT + 70 + + + + VERID + Version ID + 0 + 32 + read-only + 0x2000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + feature0 + Basic implementation + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + GPCLR + Global Pin Control Low + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE0 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE1 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE2 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE3 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE4 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE5 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE6 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE7 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE8 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE9 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE10 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE11 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE12 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE13 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE14 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE15 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + GPCHR + Global Pin Control High + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE16 + Global Pin Write Enable + 16 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE17 + Global Pin Write Enable + 17 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE18 + Global Pin Write Enable + 18 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE19 + Global Pin Write Enable + 19 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE20 + Global Pin Write Enable + 20 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE21 + Global Pin Write Enable + 21 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE22 + Global Pin Write Enable + 22 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE23 + Global Pin Write Enable + 23 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE24 + Global Pin Write Enable + 24 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE25 + Global Pin Write Enable + 25 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE26 + Global Pin Write Enable + 26 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE27 + Global Pin Write Enable + 27 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE28 + Global Pin Write Enable + 28 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE29 + Global Pin Write Enable + 29 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE30 + Global Pin Write Enable + 30 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + GPWE31 + Global Pin Write Enable + 31 + 1 + read-write + + + gpwe0 + Not updated + 0 + + + gpwe1 + Updated + 0x1 + + + + + + + CONFIG + Configuration + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RANGE + Port Voltage Range + 0 + 1 + read-write + + + range0 + 1.71 V-3.6 V + 0 + + + range1 + 2.70 V-3.6 V + 0x1 + + + + + + + EDFR + EFT Detect Flag + 0x40 + 32 + read-only + 0 + 0 + + + EDF0 + EFT Detect Flag + 0 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF1 + EFT Detect Flag + 1 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF2 + EFT Detect Flag + 2 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF3 + EFT Detect Flag + 3 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF4 + EFT Detect Flag + 4 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF5 + EFT Detect Flag + 5 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + EDF6 + EFT Detect Flag + 6 + 1 + read-only + + + edie0 + No EFT event detected + 0 + + + edie1 + High or/and low EFT event detected + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved8 + Reserved + 8 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved9 + Reserved + 9 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved16 + Reserved + 16 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved17 + Reserved + 17 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved18 + Reserved + 18 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved19 + Reserved + 19 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved20 + Reserved + 20 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved21 + Reserved + 21 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved22 + Reserved + 22 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDIER + EFT Detect Interrupt Enable + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDIE0 + EFT Detect Interrupt Enable + 0 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE1 + EFT Detect Interrupt Enable + 1 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE2 + EFT Detect Interrupt Enable + 2 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE3 + EFT Detect Interrupt Enable + 3 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE4 + EFT Detect Interrupt Enable + 4 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE5 + EFT Detect Interrupt Enable + 5 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + EDIE6 + EFT Detect Interrupt Enable + 6 + 1 + read-write + + + edie0 + Interrupt not generated upon detection of the EFT event + 0 + + + edie1 + Interrupt generated upon detection of the EFT event + 0x1 + + + + + Reserved7 + Reserved + 7 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved8 + Reserved + 8 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved9 + Reserved + 9 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved10 + Reserved + 10 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved11 + Reserved + 11 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved12 + Reserved + 12 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved13 + Reserved + 13 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved14 + Reserved + 14 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved15 + Reserved + 15 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved16 + Reserved + 16 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved17 + Reserved + 17 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved18 + Reserved + 18 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved19 + Reserved + 19 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved20 + Reserved + 20 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved21 + Reserved + 21 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved22 + Reserved + 22 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved23 + Reserved + 23 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved24 + Reserved + 24 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved25 + Reserved + 25 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved26 + Reserved + 26 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved27 + Reserved + 27 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved28 + Reserved + 28 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved29 + Reserved + 29 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved30 + Reserved + 30 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + Reserved31 + Reserved + 31 + 1 + read-only + + + edie0 + Not supported + 0 + + + edie1 + Not supported + 0x1 + + + + + + + EDCR + EFT Detect Clear + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDHC + EFT Detect High Clear + 0 + 1 + read-write + + + edhc0 + Does not clear + 0 + + + edhc1 + Clears + 0x1 + + + + + EDLC + EFT Detect Low Clear + 1 + 1 + read-write + + + edlc0 + Does not clear + 0 + + + edlc1 + Clears + 0x1 + + + + + + + PCR0 + Pin Control 0 + 0x80 + 32 + read-write + 0x333 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR1 + Pin Control 1 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR2 + Pin Control 2 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR3 + Pin Control 3 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + mux1000 + Alternative 8 (chip-specific) + 0x8 + + + mux1001 + Alternative 9 (chip-specific) + 0x9 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR4 + Pin Control 4 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR5 + Pin Control 5 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + PCR6 + Pin Control 6 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + ps0 + Enables internal pulldown resistor + 0 + + + ps1 + Enables internal pullup resistor + 0x1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + pe0 + Disables + 0 + + + pe1 + Enables + 0x1 + + + + + PV + Pull Value + 2 + 1 + read-write + + + pv0 + Low + 0 + + + pv1 + High + 0x1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + pfe0 + Disables + 0 + + + pfe1 + Enables + 0x1 + + + + + ODE + Open Drain Enable + 5 + 1 + read-write + + + ode0 + Disables + 0 + + + ode1 + Enables + 0x1 + + + + + MUX + Pin Multiplex Control + 8 + 4 + read-write + + + mux0 + Pin disabled (analog) + 0 + + + mux1 + Alternative 1 (GPIO) + 0x1 + + + mux10 + Alternative 2 (chip-specific) + 0x2 + + + mux11 + Alternative 3 (chip-specific) + 0x3 + + + mux100 + Alternative 4 (chip-specific) + 0x4 + + + mux101 + Alternative 5 (chip-specific) + 0x5 + + + mux110 + Alternative 6 (chip-specific) + 0x6 + + + mux111 + Alternative 7 (chip-specific) + 0x7 + + + + + LK + Lock Register + 15 + 1 + read-write + + + lk0 + Locks + 0 + + + lk1 + Does not lock + 0x1 + + + + + + + + + GPIOD + GPIO + GPIO + GPIO + 0x40046000 + + 0 + 0x128 + registers + + + GPIOD_INT0 + 65 + + + GPIOD_INT1 + 66 + + + + VERID + Version ID + 0 + 32 + read-only + 0x2010001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + feature0 + Basic implementation. + 0 + + + feature1 + Protection registers implemented. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + IRQNUM + Interrupt Number + 0 + 4 + read-only + + + + + LOCK + Lock + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PCNS + Lock PCNS + 0 + 1 + read-write + + + pcns0 + PCNS register is writable by software in Secure-Privilege state. + 0 + + + pcns1 + PCNS register is not writable until the next reset. + 0x1 + + + + + ICNS + Lock ICNS + 1 + 1 + read-write + + + icns0 + ICNS register is writable by software in Secure-Privilege state. + 0 + + + icns1 + ICNS register is not writable until the next reset. + 0x1 + + + + + PCNP + Lock PCNP + 2 + 1 + read-write + + + pcnp0 + PCNP register is writable by software in Secure-Privilege state. + 0 + + + pcnp1 + PCNP register is not writable until the next reset. + 0x1 + + + + + ICNP + Lock ICNP + 3 + 1 + read-write + + + icnp0 + ICNP register is writable by software in Secure-Privilege state. + 0 + + + icnp1 + ICNP register is not writable until the next reset. + 0x1 + + + + + + + PCNS + Pin Control Non-Secure + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSE0 + Non-Secure Enable + 0 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE1 + Non-Secure Enable + 1 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE2 + Non-Secure Enable + 2 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE3 + Non-Secure Enable + 3 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE4 + Non-Secure Enable + 4 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE5 + Non-Secure Enable + 5 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE6 + Non-Secure Enable + 6 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE7 + Non-Secure Enable + 7 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE8 + Non-Secure Enable + 8 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE9 + Non-Secure Enable + 9 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE10 + Non-Secure Enable + 10 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE11 + Non-Secure Enable + 11 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE12 + Non-Secure Enable + 12 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE13 + Non-Secure Enable + 13 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE14 + Non-Secure Enable + 14 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE15 + Non-Secure Enable + 15 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE16 + Non-Secure Enable + 16 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE17 + Non-Secure Enable + 17 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE18 + Non-Secure Enable + 18 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE19 + Non-Secure Enable + 19 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE20 + Non-Secure Enable + 20 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE21 + Non-Secure Enable + 21 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE22 + Non-Secure Enable + 22 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE23 + Non-Secure Enable + 23 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE24 + Non-Secure Enable + 24 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE25 + Non-Secure Enable + 25 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE26 + Non-Secure Enable + 26 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE27 + Non-Secure Enable + 27 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE28 + Non-Secure Enable + 28 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE29 + Non-Secure Enable + 29 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE30 + Non-Secure Enable + 30 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + NSE31 + Non-Secure Enable + 31 + 1 + read-write + + + nse0 + The pin is configured for Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed by software in Non-Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0 + + + nse1 + The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are accessed by software in Secure state, all bits in the registers related to that pin are read zero and write ignored. + 0x1 + + + + + + + ICNS + Interrupt Control Non-Secure + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSE0 + Non-Secure Enable + 0 + 1 + read-write + + + nse0 + The interrupt, output trigger or DMA request is configured for Secure access. Only software in Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. + 0 + + + nse1 + The interrupt, output trigger or DMA request is configured for Non-Secure access. Only software in Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. + 0x1 + + + + + NSE1 + Non-Secure Enable + 1 + 1 + read-write + + + nse0 + The interrupt, output trigger or DMA request is configured for Secure access. Only software in Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. + 0 + + + nse1 + The interrupt, output trigger or DMA request is configured for Non-Secure access. Only software in Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. + 0x1 + + + + + + + PCNP + Pin Control Non-Privilege + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + NPE0 + Non-Privilege Enable + 0 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE1 + Non-Privilege Enable + 1 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE2 + Non-Privilege Enable + 2 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE3 + Non-Privilege Enable + 3 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE4 + Non-Privilege Enable + 4 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE5 + Non-Privilege Enable + 5 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE6 + Non-Privilege Enable + 6 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE7 + Non-Privilege Enable + 7 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE8 + Non-Privilege Enable + 8 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE9 + Non-Privilege Enable + 9 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE10 + Non-Privilege Enable + 10 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE11 + Non-Privilege Enable + 11 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE12 + Non-Privilege Enable + 12 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE13 + Non-Privilege Enable + 13 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE14 + Non-Privilege Enable + 14 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE15 + Non-Privilege Enable + 15 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE16 + Non-Privilege Enable + 16 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE17 + Non-Privilege Enable + 17 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE18 + Non-Privilege Enable + 18 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE19 + Non-Privilege Enable + 19 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE20 + Non-Privilege Enable + 20 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE21 + Non-Privilege Enable + 21 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE22 + Non-Privilege Enable + 22 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE23 + Non-Privilege Enable + 23 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE24 + Non-Privilege Enable + 24 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE25 + Non-Privilege Enable + 25 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE26 + Non-Privilege Enable + 26 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE27 + Non-Privilege Enable + 27 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE28 + Non-Privilege Enable + 28 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE29 + Non-Privilege Enable + 29 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE30 + Non-Privilege Enable + 30 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + NPE31 + Non-Privilege Enable + 31 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable but write ignored. + 0 + + + npe1 + The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers is allowed by software in both Privilege or Non-Privilege state. + 0x1 + + + + + + + ICNP + Interrupt Control Non-Privilege + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + NPE0 + Non-Privilege Enable + 0 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to use the corresponding interrupt/trigger output/DMA request. + 0 + + + npe1 + The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to use the corresponding interrupt/trigger output/DMA request. + 0x1 + + + + + NPE1 + Non-Privilege Enable + 1 + 1 + read-write + + + npe0 + The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to use the corresponding interrupt/trigger output/DMA request. + 0 + + + npe1 + The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to use the corresponding interrupt/trigger output/DMA request. + 0x1 + + + + + + + PDOR + Port Data Output Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO0 + Port Data Output + 0 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + PDO31 + Port Data Output + 31 + 1 + read-write + + + pdo0 + Logic level 0 is driven on pin, if the pin is configured for general-purpose output. + 0 + + + pdo1 + Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + 0x1 + + + + + + + PSOR + Port Set Output Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO0 + Port Set Output + 0 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO1 + Port Set Output + 1 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO2 + Port Set Output + 2 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO3 + Port Set Output + 3 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO4 + Port Set Output + 4 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO5 + Port Set Output + 5 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO6 + Port Set Output + 6 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO7 + Port Set Output + 7 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO8 + Port Set Output + 8 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO9 + Port Set Output + 9 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO10 + Port Set Output + 10 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO11 + Port Set Output + 11 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO12 + Port Set Output + 12 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO13 + Port Set Output + 13 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO14 + Port Set Output + 14 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO15 + Port Set Output + 15 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO16 + Port Set Output + 16 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO17 + Port Set Output + 17 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO18 + Port Set Output + 18 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO19 + Port Set Output + 19 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO20 + Port Set Output + 20 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO21 + Port Set Output + 21 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO22 + Port Set Output + 22 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO23 + Port Set Output + 23 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO24 + Port Set Output + 24 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO25 + Port Set Output + 25 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO26 + Port Set Output + 26 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO27 + Port Set Output + 27 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO28 + Port Set Output + 28 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO29 + Port Set Output + 29 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO30 + Port Set Output + 30 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + PTSO31 + Port Set Output + 31 + 1 + read-write + + + ptso0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptso1 + Corresponding field of PDOR[PDOn] is set to logic 1. + 0x1 + + + + + + + PCOR + Port Clear Output Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO0 + Port Clear Output + 0 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + PTCO31 + Port Clear Output + 31 + 1 + read-write + + + ptco0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptco1 + Corresponding field of PDOR[PDOn] is cleared to logic 0. + 0x1 + + + + + + + PTOR + Port Toggle Output Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO0 + Port Toggle Output + 0 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 + read-write + + + ptto0 + Corresponding field of PDOR[PDOn] does not change. + 0 + + + ptto1 + Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + 0x1 + + + + + + + PDIR + Port Data Input Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI0 + Port Data Input + 0 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + PDI31 + Port Data Input + 31 + 1 + read-only + + + pdi0 + Pin logic level is logic 0, or is not configured for use by digital function. + 0 + + + pdi1 + Pin logic level is logic 1. + 0x1 + + + + + + + PDDR + Port Data Direction Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD0 + Port Data Direction + 0 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + PDD31 + Port Data Direction + 31 + 1 + read-write + + + pdd0 + Pin is configured as general-purpose input for the GPIO function. + 0 + + + pdd1 + Pin is configured as general-purpose output for the GPIO function. + 0x1 + + + + + + + PIDR + Port Input Disable Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + PID0 + Port Input Disable + 0 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID1 + Port Input Disable + 1 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID2 + Port Input Disable + 2 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID3 + Port Input Disable + 3 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID4 + Port Input Disable + 4 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID5 + Port Input Disable + 5 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID6 + Port Input Disable + 6 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID7 + Port Input Disable + 7 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID8 + Port Input Disable + 8 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID9 + Port Input Disable + 9 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID10 + Port Input Disable + 10 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID11 + Port Input Disable + 11 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID12 + Port Input Disable + 12 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID13 + Port Input Disable + 13 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID14 + Port Input Disable + 14 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID15 + Port Input Disable + 15 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID16 + Port Input Disable + 16 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID17 + Port Input Disable + 17 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID18 + Port Input Disable + 18 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID19 + Port Input Disable + 19 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID20 + Port Input Disable + 20 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID21 + Port Input Disable + 21 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID22 + Port Input Disable + 22 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID23 + Port Input Disable + 23 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID24 + Port Input Disable + 24 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID25 + Port Input Disable + 25 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID26 + Port Input Disable + 26 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID27 + Port Input Disable + 27 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID28 + Port Input Disable + 28 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID29 + Port Input Disable + 29 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID30 + Port Input Disable + 30 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + PID31 + Port Input Disable + 31 + 1 + read-write + + + pid0 + Pin is configured for general-purpose input provided, the pin is configured for any digital function. + 0 + + + pid1 + Pin is disabled for general-purpose input. + 0x1 + + + + + + + 32 + 0x1 + PDR[%s] + Pin Data Register a + 0x60 + 8 + read-write + 0 + 0xFF + + + PD + Pin Data (input and output) + 0 + 1 + read-write + + + pd0 + Pin logic level is logic zero or not configured for use by digital function. + 0 + + + pd1 + Pin logic level is logic one. + 0x1 + + + + + + + 32 + 0x4 + ICR[%s] + Interrupt Control Register index + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + irqc0 + Interrupt Status Flag (ISF) is disabled. + 0 + + + irqc1 + ISF flag and DMA request on rising edge. + 0x1 + + + irqc2 + ISF flag and DMA request on falling edge. + 0x2 + + + irqc3 + ISF flag and DMA request on either edge. + 0x3 + + + irqc5 + ISF flag sets on rising edge. + 0x5 + + + irqc6 + ISF flag sets on falling edge. + 0x6 + + + irqc7 + ISF flag sets on either edge. + 0x7 + + + irqc8 + ISF flag and Interrupt when logic 0. + 0x8 + + + irqc9 + ISF flag and Interrupt on rising-edge. + 0x9 + + + irqc10 + ISF flag and Interrupt on falling-edge. + 0xA + + + irqc11 + ISF flag and Interrupt on either edge. + 0xB + + + irqc12 + ISF flag and Interrupt when logic 1. + 0xC + + + irqc13 + Enable active high trigger output, ISF flag on rising edge. Pin state is ORed with other enabled triggers to generate the output trigger, for use by other peripherals. + 0xD + + + irqc14 + Enable active low trigger output, ISF flag on falling edge. Pin state is inverted and ORed with other enabled triggers to generate the output trigger, for use by other peripherals. + 0xE + + + + + IRQS + Interrupt Select + 20 + 1 + read-write + + + irqs0 + Interrupt/trigger output/DMA request 0. + 0 + + + irqs1 + Interrupt/trigger output/DMA request 1. + 0x1 + + + + + LK + Lock Register + 23 + 1 + read-write + + + lk0 + Interrupt configuration by ICR[23:0] is not locked and can be updated. + 0 + + + lk1 + Interrupt configuration by ICR[23:0] is locked and cannot be updated until next system reset. + 0x1 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected. + 0 + + + isf1 + Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + + + GICLR + Global Interrupt Control Low Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE0 + Global Interrupt Write Enable + 0 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE1 + Global Interrupt Write Enable + 1 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE2 + Global Interrupt Write Enable + 2 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE3 + Global Interrupt Write Enable + 3 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE4 + Global Interrupt Write Enable + 4 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE5 + Global Interrupt Write Enable + 5 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE6 + Global Interrupt Write Enable + 6 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE7 + Global Interrupt Write Enable + 7 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE8 + Global Interrupt Write Enable + 8 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE9 + Global Interrupt Write Enable + 9 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE10 + Global Interrupt Write Enable + 10 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE11 + Global Interrupt Write Enable + 11 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE12 + Global Interrupt Write Enable + 12 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE13 + Global Interrupt Write Enable + 13 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE14 + Global Interrupt Write Enable + 14 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE15 + Global Interrupt Write Enable + 15 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + GICHR + Global Interrupt Control High Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE16 + Global Interrupt Write Enable + 0 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE17 + Global Interrupt Write Enable + 1 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE18 + Global Interrupt Write Enable + 2 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE19 + Global Interrupt Write Enable + 3 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE20 + Global Interrupt Write Enable + 4 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE21 + Global Interrupt Write Enable + 5 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE22 + Global Interrupt Write Enable + 6 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE23 + Global Interrupt Write Enable + 7 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE24 + Global Interrupt Write Enable + 8 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE25 + Global Interrupt Write Enable + 9 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE26 + Global Interrupt Write Enable + 10 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE27 + Global Interrupt Write Enable + 11 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE28 + Global Interrupt Write Enable + 12 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE29 + Global Interrupt Write Enable + 13 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE30 + Global Interrupt Write Enable + 14 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWE31 + Global Interrupt Write Enable + 15 + 1 + read-write + + + giwe0 + Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. + 0 + + + giwe1 + Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + 0x1 + + + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + 2 + 0x4 + ISFR[%s] + Interrupt Status Flag Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + ISF0 + Interrupt Status Flag + 0 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF1 + Interrupt Status Flag + 1 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF2 + Interrupt Status Flag + 2 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF3 + Interrupt Status Flag + 3 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF4 + Interrupt Status Flag + 4 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF5 + Interrupt Status Flag + 5 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF6 + Interrupt Status Flag + 6 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF7 + Interrupt Status Flag + 7 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF8 + Interrupt Status Flag + 8 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF9 + Interrupt Status Flag + 9 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF10 + Interrupt Status Flag + 10 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF11 + Interrupt Status Flag + 11 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF12 + Interrupt Status Flag + 12 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF13 + Interrupt Status Flag + 13 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF14 + Interrupt Status Flag + 14 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF15 + Interrupt Status Flag + 15 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF16 + Interrupt Status Flag + 16 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF17 + Interrupt Status Flag + 17 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF18 + Interrupt Status Flag + 18 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF19 + Interrupt Status Flag + 19 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF20 + Interrupt Status Flag + 20 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF21 + Interrupt Status Flag + 21 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF22 + Interrupt Status Flag + 22 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF23 + Interrupt Status Flag + 23 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF24 + Interrupt Status Flag + 24 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF25 + Interrupt Status Flag + 25 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF26 + Interrupt Status Flag + 26 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF27 + Interrupt Status Flag + 27 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF28 + Interrupt Status Flag + 28 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF29 + Interrupt Status Flag + 29 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF30 + Interrupt Status Flag + 30 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + ISF31 + Interrupt Status Flag + 31 + 1 + read-write + oneToClear + + + isf0 + Configured interrupt is not detected on the pin of the same number. + 0 + + + isf1 + Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + 0x1 + + + + + + + + + GPIOA + GPIO + GPIO + 0x48010000 + + 0 + 0x128 + registers + + + GPIOA_INT0 + 59 + + + GPIOA_INT1 + 60 + + + + GPIOB + GPIO + GPIO + 0x48020000 + + 0 + 0x128 + registers + + + GPIOB_INT0 + 61 + + + GPIOB_INT1 + 62 + + + + GPIOC + GPIO + GPIO + 0x48030000 + + 0 + 0x128 + registers + + + GPIOC_INT0 + 63 + + + GPIOC_INT1 + 64 + + + + ADC0 + ADC + ADC + 0x40047000 + + 0 + 0x584 + registers + + + ADC0 + 71 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x2002C0B + 0xFFFFFFFF + + + RES + Resolution + 0 + 1 + read-only + + + MAX_13_bit + Up to 13-bit differential or 12-bit single-ended resolution supported. + 0 + + + MAX_16_bit + Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] available for selecting the resolution of conversions for the associated command. + 0x1 + + + + + DIFFEN + Differential Supported + 1 + 1 + read-only + + + DIFFERENTIAL_NOT_SUPPORTED + Not supported + 0 + + + DIFFERENTIAL_SUPPORTED + Supported. CMDLn[CTYPE] controls fields implemented. + 0x1 + + + + + MVI + Multiple Vref Implemented + 3 + 1 + read-only + + + MULTIPLE_REF_NOT_SUPPORTED + Single VREFH input supported. + 0 + + + MULTIPLE_REF_SUPPORTED + Multiple VREFH inputs supported. + 0x1 + + + + + CSW + Channel Scale Width + 4 + 3 + read-only + + + CSCALE_NOT_SUPPORTED + Not supported. + 0 + + + BIT_WIDTH_1 + Supported with one-bit CSCALE control field. + 0x1 + + + BIT_WIDTH_6 + Supported with six-bit CSCALE control field. + 0x6 + + + + + VR1RNGI + Voltage Reference 1 Range Control Bit Implemented + 8 + 1 + read-only + + + REF1_FIXED_VOLTAGE_RANGE + Range control not required. + 0 + + + REF1_SELECTABLE_VOLTAGE_RANGE + Range control required. + 0x1 + + + + + IADCKI + Internal ADC Clock Implemented + 9 + 1 + read-only + + + INTERNAL_CLK_NOT_AVAILABLE + Not implemented + 0 + + + INTERNAL_CLK_AVAILABLE + Implemented + 0x1 + + + + + CALOFSI + Calibration Function Implemented + 10 + 1 + read-only + + + CAL_FUNCTION_NOT_AVAILABLE + Not implemented + 0 + + + CAL_FUNCTION_AVAILABLE + Implemented + 0x1 + + + + + NUM_SEC + Number of Single-Ended Outputs Supported + 11 + 1 + read-only + + + SINGLE_CONVERTOR + One + 0 + + + DUAL_CONVERTOR + Two + 0x1 + + + + + NUM_FIFO + Number of FIFOs + 12 + 3 + read-only + + + NO_FIFO_IMPLEMENTED + N/A + 0 + + + CNT_1 + One + 0x1 + + + CNT_2 + Two + 0x2 + + + CNT_3 + Three + 0x3 + + + CNT_4 + Four + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0xF0F1004 + 0xFFFFFFFF + + + TRIG_NUM + Trigger Number + 0 + 8 + read-only + + + FIFOSIZE + Result FIFO Depth + 8 + 8 + read-only + + + ENTRIES_2 + 2 + 0x1 + + + ENTRIES_4 + 4 + 0x4 + + + ENTRIES_8 + 8 + 0x8 + + + ENTRIES_16 + 16 + 0x10 + + + ENTRIES_32 + 32 + 0x20 + + + ENTRIES_64 + 64 + 0x40 + + + + + CV_NUM + Compare Value Number + 16 + 8 + read-only + + + CMD_NUM + Command Buffer Number + 24 + 8 + read-only + + + + + CTRL + Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCEN + ADC Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RELEASED_FROM_RESET + ADC logic is not reset. + 0 + + + HELD_IN_RESET + ADC logic is reset. + 0x1 + + + + + DOZEN + Doze Enable + 2 + 1 + read-write + + + ENABLED + ADC is enabled in low-power mode. + 0 + + + DISABLED + ADC is disabled in low-power mode. + 0x1 + + + + + CAL_REQ + Auto-Calibration Request + 3 + 1 + read-write + + + NO_CALIBRATION_REQUEST + No request made. + 0 + + + CALIBRATION_REQUEST_PENDING + Request has been made. + 0x1 + + + + + CALOFS + Offset Calibration Request + 4 + 1 + read-write + + + NO_ACTIVE_OFFSET_CALIBRATION_REQUEST + Calibration function disabled + 0 + + + OFFSET_CALIBRATION_REQUEST_PENDING + Request for offset calibration function + 0x1 + + + + + RSTFIFO0 + Reset FIFO 0 + 8 + 1 + read-write + + + NO_ACTION + No effect. + 0 + + + TRIGGER_RESET + FIFO 0 is reset. + 0x1 + + + + + RSTFIFO1 + Reset FIFO 1 + 9 + 1 + read-write + + + NO_ACTION + No effect. + 0 + + + TRIGGER_RESET + FIFO 1 is reset. + 0x1 + + + + + CAL_AVGS + Auto-Calibration Averages + 16 + 3 + read-write + + + NO_AVERAGE + Single conversion. + 0 + + + AVERAGE_2 + 2 conversions averaged. + 0x1 + + + AVERAGE_4 + 4 conversions averaged. + 0x2 + + + AVERAGE_8 + 8 conversions averaged. + 0x3 + + + AVERAGE_16 + 16 conversions averaged. + 0x4 + + + AVERAGE_32 + 32 conversions averaged. + 0x5 + + + AVERAGE_64 + 64 conversions averaged. + 0x6 + + + AVERAGE_128 + 128 conversions averaged. + 0x7 + + + + + + + STAT + Status Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDY0 + Result FIFO 0 Ready Flag + 0 + 1 + read-only + + + BELOW_THRESHOLD + Not above watermark + 0 + + + ABOVE_THRESHOLD + Above watermark + 0x1 + + + + + FOF0 + Result FIFO 0 Overflow Flag + 1 + 1 + read-write + oneToClear + + + NO_OVERFLOW + No result FIFO 0 overflow has occurred since the last time that the flag was cleared. + 0 + + + OVERFLOW_DETECTED + At least one result FIFO 0 overflow has occurred since the last time that the flag was cleared. + 0x1 + + + + + RDY1 + Result FIFO1 Ready Flag + 2 + 1 + read-only + + + BELOW_THRESHOLD + Not above watermark + 0 + + + ABOVE_THRESHOLD + Above watermark + 0x1 + + + + + FOF1 + Result FIFO1 Overflow Flag + 3 + 1 + read-write + oneToClear + + + NO_OVERFLOW + No result FIFO1 overflow has occurred since the last time that the flag was cleared. + 0 + + + OVERFLOW_DETECTED + At least one result FIFO1 overflow has occurred since the last time that the flag was cleared. + 0x1 + + + + + TEXC_INT + Interrupt Flag For High-Priority Trigger Exception + 8 + 1 + read-write + oneToClear + + + NO_EXCEPTION + No trigger exceptions have occurred. + 0 + + + EXCEPTION_DETECTED + A trigger exception has occurred and is pending acknowledgment. + 0x1 + + + + + TCOMP_INT + Interrupt Flag For Trigger Completion + 9 + 1 + read-write + oneToClear + + + FLAG_CLEAR + Either IE[TCOMP_IE] = 0, or no trigger sequences have run to completion. + 0 + + + COMPLETION_DETECTED + Trigger sequence has been completed and all data is stored in the associated FIFO. + 0x1 + + + + + CAL_RDY + Calibration Ready + 10 + 1 + read-only + + + NOT_SET + Calibration is incomplete or has not been run. + 0 + + + HARDWARE_CAL_STEP_COMPLETED + ADC is calibrated. + 0x1 + + + + + ADC_ACTIVE + ADC Active + 11 + 1 + read-only + + + NOT_ACTIVE + ADC is idle. There are no pending triggers to service and no active commands are being processed. + 0 + + + BUSY + ADC is processing a conversion, running through the power-up delay, or servicing a trigger. + 0x1 + + + + + TRGACT + Trigger Active + 16 + 2 + read-only + + + TRIG_0 + Command (sequence) associated with Trigger 0 currently being executed. + 0 + + + TRIG_1 + Command (sequence) associated with Trigger 1 currently being executed. + 0x1 + + + TRIG_2 + Command (sequence) associated with Trigger 2 currently being executed. + 0x2 + + + TRIG_3 + Command (sequence) associated with Trigger 3 currently being executed. + 0x3 + + + + + CMDACT + Command Active + 24 + 4 + read-only + + + NO_COMMAND_ACTIVE + No command currently in progress. + 0 + + + COMMAND_1 + Command 1 currently being executed. + 0x1 + + + COMMAND_2 + Command 2 currently being executed. + 0x2 + + + COMMAND_x_3 + Associated command number currently being executed. + 0x3 + + + COMMAND_x_4 + Associated command number currently being executed. + 0x4 + + + COMMAND_x_5 + Associated command number currently being executed. + 0x5 + + + COMMAND_x_6 + Associated command number currently being executed. + 0x6 + + + COMMAND_x_7 + Associated command number currently being executed. + 0x7 + + + COMMAND_x_8 + Associated command number currently being executed. + 0x8 + + + COMMAND_x_9 + Associated command number currently being executed. + 0x9 + + + + + + + IE + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMIE0 + FIFO 0 Watermark Interrupt Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FOFIE0 + Result FIFO 0 Overflow Interrupt Enable + 1 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FWMIE1 + FIFO1 Watermark Interrupt Enable + 2 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FOFIE1 + Result FIFO1 Overflow Interrupt Enable + 3 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + TEXC_IE + Trigger Exception Interrupt Enable + 8 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + TCOMP_IE + Trigger Completion Interrupt Enable + 16 + 4 + read-write + + + DISABLED + All disabled + 0 + + + TRIGGER_0_COMPLETE_ENABLED + Trigger completion interrupts are enabled for trigger source 0 only. + 0x1 + + + TRIGGER_1_COMPLETE_ENABLED + Trigger completion interrupts are enabled for trigger source 1 only. + 0x2 + + + TRIGGER_x_COMPLETE_ENABLED_3 + Associated trigger completion interrupts are enabled. + 0x3 + + + TRIGGER_x_COMPLETE_ENABLED_4 + Associated trigger completion interrupts are enabled. + 0x4 + + + TRIGGER_x_COMPLETE_ENABLED_5 + Associated trigger completion interrupts are enabled. + 0x5 + + + TRIGGER_x_COMPLETE_ENABLED_6 + Associated trigger completion interrupts are enabled. + 0x6 + + + TRIGGER_x_COMPLETE_ENABLED_7 + Associated trigger completion interrupts are enabled. + 0x7 + + + TRIGGER_x_COMPLETE_ENABLED_8 + Associated trigger completion interrupts are enabled. + 0x8 + + + TRIGGER_x_COMPLETE_ENABLED_9 + Associated trigger completion interrupts are enabled. + 0x9 + + + ALL_TRIGGER_COMPLETES_ENABLED + All enabled + 0xF + + + + + + + DE + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMDE0 + FIFO 0 Watermark DMA Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FWMDE1 + FIFO1 Watermark DMA Enable + 1 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + + + CFG + Configuration Register + 0x20 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + TPRICTRL + ADC Trigger Priority Control + 0 + 2 + read-write + + + ABORT_CURRENT_ON_PRIORITY + Current conversion is aborted and the new command specified by the trigger is started. + 0 + + + FINISH_CURRENT_ON_PRIORITY + Current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is serviced. + 0x1 + + + FINISH_SEQUENCE_ON_PRIORITY + Current command is completed (averaging, looping, compare) before servicing the higher-priority trigger. + 0x2 + + + + + PWRSEL + Power Configuration Select + 4 + 2 + read-write + + + LOWEST + Low power + #0x + + + HIGHEST + High power + #1x + + + + + REFSEL + Voltage Reference Selection + 6 + 2 + read-write + + + OPTION_1 + Option 1 + 0 + + + OPTION_2 + Option 2 + 0x1 + + + OPTION_3 + Option 3 + 0x2 + + + + + TRES + Trigger Resume Enable + 8 + 1 + read-write + + + DISABLED + Not automatically resumed or restarted + 0 + + + ENABLED + Automatically resumed or restarted + 0x1 + + + + + TCMDRES + Trigger Command Resume + 9 + 1 + read-write + + + DISABLED + Trigger sequence automatically restarted. + 0 + + + ENABLED + Trigger sequence resumed from the command that was executed prior to the exception. + 0x1 + + + + + HPT_EXDI + High-Priority Trigger Exception Disable + 10 + 1 + read-write + + + ENABLED + Enabled + 0 + + + DISABLED + Disabled + 0x1 + + + + + PUDLY + Power-up Delay + 16 + 8 + read-write + + + PWREN + ADC Analog Pre-Enable + 28 + 1 + read-write + + + NOT_PRE_ENABLED + ADC analog circuits are only enabled while conversions are active. Analog startup delays affect performance. + 0 + + + PRE_ENABLED + ADC analog circuits are pre-enabled and ready to execute conversions without startup delays, at the cost of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immediately once PWREN is set. No detected triggers begin ADC operation until the power-up delay time has passed. After this initial delay expires, the analog circuits remain pre-enabled, and no additional delays are executed. + 0x1 + + + + + + + PAUSE + Pause Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PAUSEDLY + Pause Delay + 0 + 9 + read-write + + + PAUSEEN + Pause Enable + 31 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + + + SWTRIG + Software Trigger Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWT0 + Software Trigger 0 + 0 + 1 + read-write + + + NO_TRIGGER + No trigger 0 event generated. + 0 + + + INITIATE_TRIGGER_0 + Trigger 0 event generated. + 0x1 + + + + + SWT1 + Software Trigger 1 + 1 + 1 + read-write + + + NO_TRIGGER + No trigger 1 event generated. + 0 + + + INITIATE_TRIGGER_1 + Trigger 1 event generated. + 0x1 + + + + + SWT2 + Software Trigger 2 + 2 + 1 + read-write + + + NO_TRIGGER + No trigger 2 event generated. + 0 + + + INITIATE_TRIGGER_2 + Trigger 2 event generated. + 0x1 + + + + + SWT3 + Software Trigger 3 + 3 + 1 + read-write + + + NO_TRIGGER + No trigger 3 event generated. + 0 + + + INITIATE_TRIGGER_3 + Trigger 3 event generated. + 0x1 + + + + + + + TSTAT + Trigger Status Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + TEXC_NUM + Trigger Exception Number + 0 + 4 + read-write + oneToClear + + + NO_EXCEPTIONS + No triggers have been interrupted by a high-priority exception. + 0 + + + BIT0_MEANS_TRIGGER_0_INTERRUPTED + Trigger 0 has been interrupted by a high-priority exception. + 0x1 + + + BIT1_MEANS_TRIGGER_1_INTERRUPTED + Trigger 1 has been interrupted by a high-priority exception. + 0x2 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_3 + Associated trigger sequence has interrupted by a high-priority exception. + 0x3 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_4 + Associated trigger sequence has interrupted by a high-priority exception. + 0x4 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_5 + Associated trigger sequence has interrupted by a high-priority exception. + 0x5 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_6 + Associated trigger sequence has interrupted by a high-priority exception. + 0x6 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_7 + Associated trigger sequence has interrupted by a high-priority exception. + 0x7 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_8 + Associated trigger sequence has interrupted by a high-priority exception. + 0x8 + + + SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_9 + Associated trigger sequence has interrupted by a high-priority exception. + 0x9 + + + ALL_BITS_SET_INDICATE_ALL_TRIGGERS_INTERRUPTED + Every trigger sequence has been interrupted by a high-priority exception. + 0xF + + + + + TCOMP_FLAG + Trigger Completion Flag + 16 + 4 + read-write + oneToClear + + + NO_TRIGGER + No triggers have been completed. Trigger completion interrupts are disabled. + 0 + + + BIT0_MEANS_TRIGGER_0_COMPLETED + Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + 0x1 + + + BIT1_MEANS_TRIGGER_1_COMPLETED + Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + 0x2 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_3 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x3 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_4 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x4 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_5 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x5 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_6 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x6 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_7 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x7 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_8 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x8 + + + SET_BITS_INDICATE_TRIGGER_x_COMPLETED_9 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x9 + + + ALL_BITS_SET_INDICATE_ALL_TRIGGERS_COMPLETED + Every trigger sequence has been completed and every trigger has enabled completion interrupts. + 0xF + + + + + + + OFSTRIM + Offset Trim Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFSTRIM_A + Trim for Offset + 0 + 5 + read-write + + + OFSTRIM_B + Trim for Offset + 16 + 5 + read-write + + + + + 4 + 0x4 + TCTRL[%s] + Trigger Control Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HTEN + Trigger Enable + 0 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + FIFO_SEL_A + SAR Result Destination for Channel A + 1 + 1 + read-write + + + STORE_TO_FIFO0 + FIFO 0 + 0 + + + STORE_TO_FIFO1 + FIFO 1 + 0x1 + + + + + FIFO_SEL_B + SAR Result Destination for Channel B + 2 + 1 + read-write + + + STORE_TO_FIFO0 + FIFO 0 + 0 + + + STORE_TO_FIFO1 + FIFO 1 + 0x1 + + + + + TPRI + Trigger Priority Setting + 8 + 2 + read-write + + + HIGHEST_PRIORITY + Highest priority, Level 1 + 0 + + + CORRESPONDING_LOWER_PRIORITY_1 + Set to corresponding priority level. + 0x1 + + + CORRESPONDING_LOWER_PRIORITY_2 + Set to corresponding priority level. + 0x2 + + + LOWEST_PRIORITY + Lowest priority, Level 4 + 0x3 + + + + + RSYNC + Trigger Resync + 15 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TDLY + Trigger Delay Select + 16 + 4 + read-write + + + TCMD + Trigger Command Select + 24 + 4 + read-write + + + NOT_VALID + Not a valid selection from the command buffer. Trigger event is ignored. + 0 + + + EXECUTE_CMD1 + CMD1 + 0x1 + + + EXECUTE_CORRESPONDING_CMD_2 + Corresponding CMD is executed + 0x2 + + + EXECUTE_CORRESPONDING_CMD_3 + Corresponding CMD is executed + 0x3 + + + EXECUTE_CORRESPONDING_CMD_4 + Corresponding CMD is executed + 0x4 + + + EXECUTE_CORRESPONDING_CMD_5 + Corresponding CMD is executed + 0x5 + + + EXECUTE_CORRESPONDING_CMD_6 + Corresponding CMD is executed + 0x6 + + + EXECUTE_CORRESPONDING_CMD_7 + Corresponding CMD is executed + 0x7 + + + EXECUTE_CORRESPONDING_CMD_8 + Corresponding CMD is executed + 0x8 + + + EXECUTE_CORRESPONDING_CMD_9 + Corresponding CMD is executed + 0x9 + + + EXECUTE_CMD15 + CMD15 + 0xF + + + + + + + 2 + 0x4 + FCTRL[%s] + FIFO Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FCOUNT + Result FIFO Counter + 0 + 5 + read-only + + + FWMARK + Watermark Level Selection + 16 + 4 + read-write + + + + + 2 + 0x4 + GCC[%s] + Gain Calibration Control + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GAIN_CAL + Gain Calibration Value + 0 + 16 + read-only + + + RDY + Gain Calibration Value Valid + 24 + 1 + read-only + + + GAIN_CAL_NOT_VALID + Invalid + 0 + + + HARDWARE_CAL_ROUTINE_COMPLETED + Valid + 0x1 + + + + + + + 2 + 0x4 + GCR[%s] + Gain Calculation Result + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GCALR + Gain Calculation Result + 0 + 16 + read-write + + + RDY + Gain Calculation Ready + 24 + 1 + read-write + + + NOT_VALID + Invalid + 0 + + + VALID + Valid + 0x1 + + + + + + + CMDL1 + Command Low Buffer Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH1 + Command High Buffer Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL2 + Command Low Buffer Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH2 + Command High Buffer Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL3 + Command Low Buffer Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH3 + Command High Buffer Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL4 + Command Low Buffer Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH4 + Command High Buffer Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL5 + Command Low Buffer Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH5 + Command High Buffer Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL6 + Command Low Buffer Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH6 + Command High Buffer Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL7 + Command Low Buffer Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH7 + Command High Buffer Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL8 + Command Low Buffer Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH8 + Command High Buffer Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL9 + Command Low Buffer Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH9 + Command High Buffer Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL10 + Command Low Buffer Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH10 + Command High Buffer Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL11 + Command Low Buffer Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH11 + Command High Buffer Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL12 + Command Low Buffer Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH12 + Command High Buffer Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL13 + Command Low Buffer Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH13 + Command High Buffer Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL14 + Command Low Buffer Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH14 + Command High Buffer Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + CMDL15 + Command Low Buffer Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + SELECT_CH0 + CH0A or CH0B or CH0A/CH0B pair. + 0 + + + SELECT_CH1 + CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + SELECT_CH2 + CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + SELECT_CH3 + CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + SELECT_CORRESPONDING_CHANNEL_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + SELECT_CORRESPONDING_CHANNEL_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + SELECT_CORRESPONDING_CHANNEL_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + SELECT_CORRESPONDING_CHANNEL_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + SELECT_CORRESPONDING_CHANNEL_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + SELECT_CORRESPONDING_CHANNEL_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + SELECT_CH30 + CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + SELECT_CH31 + CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + SINGLE_ENDED_A_SIDE_CHANNEL + Single-Ended mode. Only A-side channel is converted. + 0 + + + SINGLE_ENDED_B_SIDE_CHANNEL + Single-Ended mode. Only B-side channel is converted. + 0x1 + + + DIFFERENTIAL_A_MINUS_B + Differential mode. A-B. + 0x2 + + + DUAL_A_AND_B + Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + 0x3 + + + + + MODE + Select Resolution of Conversions + 7 + 1 + read-write + + + DATA_12_BITS + Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + 0 + + + DATA_16_BITS + High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH15 + Command High Buffer Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + DISABLED_ALWAYS_STORE_RESULT + Disabled + 0 + + + COMPARE_RESULT_STORE_IF_TRUE + Enabled. Store on true. + 0x2 + + + COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for Trigger Assertion Before Execution + 2 + 1 + read-write + + + DISABLED + Command executes automatically. + 0 + + + ENABLED + Active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + SAMPLE_3p5 + Minimum sample time of 3.5 ADCK cycles. + 0 + + + SAMPLE_5p5 + 5.5 ADCK cycles + 0x1 + + + SAMPLE_7p5 + 7.5 ADCK cycles + 0x2 + + + SAMPLE_11p5 + 11.5 ADCK cycles + 0x3 + + + SAMPLE_19p5 + 19.5 ADCK cycles + 0x4 + + + SAMPLE_35p5 + 35.5 ADCK cycles + 0x5 + + + SAMPLE_67p5 + 67.5 ADCK cycles + 0x6 + + + SAMPLE_131p5 + 131.5 ADCK cycles + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + NO_AVERAGE + Single conversion + 0 + + + AVERAGE_2 + 2 + 0x1 + + + AVERAGE_4 + 4 + 0x2 + + + AVERAGE_8 + 8 + 0x3 + + + AVERAGE_16 + 16 + 0x4 + + + AVERAGE_32 + 32 + 0x5 + + + AVERAGE_64 + 64 + 0x6 + + + AVERAGE_128 + 128 + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + CMD_EXEC_1x + Looping not enabled. Command executes one time. + 0 + + + CMD_EXEC_2x + Loop one time. Command executes two times. + 0x1 + + + CMD_EXEC_3x + Loop two times. Command executes three times. + 0x2 + + + CMD_EXECUTES_CORRESPONDING_TIMES_3 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x3 + + + CMD_EXECUTES_CORRESPONDING_TIMES_4 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x4 + + + CMD_EXECUTES_CORRESPONDING_TIMES_5 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x5 + + + CMD_EXECUTES_CORRESPONDING_TIMES_6 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x6 + + + CMD_EXECUTES_CORRESPONDING_TIMES_7 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x7 + + + CMD_EXECUTES_CORRESPONDING_TIMES_8 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x8 + + + CMD_EXECUTES_CORRESPONDING_TIMES_9 + Loop corresponding number of times. Command executes LOOP + 1 times. + 0x9 + + + CMD_EXEC_15x + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NO_NEXT_CMD_TERMINATE_ON_FINISH + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + DO_CMD1_NEXT + CMD1 + 0x1 + + + DO_CORRESPONDING_CMD_NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + DO_CORRESPONDING_CMD_NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + DO_CORRESPONDING_CMD_NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + DO_CORRESPONDING_CMD_NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + DO_CORRESPONDING_CMD_NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + DO_CORRESPONDING_CMD_NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + DO_CORRESPONDING_CMD_NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + DO_CORRESPONDING_CMD_NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + DO_CMD15_NEXT + CMD15 + 0xF + + + + + + + 15 + 0x4 + 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CV%s + Compare Value Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CVL + Compare Value Low + 0 + 16 + read-write + + + CVH + Compare Value High + 16 + 16 + read-write + + + + + 2 + 0x4 + RESFIFO[%s] + Data Result FIFO Register + 0x300 + 32 + read-only + 0 + 0xFFFFFFFF + + + D + Data Result + 0 + 16 + read-only + + + TSRC + Trigger Source + 16 + 2 + read-only + + + TRIGGER_0 + Trigger source 0 + 0 + + + TRIGGER_1 + Trigger source 1 + 0x1 + + + CORRESPONDING_TRIGGER_2 + Corresponding trigger source initiated this conversion. + 0x2 + + + TRIGGER_3 + Trigger source 3 + 0x3 + + + + + LOOPCNT + Loop Count Value + 20 + 4 + read-only + + + RESULT_1 + Result is from initial conversion in command. + 0 + + + RESULT_2 + Result is from second conversion in command. + 0x1 + + + CORRESPONDING_RESULT_2 + Result is from (LOOPCNT + 1) conversion in command. + 0x2 + + + CORRESPONDING_RESULT_3 + Result is from (LOOPCNT + 1) conversion in command. + 0x3 + + + CORRESPONDING_RESULT_4 + Result is from (LOOPCNT + 1) conversion in command. + 0x4 + + + CORRESPONDING_RESULT_5 + Result is from (LOOPCNT + 1) conversion in command. + 0x5 + + + CORRESPONDING_RESULT_6 + Result is from (LOOPCNT + 1) conversion in command. + 0x6 + + + CORRESPONDING_RESULT_7 + Result is from (LOOPCNT + 1) conversion in command. + 0x7 + + + CORRESPONDING_RESULT_8 + Result is from (LOOPCNT + 1) conversion in command. + 0x8 + + + CORRESPONDING_RESULT_9 + Result is from (LOOPCNT + 1) conversion in command. + 0x9 + + + RESULT_16 + Result is from 16th conversion in command. + 0xF + + + + + CMDSRC + Command Buffer Source + 24 + 4 + read-only + + + NOT_VALID + Not a valid value CMDSRC value for a data word in RESFIFO. 0h is only found in the initial FIFO state, prior to the storage of an ADC conversion result into a RESFIFO buffer. + 0 + + + CMD1 + CMD1 + 0x1 + + + CORRESPONDING_CMD_2 + Corresponding command buffer used as control settings for this conversion. + 0x2 + + + CORRESPONDING_CMD_3 + Corresponding command buffer used as control settings for this conversion. + 0x3 + + + CORRESPONDING_CMD_4 + Corresponding command buffer used as control settings for this conversion. + 0x4 + + + CORRESPONDING_CMD_5 + Corresponding command buffer used as control settings for this conversion. + 0x5 + + + CORRESPONDING_CMD_6 + Corresponding command buffer used as control settings for this conversion. + 0x6 + + + CORRESPONDING_CMD_7 + Corresponding command buffer used as control settings for this conversion. + 0x7 + + + CORRESPONDING_CMD_8 + Corresponding command buffer used as control settings for this conversion. + 0x8 + + + CORRESPONDING_CMD_9 + Corresponding command buffer used as control settings for this conversion. + 0x9 + + + CMD15 + CMD15 + 0xF + + + + + VALID + FIFO Entry is Valid + 31 + 1 + read-only + + + NOT_VALID + FIFO is empty. Discard any read from RESFIFO. + 0 + + + VALID + FIFO contains data. FIFO record read from RESFIFO is valid. + 0x1 + + + + + + + 33 + 0x4 + CAL_GAR[%s] + Calibration General A-Side Registers + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GAR_VAL + Calibration General A Side Register Element + 0 + 11 + read-write + + + + + 33 + 0x4 + CAL_GBR[%s] + Calibration General B-Side Registers + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GBR_VAL + Calibration General B Side Register Element + 0 + 11 + read-write + + + + + + + LPCMP0 + LPCMP + LPCMP + LPCMP + 0x40048000 + + 0 + 0x24 + registers + + + LPCMP0 + 72 + + + + VERID + Version ID + 0 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + ROUND_ROBIN + Round robin feature + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + DAC_RES + DAC Resolution + 0 + 4 + read-only + + + RESO_4 + 4-bit DAC + 0 + + + RESO_6 + 6-bit DAC + 0x1 + + + RESO_8 + 8-bit DAC + 0x2 + + + RESO_10 + 10-bit DAC + 0x3 + + + RESO_12 + 12-bit DAC + 0x4 + + + RESO_14 + 14-bit DAC + 0x5 + + + RESO_16 + 16-bit DAC + 0x6 + + + + + + + CCR0 + Comparator Control Register 0 + 0x8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CMP_EN + Comparator Enable + 0 + 1 + read-write + + + DISABLE + Disables (The analog logic remains off and consumes no power.) + 0 + + + ENABLE + Enables + 0x1 + + + + + CMP_STOP_EN + Comparator Sleep Mode Enable + 1 + 1 + read-write + + + DISABLE + Disable the analog comparator regardless of CMP_EN. + 0 + + + ENABLE + Allows CMP_EN to enable the analog comparator. + 0x1 + + + + + + + CCR1 + Comparator Control Register 1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINDOW_EN + Windowing Enable + 0 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + SAMPLE_EN + Sampling Enable + 1 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + DMA_EN + DMA Enable + 2 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + COUT_INV + Comparator Invert + 3 + 1 + read-write + + + NO_INVERT + Do not invert + 0 + + + INVERT + Invert + 0x1 + + + + + COUT_SEL + Comparator Output Select + 4 + 1 + read-write + + + COUT + Use COUT (filtered) + 0 + + + COUTA + Use COUTA (unfiltered) + 0x1 + + + + + COUT_PEN + Comparator Output Pin Enable + 5 + 1 + read-write + + + UNAVAILABLE + Not available + 0 + + + AVAILABLE + Available + 0x1 + + + + + COUTA_OWEN + COUTA_OW Enable + 6 + 1 + read-write + + + SAMPLED + COUTA holds the last sampled value + 0 + + + COUTA_OW + COUTA_OW defines COUTA + 0x1 + + + + + COUTA_OW + COUTA Output Level for Closed Window + 7 + 1 + read-write + + + COUTA_0 + COUTA is 0 + 0 + + + COUTA_1 + COUTA is 1 + 0x1 + + + + + WINDOW_INV + WINDOW/SAMPLE Signal Invert + 8 + 1 + read-write + + + NO_INVERT + Do not invert + 0 + + + INVERT + Invert + 0x1 + + + + + WINDOW_CLS + CMPO Event Window Close + 9 + 1 + read-write + + + NO_CLOSE + CMPO event cannot close the window + 0 + + + CLOSE + CMPO event can close the window + 0x1 + + + + + EVT_SEL + CMPO Event Select + 10 + 2 + read-write + + + RISING + Rising edge + 0 + + + FALLING + Falling edge + 0x1 + + + BOTH + Both edges + #1x + + + + + FILT_CNT + Filter Sample Count + 16 + 3 + read-write + + + BYPASSED + Filter is bypassed: COUT = COUTA + 0 + + + SAMPLE_1 + 1 consecutive sample (Comparator output is simply sampled.) + 0x1 + + + SAMPLE_2 + 2 consecutive samples + 0x2 + + + SAMPLE_3 + 3 consecutive samples + 0x3 + + + SAMPLE_4 + 4 consecutive samples + 0x4 + + + SAMPLE_5 + 5 consecutive samples + 0x5 + + + SAMPLE_6 + 6 consecutive samples + 0x6 + + + SAMPLE_7 + 7 consecutive samples + 0x7 + + + + + FILT_PER + Filter Sample Period + 24 + 8 + read-write + + + + + CCR2 + Comparator Control Register 2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP_HPMD + CMP High Power Mode Select + 0 + 1 + read-write + + + LOW + Low power (speed) comparison mode + 0 + + + HIGH + High power (speed) comparison mode + 0x1 + + + + + CMP_NPMD + CMP Nano Power Mode Select + 1 + 1 + read-write + + + NO_NANO + Disables (CCR2[CMP_HPMD] determines the mode). + 0 + + + NANO + Enables + 0x1 + + + + + HYSTCTR + Comparator Hysteresis Control + 4 + 2 + read-write + + + LEVEL_0 + Level 0 + 0 + + + LEVEL_1 + Level 1 + 0x1 + + + LEVEL_2 + Level 2 + 0x2 + + + LEVEL_3 + Level 3 + 0x3 + + + + + PSEL + Plus Input MUX Select + 16 + 3 + read-write + + + INPUT_0 + Input 0p + 0 + + + INPUT_1 + Input 1p + 0x1 + + + INPUT_2 + Input 2p + 0x2 + + + INPUT_3 + Input 3p + 0x3 + + + INPUT_4 + Input 4p + 0x4 + + + INPUT_5 + Input 5p + 0x5 + + + INPUT_7 + Internal DAC output + 0x7 + + + + + MSEL + Minus Input MUX Select + 20 + 3 + read-write + + + INPUT_0 + Input 0m + 0 + + + INPUT_1 + Input 1m + 0x1 + + + INPUT_2 + Input 2m + 0x2 + + + INPUT_3 + Input 3m + 0x3 + + + INPUT_4 + Input 4m + 0x4 + + + INPUT_5 + Input 5m + 0x5 + + + INPUT_7 + Internal DAC output + 0x7 + + + + + + + DCR + DAC Control + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAC_EN + DAC Enable + 0 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + DAC_HPMD + DAC High Power Mode Select + 1 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables + 0x1 + + + + + VRSEL + DAC Reference High Voltage Source Select + 8 + 1 + read-write + + + VREF0 + vrefh0 + 0 + + + VREF1 + vrefh1 + 0x1 + + + + + DAC_DATA + DAC Output Voltage Select + 16 + 8 + read-write + + + + + IER + Interrupt Enable + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CFR_IE + Comparator Flag Rising Interrupt Enable + 0 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables: Assert an interrupt when CFR sets. + 0x1 + + + + + CFF_IE + Comparator Flag Falling Interrupt Enable + 1 + 1 + read-write + + + DISABLE + Disables + 0 + + + ENABLE + Enables: Assert an interrupt when CFF sets. + 0x1 + + + + + + + CSR + Comparator Status + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CFR + Analog Comparator Flag Rising + 0 + 1 + read-write + oneToClear + + + NOT_DETECTED + Not detected + 0 + + + DETECTED + Detected + 0x1 + + + + + CFF + Analog Comparator Flag Falling + 1 + 1 + read-write + oneToClear + + + NOT_DETECTED + Not detected + 0 + + + DETECTED + Detected + 0x1 + + + + + COUT + Analog Comparator Output + 8 + 1 + read-only + + + + + + + LPCMP1 + LPCMP + LPCMP + 0x40049000 + + 0 + 0x24 + registers + + + LPCMP1 + 73 + + + + VREF0 + VREF + VREF + 0x4004A000 + + 0 + 0x14 + registers + + + + VERID + Version ID + 0 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameters + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CSR + Control and Status + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HCBGEN + HC Bandgap Enabled + 0 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + LPBGEN + Low-Power Bandgap Enable + 1 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + LPBG_BUF_EN + Low-Power Bandgap Buffer Enable + 2 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + CHOPEN + Chop Oscillator Enable + 3 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + ICOMPEN + Current Compensation Enable + 4 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + REGEN + Regulator Enable + 5 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + REFCHSELN_EN + Reference Channel Select Negative Enable + 6 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + REFCHSELP_EN + Reference Channel Select Positive Enable + 7 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + VRSEL + Voltage Reference Selection + 8 + 2 + read-write + + + BANDGAP + Internal bandgap + 0 + + + ONE_V + Low-power buffered 1v + 0x1 + + + TWO_PT_ONE_V + Buffer 2.1v output + 0x2 + + + + + REFL_GRD_SEL + Ground Select + 10 + 1 + read-write + + + VREFL_3V + vrefl_3v + 0 + + + VSSA + VSSA + 0x1 + + + + + HI_PWR_LV + High-Power Level + 11 + 1 + read-write + + + LOW + Low-power + 0 + + + HIGH + High-power + 0x1 + + + + + BUF21EN + Internal Buffer21 Enable + 16 + 1 + read-write + + + DIS + Disables + 0 + + + ENA + Enables + 0x1 + + + + + VREFST + Internal HC Voltage Reference Stable + 31 + 1 + read-only + + + DIS_NOTSTABLE + Disabled and unstable + 0 + + + STABLE + Stable + 0x1 + + + + + + + UTRIM + User Trim + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM2V1 + VREF 2.1V Trim + 0 + 4 + read-write + + + VREFTRIM + VREF Trim + 8 + 6 + read-write + + + + + + + CIU2 + no description available + CIU2 + 0x48948000 + + 0 + 0x258 + registers + + + RF_NBU + 50 + + + + CIU2_CLK_ENABLE + Clock enable + 0 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + ahb2_clk_enable + Clock ahb2_clk enable signal. Ahb2_clk enable. 1: enable, 0: disable + 29 + 1 + read-write + + + cpu1_div_clk_enable + Clock cpu1_div_clk enable signal. cpu1_div_clk enable. 1: enable, 0: disable + 30 + 1 + read-write + + + soc_ahb_clk_sel + Clock selection for soc_ahb_clk. 0: AHB2_CLK, 1: CPU1_CLK_DIV + 31 + 1 + read-write + + + + + CIU2_ECO_0 + ECO Register 0 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_1 + ECO Register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_2 + ECO Register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_3 + ECO Register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_4 + ECO Register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_5 + ECO Register 5 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_6 + ECO Register 6 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_7 + ECO Register 7 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_8 + ECO Register 8 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_9 + ECO Register 9 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_10 + ECO Register 10 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_11 + ECO Register 11 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_12 + ECO Register 12 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_13 + ECO Register 13 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_14 + ECO Register 14 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_ECO_15 + ECO Register 15 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + spare + Eco Reserve Register + 0 + 32 + read-write + + + + + CIU2_CLK_ENABLE4 + Clock Enable 4 + 0x100 + 32 + read-write + 0x6029403F + 0xFFFFFFFF + + + bist_ahb2_clk_gating_en + CPU2 Redbist and Rombist Clock for ITCM/DTCM/SQU/BROM + 0 + 1 + read-write + + + bru_ahb2_addr_mask_dis + CPU2 ROM Address Mask Selection + 1 + 1 + read-write + + + itcm_ahb2_dyn_clk_gating_dis + CPU2 ITCM Dynamic Clock Gating Feature + 2 + 1 + read-write + + + dtcm_ahb2_dyn_clk_gating_dis + CPU2 DTCM Dynamic Clock Gating Feature + 3 + 1 + read-write + + + bru_ahb2_dyn_clk_gating_dis + CPU2 ROM Dynamic Clock Gating Feature + 4 + 1 + read-write + + + smu2_dyn_clk_gating_dis + SMU2 Dynamic Clock Gating Feature + 5 + 1 + read-write + + + ebram_bist_clk_en + EBRAM BIST Clock Enable + 8 + 1 + read-write + + + bt_eclk_en + BTU EBC Clock Enable + 9 + 1 + read-write + + + bt_4mclk_en + BTU 4 MHz Clock Enable + 10 + 1 + read-write + + + btu_ahb_clk_en + BTU AHB Clock Enable + 13 + 1 + read-write + + + siu_clk_en + BT SIU (UART) clock enable + 14 + 1 + read-write + + + smu2_ahb_clk_en + SMU2 AHB Clock Enable + 16 + 1 + read-write + + + hpu2_ciu_clk_en + HPU2 CIU Clock Enable + 19 + 1 + read-write + + + ble_ahb_clk_en + BLE ARM Clock Enable + 20 + 1 + read-write + + + ble_sys_clk_en + BLE SYS Clock Enable + 21 + 1 + read-write + + + ble_aeu_clk_en + BT/BLE AEU Clock Enable + 22 + 1 + read-write + + + bt_16m_clk_en + BT 16MHz Clock Enable + 23 + 1 + read-write + + + dbus_clk_en + BLE DBUS Clock Enable + 24 + 1 + read-write + + + siu_ahb2_clk_en + BT SIU (UART) AHB clock enable + 29 + 1 + read-write + + + btrtu1_clk_en + BT RTU1 clock enable + 30 + 1 + read-write + + + + + CIU2_CLK_ENABLE5 + Clock Enable 5 + 0x104 + 32 + read-write + 0x9FFFFF8F + 0xFFFFFFFF + + + itcm_ahb2_clk_en + Enable CPU2 ITCM Banks 1-2 + 0 + 3 + read-write + + + bt_adma_ahb_clk_en + BT ADMA AHB Clock Enable + 3 + 1 + read-write + + + ciu2_reg_clk_en + CIU2 Reg Clock Enable + 7 + 1 + read-write + + + br_ahb2_clk_en + CPU2 BROM AHB Clock Enable + 8 + 15 + read-write + + + btu_mclk_en + BTU MCLK Enalbe + 23 + 1 + read-write + + + smu2_bank_clk_en + SMU2 bank Clock Enable + 24 + 3 + read-write + + + sif_clk_sel + SIF Clock Select + 27 + 1 + read-write + + + cpu2_gatehclk_en + 1 = Give hclk control to cpu2 generated HW signal to gate the clock automatically in sleep 0 = No hclk gating + 28 + 1 + read-write + + + cpu2_fabric_clk_en + 1= Give cpu2 fabric clock control to cpu2 generated HW signal to gate the clock automatically in sleep 0 = No cpu2 fabric gating + 29 + 1 + read-write + + + cpu2_mem_slv_clk_en + 1= Give cpu2 mem slave clock control to cpu2 generated HW signal to gate the clock automatically in sleep 0 = No cpu2 mem slave clock gating + 30 + 1 + read-write + + + sif_ahb2_clk_en + SIF ahb2 Clock Enalbe + 31 + 1 + read-write + + + + + CIU2_CLK_CPU2CLK_CTRL + CPU2_AHB2 Clock Control + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + t1_freq_sel + AHB2 Clock Frequency Select + 0 + 4 + read-write + + + + + CIU2_CLK_UARTCLK_CTRL + UART Clock Control + 0x10C + 32 + read-write + 0x249A4900 + 0xFFFFFFFF + + + refclk_sel + Reference Clock Select + 0 + 1 + read-write + + + nco_step_size + Programmable UART Clock Frequency + 7 + 25 + read-write + + + + + CIU2_CLK_LBU2_BTRTU1_CTRL + LBU2 BT_RTU1 Clock Control + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + lbu2_use_refclk + Static bit set by FW based on Reference Clock Frequency. If reference clock frequency is lower and LBU can not support high baud rate of UART, then FW will set soc_use_ref_mode = 0. This is an indication for Bluetooth subsystem that there is some IP which need PLL to function which is LBU in this case. + 1 + 1 + read-write + + + btrtu1_timer1_use_slp_clk + Timer 1 BT_RTU1 Clock + 11 + 1 + read-write + + + btrtu1_use_ref_clk + Static bit set by FW. If it is required that timers need not be programmed with dynamic switching of T1/Reference, the BT_RTU1 source clock is set on reference clock so that the timer are not distrubed. + 12 + 1 + read-write + + + btrtu1_dbg_clk_ctrl + 1= Enable BT_RTU1 timers turn off during debugger mode 0= This feature is disabled + 15 + 1 + read-write + + + + + CIU2_CLK_CP15_DIS3 + Clock Auto Shut-off Enable3 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + br_ahb2_clk + BRU_AHB2 Shut Off + 0 + 16 + read-write + + + imem_ahb2_clk + IMEM_AHB2 Shut Off + 21 + 4 + read-write + + + dmem_ahb2_clk + DMEM_AHB2 Shut Off + 25 + 2 + read-write + + + arb_ahb2_clk + AHB2 Arbiter Shut Off + 28 + 1 + read-write + + + dec_ahb2_clk + AHB2 Decoder Shut Off + 29 + 1 + read-write + + + btu_ahb_clk + BTU Shut Off + 30 + 1 + read-write + + + ble_ahb_clk + BLE Shut Off + 31 + 1 + read-write + + + + + CIU2_RST_SW3 + Software Module Reset + 0x11C + 32 + read-write + 0xE45D0FB7 + 0xFFFFFFFF + + + btu_ahb_clk_ + BTU (ARM_Clk) Soft Reset + 0 + 1 + read-write + + + ble_soc_ + BLE SoC Soft Reset + 1 + 1 + read-write + + + bt_common_ + BT Common Soft Rest + 2 + 1 + read-write + + + cpu2_core_ + CPU2 core reset + 4 + 1 + read-write + + + cpu2_tcm_ + CPU2 TCM/DMA/Arbiter reset + 5 + 1 + read-write + + + arb_ahb2_clk_ + AHB2 Arbiter Soft Reset + 7 + 1 + read-write + + + dec_ahb2_clk_ + AHB2 Decoder Mux Soft Reset + 8 + 1 + read-write + + + bru_ahb2_clk_ + BRU_AHB2 Soft Reset + 9 + 1 + read-write + + + bt_uart_n + BT UART soft reset + 10 + 1 + read-write + + + siu_ahb2_clk_n + BT SIU (UART) AHB soft reset + 11 + 1 + read-write + + + smu2_ahb_clk_ + SMU2 (AHB_Clk) Soft Reset + 16 + 1 + read-write + + + sif_ + sif clock Soft Reset + 18 + 1 + read-write + + + sif_ahb2_clk_ + sif ahb2 Clock Soft Reset + 19 + 1 + read-write + + + hpu2_ + HPU2 Reset + 20 + 1 + read-write + + + ciu2_ahb_clk_ + CIU2 AHB Soft Reset + 22 + 1 + read-write + + + brf_pr_ + BRF_PR Reset + 26 + 1 + read-write + + + wd2_chip_rst_disable + 1: Disable the rtu2 watchdog reset to reset the chip 0: Enable + 28 + 1 + read-write + + + wd2_cpu2_rst_disable + 1: Disable the rtu2 watchdog reset to reset the CPU2 0: Enable + 29 + 1 + read-write + + + bt_16m_clk_ + Bt 16M clock reset + 30 + 1 + read-write + + + bt_adma_ + BT ADMA Soft Reset + 31 + 1 + read-write + + + + + CIU2_MEM_WRTC3 + Memory WRTC Control 3 + 0x120 + 32 + read-write + 0x2600 + 0xFFFFFFFF + + + ble_rom_rtc + BLE ROM RTC + 8 + 3 + read-write + + + ble_rom_rtc_ref + BLE ROM RTC_REF + 12 + 2 + read-write + + + + + CIU2_MEM_WRTC4 + Memory WRTC Control 4 + 0x124 + 32 + read-write + 0x14166555 + 0xFFFFFFFF + + + cpu2_itcm_rtc + CPU2 ITCM RTC + 0 + 2 + read-write + + + cpu2_itcm_wtc + CPU2 ITCM WTC + 2 + 2 + read-write + + + cpu2_dtcm_rtc + CPU2 DTCM RTC + 4 + 2 + read-write + + + cpu2_dtcm_wtc + CPU2 DTCM WTC + 6 + 2 + read-write + + + smu2_rtc + SMU2 RTC + 8 + 2 + read-write + + + smu2_wtc + SMU2 WTC + 10 + 2 + read-write + + + cpu2_bru_rtc + CPU2 BROM RTC + 12 + 3 + read-write + + + cpu2_bru_rtc_ref + CPU2 BROM RTC_REF + 16 + 2 + read-write + + + btu_rtc + BTU EBRAM RTC + 18 + 2 + read-write + + + btu_wtc + BTU EBRAM WTC + 20 + 2 + read-write + + + ble_rtc + ble RTC + 26 + 2 + read-write + + + ble_wtc + ble WTC + 28 + 2 + read-write + + + + + CIU2_MEM_PWDN3 + Memory Powerdown Control + 0x128 + 32 + read-write + 0x2770000 + 0xFFFFFFFF + + + cpu2_bru_bypass_val + Firmware Bypass value for CPU2 Boot ROM Memories Power Down + 0 + 1 + read-write + + + cpu2_dtcm_bypass_val + Firmware Bypass value for CPU2 DTCM Memories Power Down + 1 + 1 + read-write + + + cpu2_itcm_bypass_val + Firmware Bypass value for CPU2 ITCM Memories Power Down + 2 + 1 + read-write + + + smu2_bypass_val + Firmware Bypass value for SMU2 Memories Power Down + 4 + 1 + read-write + + + siu_bypass_val + Firmware Bypass value for UART Memories Power Down + 5 + 1 + read-write + + + btu_bypass_val + Firmware Bypass value for BTU Memories Power Down + 6 + 1 + read-write + + + bt_adma_bypass_val + Firmware Bypass value for BT ADMA Memories Power Down + 9 + 1 + read-write + + + cpu2_bru_bypass_en + Firmware Bypass Enable for CPU2 Boot ROM Memories Power Down + 16 + 1 + read-write + + + cpu2_dtcm_bypass_en + Firmware Bypass Enable for CPU2 DTCM Memories Power Down + 17 + 1 + read-write + + + cpu2_itcm_bypass_en + Firmware Bypass Enable for CPU2 ITCM Memories Power Down + 18 + 1 + read-write + + + smu2_bypass_en + Firmware Bypass Enable for SMU2 Memories Power Down + 20 + 1 + read-write + + + siu_bypass_en + Firmware Bypass Enable for UART Memories Power Down + 21 + 1 + read-write + + + btu_bypass_en + Firmware Bypass Enable for BTU Memories Power Down + 22 + 1 + read-write + + + bt_adma_bypass_en + Firmware Bypass Enable for BT ADMA Memories Power Down + 25 + 1 + read-write + + + + + CIU2_BLE_CTRL + BLE Control and Status + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + bt_aes_clk_freq_sel + btu_aes_clk Frequency Select + 8 + 1 + read-write + + + + + CIU2_AHB2_TO_LAST_ADDR + AHB2 Timeout Last Address + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + address + Last AHB2 Address Right Before the Current Timeout + 0 + 32 + read-only + + + + + CIU2_AHB2_TO_CUR_ADDR + AHB2 Current Timeout Address + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + address + Current_TO_Addr + 0 + 32 + read-only + + + + + CIU2_AHB2_TO_CTRL + AHB2 ARB Control + 0x14C + 32 + read-write + 0x70000 + 0xFFFFFFFF + + + current_to_slave_id + Current_TO_Slave_ID + 0 + 4 + read-only + + + last_to_slave_id + Last_TO_Slave_ID + 4 + 4 + read-only + + + current_to_master_id + AHB2 Current_TO_Master_ID + 8 + 4 + read-only + + + last_to_master_id + AHB2 Last_TO_Master_ID + 12 + 4 + read-only + + + ahb2_smu1_mem_prot_dis + Disable SMU1 Memory Protection from AHB2 side + 16 + 1 + read-write + + + ahb2_cpu2_imem_prot_dis + 1 = Disable CPU2 Imem Memory Protection from AHB2 side and allow AHB2 to read/write Imem + 17 + 1 + read-write + + + ahb2_cpu2_dmem_prot_dis + 1 = Disable CPU2 Dmem Memory Protection from AHB2 side and allow AHB2 to read/write Dmem + 18 + 1 + read-write + + + ahb2_timeout_mode + AHB2_TimeoutMode[1:0] + 30 + 2 + read-write + + + + + CIU2_AHB2_SMU1_ACCESS_ADDR + AHB2 to SMU1 Accessible Address + 0x150 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ahb2_smu1_access_addr + SMU1 Accessible Memory Address from AHB2 side + 0 + 32 + read-write + + + + + CIU2_AHB2_SMU1_ACCESS_MASK + AHB2 to SMU1 Accessible Mask + 0x154 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ahb2_smu1_access_mask + SMU1 Accessible Memory Mask from AHB2 side + 0 + 32 + read-write + + + + + CIU2_CPU2_FABRIC_ARB_CTRL + CPU2 fabric arbiter control + 0x158 + 32 + read-write + 0x44A + 0xFFFFFFFF + + + dmem_brst_term_cnt + 00= terminate dmem immediate after current transactio finish 01= termiante dmem transaction after 4 burst 10= termiante dmem transaction after 8 burst 11 = terminate dmem transaction after 16 burst + 0 + 2 + read-write + + + imem_brst_term_cnt + 00= terminate imem immediate after current transactio finish 01= termiante imem transaction after 4 burst 10= termiante imem transaction after 8 burst 11 = terminate imem transaction after 16 burst + 2 + 2 + read-write + + + dmem_noburstterm + 0= burst of dmem will be terminated as per [1:0] setting 1= burst of dmem will not be terminated + 4 + 1 + read-write + + + dmem_priority + 00= Dcode has higher prioirty compared to Icode for DMEM acccess 01= Dcode has higher prioirty compared to Icode for DMEM acccess 10= Icode has higher prioirty compared to Dcode for DMEM acccess 11= Dcode has higher prioirty compared to Icode for DMEM acccess + 5 + 2 + read-write + + + dmem_round_robin_en + 0= fixed priority for DMEM acess from Icode and Dcode 1= round robin priority for DMEM acess from Icode and Dcode + 7 + 1 + read-write + + + imem_noburstterm + 0= burst of imem will be terminated as per [1:0] setting 1= burst of imem will not be terminated + 8 + 1 + read-write + + + imem_priority + 00 = Icode has higher prioirty compared to Icode for IMEM acccess 01= Dcode has higher prioirty compared to Icode for IMEM acccess 10= Icode has higher prioirty compared to Dcode for IMEM acccess 11= Dcode has higher prioirty compared to Icode for IMEM acccess + 9 + 2 + read-write + + + imem_round_robin_en + 0= fixed priority for IMEM acess from Icode and Dcode 1= round robin priority for IMEM acess from Icode and Dcode + 11 + 1 + read-write + + + + + CIU2_CPU2_ICODE_INV_ADDR_CTRL + CPU2 Icode invalid address access control + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + last2_inv_addr_slave_id + Last2_inv_addr_Slave_ID + 0 + 4 + read-only + + + last_inv_addr_slave_id + Last_inv_addr_Slave_ID + 4 + 4 + read-only + + + cur_inv_addr_slave_id + Cur_inv_addr_Slave_ID + 8 + 4 + read-only + + + haddr_icod_sel + There are 3 haddr which can be observed by selecting this: + 30 + 2 + read-write + + + + + CIU2_CPU2_ICODE_INV_ADDR + CPU2 Icode invalid address + 0x160 + 32 + read-only + 0 + 0xFFFFFFFF + + + haddr_inv_addr + based on CIU_CPU2_ICODE_INV_ADDR_CTRL[31:30], the address status is obsrved in this register + 0 + 32 + read-only + + + + + CIU2_CPU2_DCODE_INV_ADDR_CTRL + CPU2 Dcode invalid address access control + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + last2_inv_addr_slave_id + Last2_inv_addr_Slave_ID + 0 + 4 + read-only + + + last_inv_addr_slave_id + Last_inv_addr_Slave_ID + 4 + 4 + read-only + + + cur_inv_addr_slave_id + Cur_inv_addr_Slave_ID + 8 + 4 + read-only + + + last2_inv_addr_master_id + Last2_inv_addr_master_ID + 12 + 4 + read-only + + + last_inv_addr_master_id + Last_inv_addr_master_ID + 16 + 4 + read-only + + + cur_inv_addr_master_id + Cur_inv_addr_master_ID + 20 + 4 + read-only + + + haddr_icod_sel + There are 3 haddr which can be observed by selecting this: + 30 + 2 + read-write + + + + + CIU2_CPU2_DCODE_INV_ADDR + CPU2 Dcode invalid address + 0x168 + 32 + read-only + 0 + 0xFFFFFFFF + + + haddr_inv_addr + based on CIU_CPU2_DCODE_INV_ADDR_CTRL[31:30], the address status is obsrved in this register + 0 + 32 + read-only + + + + + CIU2_CPU_CPU2_CTRL + CPU2 control register + 0x16C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + vinithi + 1= Boot form high address 0x0030_0000 (ROM) 0 = Boot from low address 0x0000_0000 (ITCM) By default CPU2 is out of reset and boot from ROM + 0 + 1 + read-write + + + cpu2_jtag_chain_bypass + 1 = Bypass the JTAG chain of CPU2 0 = The CPU2 remains in JTAG chain This bit is backup in case the CPU2 doesn't work on silicon + 2 + 1 + read-write + + + cpu2_boot_imem_mux_en + 1 = IMEM mux control is on CPU2 side to download the code during boot 0 = The IMEM mux is on CPU2 side + 4 + 1 + read-write + + + cpu2_boot_dmem_mux_en + 1 = DMEM mux control is on CPU2 side to download the code during boot 0 = The DMEM mux is on CPU2 side This bit is disconnected in NBU level, DMEM MUX will always on CPU2 side + 5 + 1 + read-write + + + cpu2_dbg_ctrl + cpu2 debug control + 16 + 12 + read-write + + + cpu3_reset_int + cpu2 fw resets cpu3(or cpu3 fw resets cpu2 if this register is used by cpu3) + 29 + 1 + read-write + + + dsr_wkup_in_use + dsr wkup when dsr_wkup_in_use = 1'b1 + 30 + 1 + read-write + + + cpu1_reset_int + cpu2 fw resets cpu1( or cpu3 fw resets cpu1 if this register is used by cpu3) + 31 + 1 + read-write + + + + + CIU2_BRF_CTRL + BRF Control and Status + 0x170 + 32 + read-write + 0x301 + 0xFFFFFFFF + + + ahb_slv_brf_ser_en + When set to 1, BRF serial interface will be accessed thru AHB slave memory mapped from 0xA800A000 to 0xA8011FFF + 0 + 1 + read-write + + + sel_brf_to_ssu_dump_path + When set to 0, select BRF to SSU dump path + 1 + 1 + read-write + + + ciu_brf_ref1x_clk_ctrl_bypass_en + 0: brf ref 1x clock is controlled brf_clk_req 1 + 8 + 1 + read-write + + + ciu_brf_ref1x_clk_ctrl_bypass_val + 1. brf ref clk 1x is enabled + 9 + 1 + read-write + + + brf_chip_rdy + BRF Chip_Rdy Status + 31 + 1 + read-only + + + + + CIU2_BRF_EXTRA_PORT + BRF Extra Port Connection + 0x174 + 32 + read-write + 0xA + 0xFFFFFFFF + + + soc_brf_extra + SOC_BRF_EXTRA[3:0] + 0 + 4 + read-write + + + + + CIU2_BRF_ECO_CTRL + BRF ECO Control + 0x17C + 32 + read-write + 0xAAAAAAAA + 0xFFFFFFFF + + + eco_bits + Reserved + 0 + 32 + read-write + + + + + CIU2_BTU_CTRL + BTU Control and Status + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + btu_cipher_en + Bluetooth Cipher Logic + 0 + 1 + read-write + + + dbus_high_speed_sel + Dbus High Speed Select Signal for Greater than 4 MHz + 1 + 1 + read-write + + + bt_clk_sel + Bluetooth sys Clock Select + 2 + 2 + read-write + + + bt_ip_ser_sel + bt_ip_ser_sel + 8 + 3 + read-write + + + btu_mc_wakeup + BTU MC_Wakeup Status + 31 + 1 + read-only + + + + + CIU2_BT_PS + BT Clock Power Save + 0x184 + 32 + read-write + 0x8000000 + 0xFFFFFFFF + + + bt_mclk_nco_mval + BT_MCLK NCO Module Step Control (default 0x0) + 0 + 26 + read-write + + + bt_mclk_nco_en + BT_MCLK_NCO logic to count + 26 + 1 + read-write + + + bt_mclk_tbg_nco_sel + BT_4M_PCM_CLK + 27 + 1 + read-write + + + bt_mclk_from_soc_sel + BT_MCLK + 28 + 1 + read-write + + + + + CIU2_BT_PS2 + BT Clock Power Save 2 + 0x188 + 32 + read-write + 0x8000000 + 0xFFFFFFFF + + + bt_pcm_clk_nco_mval + BT_PCM_CLK NCO Module Step Control (default 0x0) + 0 + 26 + read-write + + + bt_pcm_clk_nco_en + BT_PCM_CLK_NCO logic to count + 26 + 1 + read-write + + + bt_pcm_clk_tbg_nco_sel + BT_4M_PCM_CLK + 27 + 1 + read-write + + + + + CIU2_BT_REF_CTRL + BT Ref Control + 0x18C + 32 + read-write + 0x100000 + 0xFFFFFFFF + + + nco_en + Bluetooth Reference Clock NCO Enable information to APU. + 0 + 1 + read-write + + + nco_sel + Bluetooth Reference Clock NCO Select Value + 1 + 1 + read-write + + + nco_gen + Bluetooth Reference Clock NCO Gen Value + 2 + 16 + read-write + + + bt_clk_nco_refclk_sel + BT clk (bt sys clk) selection + 20 + 1 + read-write + + + + + CIU2_BT_PS3 + BT Clock Power Save 3 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + btu_16m_clk_nco_step_ctrl + BT_16M_CLK NCO Module Step Control + 0 + 26 + read-write + + + btu_16m_clk_nco_en + BTU 16M Clock NCO Enable + 26 + 1 + read-write + + + btu_16m_clk_nco_sel + BTU 16M clock NCO Select Value + 27 + 1 + read-write + + + btu_clk_nco_mode + BTU Clock source from ref clock (nco mode) + 29 + 1 + read-write + + + + + CIU2_BTU_ECO_CTRL + BTU ECO Control + 0x198 + 32 + read-write + 0xAAAAAAAA + 0xFFFFFFFF + + + eco_bits + Reserved + 0 + 32 + read-write + + + + + CIU2_INT_MASK + CIU2 Interrupt Mask + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + mask + Interrupt Mask for CIU2 Interrupts + 0 + 32 + read-write + + + + + CIU2_INT_SELECT + CIU2 Interrupt Select + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + sel + Interrupt Read/Write Clear for CIU2 Interrupts + 0 + 32 + read-write + + + + + CIU2_INT_EVENT_MASK + CIU2 Interrupt Event Mask + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + mask + Interrupt Event Mask for CIU2 Interrupts + 0 + 32 + read-write + + + + + CIU2_INT_STATUS + CIU2 Interrupt Status + 0x1AC + 32 + read-only + 0 + 0xFFFFFFFF + + + ciu_isr + CIU2 Interrupt Status (ISR) + 0 + 32 + read-only + + + + + CPU2_ERR_INT_MASK + CPU2 ERR Interrupt Mask + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + mask + Interrupt Mask for CPU2 ERR Interrupts + 0 + 32 + read-write + + + + + CPU2_ERR_INT_SELECT + CPU2 ERR Interrupt Clear Select + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + sel + Interrupt Read/Write Clear for CPU2 ERR Interrupts + 0 + 32 + read-write + + + + + CPU2_ERR_INT_EVENT_MASK + CPU2 ERR Interrupt Event Mask + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + mask + Interrupt Event Mask for CPU2 ERR Interrupts + 0 + 32 + read-write + + + + + CPU2_ERR_INT_STATUS + CPU2 ERR Interrupt Status + 0x1BC + 32 + read-only + 0 + 0xFFFFFFFF + + + err_isr + CPU2 ERR Interrupt Status (ISR) + 0 + 32 + read-only + + + + + CPU2_ERR_INT2_MASK + CPU2 ERR Interrupt 2 Mask + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + mask + Interrupt Mask for CPU2 ERR Interrupts 2 + 0 + 32 + read-write + + + + + CPU2_ERR_INT2_SELECT + CPU2 ERR Interrupt 2 Clear Select + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + sel + Interrupt Read/Write Clear for CPU2 ERR Interrupts 2 + 0 + 32 + read-write + + + + + CPU2_ERR_INT2_EVENT_MASK + CPU2 ERR Interrupt 2 Event Mask + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + mask + Interrupt Event Mask for CPU2 ERR Interrupts 2 + 0 + 32 + read-write + + + + + CPU2_ERR_INT2_STATUS + CPU2 ERR Interrupt 2 Status + 0x1CC + 32 + read-only + 0 + 0xFFFFFFFF + + + err_isr + CPU1 ERR Interrupt 2 Status (ISR) + 0 + 32 + read-only + + + + + CIU2_CPU_CPU2_MSG_CTRL + CPU2 message register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + cpu1_to_cpu2_msg_rdy + CPU1 Message for CPU2 is ready. This is self clearing bit. The CPU1 writes 1 to indicate that message for CPU2 is ready. This generates an Interrupt to CPU2 via APU. This is old schem and we should use IMU based scheme. + 0 + 1 + read-write + + + cpu3_to_cpu2_msg_rdy + CPU3 Message for CPU2 is ready. This is self clearing bit. The CPU3 writes 1 to indicate that message for CPU2 is ready. This generates an Interrupt to CPU2 via APU. This is old schem and we should use IMU based scheme. + 1 + 1 + read-write + + + cpu1_to_cpu2_msg_process_done + CPU1 Message for CPU2 has been read by CPU2 and executed. This is self clearing bit. The CPU2 writes 1 to indicate that message send by CPU1 is executed. This generates an Interrupt to CPU1 via CIU1. + 8 + 1 + read-write + + + cpu3_to_cpu2_msg_process_done + CPU3 Message for CPU2 has been read by CPU2 and executed. This is self clearing bit. The CPU2 writes 1 to indicate that message send by CPU3 is executed. This generates an Interrupt to CPU3 via CIU3. + 9 + 1 + read-write + + + + + CIU2_IMU_CPU1_WR_MSG_TO_CPU2 + CPU1 write message to CPU2 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + cpu1_wr_msg_cpu2 + Write CPU1 message data to CPU2 (push to FIFO) + 0 + 32 + read-write + + + + + CIU2_IMU_CPU1_RD_MSG_FROM_CPU2 + CPU1 read message from CPU2 + 0x1D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu1_rd_msg_cpu2 + CPU1 read message data from CPU2 (pop from FIFO) + 0 + 32 + read-only + + + + + CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS + CPU1 to CPU2 message FIFO status + 0x1DC + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu1_to_cpu2_msg_fifo_locked + cpu1_to_cpu2_msg_fifo_locked + 0 + 1 + read-only + + + cpu1_to_cpu2_msg_fifo_almost_full + cpu1_to_cpu2_msg_fifo_almost_full (based upon FIFO watermark) + 1 + 1 + read-only + + + cpu1_to_cpu2_msg_fifo_full + cpu1_to_cpu2_msg_fifo_full (based upon FIFO depth) + 2 + 1 + read-only + + + cpu1_to_cpu2_msg_fifo_empty + cpu1_to_cpu2_msg_fifo_empty + 3 + 1 + read-only + + + cpu1_to_cpu2_msg_count + cpu1_to_cpu2_msg_count + 4 + 5 + read-only + + + cpu1_to_cpu2_msg_fifo_wr_ptr + cpu1 to cpu2 msg fifo write pointer for debug + 16 + 4 + read-only + + + cpu1_to_cpu2_msg_fifo_rd_ptr + cpu1 to cpu2 msg fifo read pointer for debug + 20 + 4 + read-only + + + + + CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL + CPU1 to CPU2 message FIFO control + 0x1E0 + 32 + read-write + 0xF00000 + 0xFFFFFFFF + + + cpu1_msg_rdy_int_clr + Writing 1 to this bit will clear message ready interrupt to CPU1 (self clear bit) + 0 + 1 + read-write + + + cpu1_msg_sp_av_int_clr + Writing 1 to this bit will clear message space available interrupt to CPU1 (self clear bit) + 8 + 1 + read-write + + + cpu1_to_cpu2_msg_fifo_flush + Writing 1 to this bit will flush cpu1_to_cpu2 message fifo + 16 + 1 + read-write + + + cpu1_wait_for_ack + 1: CPU1 will wait for an ack for the next message to be written to CPU2 0: CPU1 will not wat for an ack for next message to be written to CPU2 + 17 + 1 + read-write + + + cpu1_cpu2_msg_fifo_full_watermark + cpu1_to_cpu2 message fifo full watermark (space avail intr based upon it) + 20 + 4 + read-write + + + + + CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG + CPU2 last message read (from cpu1) + 0x1E4 + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu2_rd_msg + CPU2 last message read (from cpu1) + 0 + 32 + read-only + + + + + CIU2_IMU_CPU2_WR_MSG_TO_CPU1 + CPU2 write message to CPU1 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + cpu2_wr_msg_cpu1 + Write CPU2 message data to CPU1 (push to FIFO) + 0 + 32 + read-write + + + + + CIU2_IMU_CPU2_RD_MSG_FROM_CPU1 + CPU2 read message from CPU1 + 0x1EC + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu2_rd_msg_cpu1 + CPU2 read message data from CPU1 (pop from FIFO) + 0 + 32 + read-only + + + + + CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS + CPU2 to CPU1 message FIFO status + 0x1F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu2_to_cpu1_msg_fifo_locked + cpu2_to_cpu1_msg_fifo_locked + 0 + 1 + read-only + + + cpu2_to_cpu1_msg_fifo_almost_full + cpu2_to_cpu1_msg_fifo_almost_full (based upon FIFO watermark) + 1 + 1 + read-only + + + cpu2_to_cpu1_msg_fifo_full + cpu2_to_cpu1_msg_fifo_full (based upon FIFO depth) + 2 + 1 + read-only + + + cpu2_to_cpu1_msg_fifo_empty + cpu2_to_cpu1_msg_fifo_empty + 3 + 1 + read-only + + + cpu2_to_cpu1_msg_count + cpu2_to_cpu1_msg_count + 4 + 5 + read-only + + + cpu2_to_cpu1_msg_fifo_wr_ptr + cpu1 to cpu2 msg fifo write pointer for debug + 16 + 4 + read-only + + + cpu2_to_cpu1_msg_fifo_rd_ptr + cpu1 to cpu2 msg fifo read pointer for debug + 20 + 4 + read-only + + + + + CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL + CPU2 to CPU1 message FIFO control + 0x1F4 + 32 + read-write + 0xF00000 + 0xFFFFFFFF + + + cpu2_msg_rdy_int_clr + Writing 1 to this bit will clear message ready interrupt to CPU2 (self clear bit) + 0 + 1 + read-write + + + cpu2_msg_sp_av_int_clr + Writing 1 to this bit will clear message space available interrupt to CPU2 (self clear bit) + 8 + 1 + read-write + + + cpu2_to_cpu1_msg_fifo_flush + Writing 1 to this bit will flush cpu2_to_cpu1 message fifo + 16 + 1 + read-write + + + cpu2_wait_for_ack + 1: CPU2 will wait for an ack for the next message to be written to CPU1 0: CPU2 will not wat for an ack for next message to be written to CPU1 + 17 + 1 + read-write + + + cpu2_cpu1_msg_fifo_full_watermark + cpu2_to_cpu1 message fifo full watermark (space avail intr based upon it) + 20 + 4 + read-write + + + + + CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG + CPU1 last message read (from cpu2) + 0x1F8 + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu1_rd_msg + CPU1 last message read (from cpu2) + 0 + 32 + read-only + + + + + CIU2_BCA1_CPU2_INT_MASK + BCA1 to CPU2 Interrupt Mask + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + imr + Interrupt Mask for BCA1 to CPU2 Interrupts + 0 + 32 + read-write + + + + + CIU2_BCA1_CPU2_INT_SELECT + BCA1 to CPU2 Interrupt Select + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + rsr + Interrupt Read/Write Clear for BCA1 to CPU2 Interrupts + 0 + 32 + read-write + + + + + CIU2_BCA1_CPU2_INT_EVENT_MASK + BCA1 to CPU2 Interrupt Event Mask + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + smr + Interrupt Event Mask for BCA1 to CPU2 Interrupts + 0 + 32 + read-write + + + + + CIU2_BCA1_CPU2_INT_STATUS + BCA1 to CPU2 Interrupt Status + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + isr + BCA1 to CPU2 Interrupt Status + 0 + 32 + read-only + + + + + CIU2_APU_BYPASS1 + CIU2 APU Bypass Register 1 + 0x210 + 32 + read-write + 0x77F + 0xFFFFFFFF + + + brf_clk_en_bypass_en + Firmware Bypass BRF_Clk_En + 0 + 1 + read-write + + + brf_clk_en_bypass_val + Firmware Bypass Value for BRF_Clk_En (active high signal) + 1 + 1 + read-write + + + bt_aes_clk_en_bypass_en + Firmware Bypass for Btu_Aes_Clk + 2 + 1 + read-write + + + bt_aes_clk_en_bypass_val + Firmware Bypass Value for Btu_Aes_Clk + 3 + 1 + read-write + + + soc_clk_en2_T1_bypass_en + Firmware Bypass for SoC_Clk_En2 + 4 + 1 + read-write + + + soc_clk_en2_T1_bypass_val + Firmware Bypass Value for SoC_Clk_En2(active high signal) + 5 + 1 + read-write + + + tbg_btu_clk_en_bypass_sel + TBG512_320_176_BTU_Clk_En_Sel to TBG512_320_176 of CAU + 6 + 2 + read-write + + + bt_aes_clk_sel_bypass_en + Firmware Bypass for Btu_Aes_Clk_Sel + 8 + 1 + read-write + + + bt_aes_clk_sel_bypass_val + Firmware Bypass Value for Btu_Aes_Clk_Sel + 9 + 1 + read-write + + + tbg_btu_clk_en_bypass_val + TBG512_320_176_BTU_Clk_En Bypass Value + 10 + 1 + read-write + + + + + CIU2_CPU2_LMU_STA_BYPASS0 + LMU static bank control byapss0 Register for CPU2 mem + 0x214 + 32 + read-write + 0xFF00FF + 0xFFFFFFFF + + + lmu_sta_banks_iso_en_bp_en + Firmware Bypass enable for lmu static banks iso_en + 0 + 8 + read-write + + + lmu_sta_banks_iso_en_bp_val + Firmware Bypass value for lmu static banks iso_en + 8 + 8 + read-write + + + lmu_sta_banks_psw_en_bp_en + Firmware Bypass enable for lmu static banks psw_en + 16 + 8 + read-write + + + lmu_sta_banks_psw_en_bp_val + Firmware Bypass value for lmu static banks psw_en + 24 + 8 + read-write + + + + + CIU2_CPU2_LMU_STA_BYPASS1 + LMU static bank control byapss1 Register for CPU2 + 0x218 + 32 + read-write + 0xFFFF00FF + 0xFFFFFFFF + + + lmu_sta_banks_sram_pd_bp_en + Firmware Bypass enable for lmu static banks sram_pd + 0 + 8 + read-write + + + lmu_sta_banks_sram_pd_bp_val + Firmware Bypass value for lmu static banks sram_pd + 8 + 8 + read-write + + + lmu_sta_banks_fnrst_bp_en + Firmware Bypass enable for lmu static banks fnrst + 16 + 8 + read-write + + + lmu_sta_banks_fnrst_bp_val + Firmware Bypass value for lmu static banks fnrst + 24 + 8 + read-write + + + + + CIU2_CPU2_LMU_STA_BYPASS2 + LMU static bank byapss2 Register for CPU2 + 0x21C + 32 + read-write + 0xFF + 0xFFFFFFFF + + + lmu_sta_banks_vddmc_sw_pd_ctrl_bp_en + Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl + 0 + 8 + read-write + + + lmu_sta_banks_vddmc_sw_pd_ctrl_bp_val + Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl + 8 + 8 + read-write + + + + + CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS + LMU G2Bist control byapss Register for CPU2 + 0x220 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + lmu_cpu2_sta_pwrdmn_rpr_req_bp_en + Firmware Bypass enable for CPU2 static banks lmu powerdomain repair request + 0 + 1 + read-write + + + lmu_cpu2_sta_pwrdmn_rpr_req_bp_val + Firmware Bypass value for CPU2 static banks lmu powerdomain repair request + 1 + 7 + read-write + + + + + CIU2_APU_PWR_CTRL_BYPASS1 + APU power control Bypass Register 1 + 0x22C + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + brf_psw_bypass_val + brf Power Switch Control + 0 + 1 + read-write + + + brf_psw_bypass_en + brf Power Switch Control Enable + 1 + 1 + read-write + + + brf_fwbar_bypass_val + brf Firewallbar Control + 2 + 1 + read-write + + + brf_fwbar_bypass_en + brf Firewallbar Control Enable + 3 + 1 + read-write + + + brf_iso_en_bypass_val + brf Isolation Cell Control + 4 + 1 + read-write + + + brf_iso_en_bypass_en + brf Isolation Cell Control Enable + 5 + 1 + read-write + + + brf_clk_div_rstb_bypass_val + Firmware Bypass Value for brf Clk_Div_Rstb (active low signal) + 6 + 1 + read-write + + + brf_clk_div_rstb_bypass_en + Firmware Bypass brf Clk_Div_Rstb from APU + 7 + 1 + read-write + + + brf_sram_pd_bypass_val + Firmware Bypass Value for SRAM_PD (active high signal) + 8 + 1 + read-write + + + brf_sram_pd_bypass_en + Firmware Bypass SRAM_PD from APU + 9 + 1 + read-write + + + + + CIU2_AHB2AHB_BRIDGE_CTRL + AHB2AHB Bridge Control Register + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + prefetch_hsel_en + ahb2ahb bridge pre-fetch hsel enable + 0 + 1 + read-write + + + + + CIU2_AHB1_AHB2_TO_CLEAR + AHB1 AHB2 timeout logic clear register + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + ahb2_timeout_clear + After the timeout happended on AHB2 bus, the cpu will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the AHB2 timeout logic to start recroding next transaction. This is self clearing bit + 8 + 1 + read-write + + + cpu2_dcode_inv_addr_clr + After the invalid address int happended on CPU2 dcode bus, the cpu2 will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the CPU2 Dcode invalid addr logic to start recroding next transaction. This is self clearing bit + 9 + 1 + read-write + + + cpu2_icode_inv_addr_clr + After the invalid address int happended on CPU2 icode bus, the cpu2 will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the CPU2 Icode invalid addr logic to start recroding next transaction. This is self clearing bit + 10 + 1 + read-write + + + + + CIU2_CPU_CPU2_DBG_STAT + CPU2 debug register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + cpu2_ro_status + cpu2 debug output + 0 + 32 + read-only + + + + + CIU2_CPU_CPU1_CTRL + CPU1 control register + 0x23C + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + cpu1_jtag_chain_bypass + 1 = Bypass the JTAG chain of CPU1 0 = The CPU1 remains in JTAG chain This bit is backup in case the CPU1 doesn't work on silicon + 17 + 1 + read-write + + + cpu1_cpu2_msg_scheme + 1 = new IMU based scheme (default) 0 = old ciu reg based scheme + 18 + 1 + read-write + + + cpu2_reset_int + cpu1 fw reset cpu2 + 31 + 1 + read-write + + + + + CIU2_TESTBUS_CTRL + CPU2 debug register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + testbus_sel + Select testbus debug output + 0 + 4 + read-write + + + + + CIU2_LBC_CTRL + LBC Control and Status + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + lbc_nco_en + LBC NCO Enable Signal + 0 + 1 + read-write + + + lbc_debug_ctrl + LBC Debug Control Signal + 5 + 2 + read-write + + + dejit_en + De-jitter Enable + 16 + 1 + read-write + + + auto_dejit + Auto de-jitter + 17 + 1 + read-write + + + man_sel_nco + Manual select NCO + 18 + 1 + read-write + + + nco_lpo_ramp_dn + Status nco_lpo_ramp_dn + 23 + 1 + read-only + + + ref_lpo_clk_good + Status ref_lpo_clk_good + 24 + 1 + read-only + + + ref_lpo_ramp_dn + Status ref_lpo_ramp_dn + 25 + 1 + read-only + + + lpo_clk_sel_fsm + Status lpo_clk_sel_fsm + 26 + 1 + read-only + + + lpo_clk_3k2_cnt + Status lpo_clk_3k2_cnt, 3.2KHz Count + 27 + 5 + read-only + + + + + CIU2_LBC_SLPCLK_NCO + LBC NCO Step for Sleep Clock + 0x254 + 32 + read-write + 0x19000000 + 0xFFFFFFFF + + + step + LBC NCO step for sleep clock. Please refer to design spreadsheet for more details. + 0 + 32 + read-write + + + + + + + FRO192M0 + FRO192 clock generator + FRO192M + 0x48980000 + + 0 + 0x200 + registers + + + + FROCCSR + FRO192 Clock Control Status Register + 0 + 32 + read-write + 0x2001 + 0xFFFFFFFF + + + FRODIV + FRO Clock Divide + 0 + 2 + read-only + + + DIV_1 + Divide by 1 + 0 + + + DIV_2 + Divide by 2 + 0x1 + + + DIV_3 + Divide by 3 + 0x2 + + + DIV_4 + Divide by 4 + 0x3 + + + + + POSTDIV_SEL + Post Divider Clock Select + 12 + 3 + read-write + + + POSTDIV_SEL_000 + FRO 16MHz Range selected. + 0 + + + POSTDIV_SEL_001 + FRO 24MHz Range selected + 0x1 + + + POSTDIV_SEL_010 + FRO 32MHz Range selected + 0x2 + + + POSTDIV_SEL_011 + FRO 48MHz Range selected + 0x3 + + + POSTDIV_SEL_100 + FRO 64MHz Range selected + 0x4 + + + + + VALID + Clock Valid Flag + 24 + 1 + read-only + + + INVALID + FRO192 is not enabled or clock is not valid. + 0 + + + VALID + FRO192 is enabled and output clock is valid. + 0x1 + + + + + + + FRODIV + FRO192 Divide Register + 0x4 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + FRODIV + FRO Clock Divide + 0 + 2 + read-write + + + DIV_1 + Divide by 1 + 0 + + + DIV_2 + Divide by 2 + 0x1 + + + DIV_3 + Divide by 3 + 0x2 + + + DIV_4 + Divide by 4 + 0x3 + + + + + + + + + RF_FMU + Flash + RF_FMU + 0x48981000 + + 0 + 0x30 + registers + + + RF_FMU + 51 + + + + FSTAT + Flash Status Register + 0 + 32 + read-write + 0x80 + 0xFFFFFFFE + + + FAIL + Command Fail Flag + 0 + 1 + read-only + + + FAIL_0 + Error not detected + 0 + + + FAIL_1 + Error detected + 0x1 + + + + + CMDABT + Command Abort Flag + 2 + 1 + read-write + oneToClear + + + CMDABT_0 + No command abort detected + 0 + + + CMDABT_1 + Command abort detected + 0x1 + + + + + PVIOL + Command Protection Violation Flag + 4 + 1 + read-write + oneToClear + + + PVIOL_0 + No protection violation detected + 0 + + + PVIOL_1 + Protection violation detected + 0x1 + + + + + ACCERR + Command Access Error Flag + 5 + 1 + read-write + oneToClear + + + ACCERR_0 + No access error detected + 0 + + + ACCERR_1 + Access error detected + 0x1 + + + + + CWSABT + Command Write Sequence Abort Flag + 6 + 1 + read-write + oneToClear + + + CWSABT_0 + Command write sequence not aborted + 0 + + + CWSABT_1 + Command write sequence aborted + 0x1 + + + + + CCIF + Command Complete Interrupt Flag + 7 + 1 + read-write + oneToClear + + + CCIF_0 + Flash command, initialization, or power mode recovery in progress + 0 + + + CCIF_1 + Flash command, initialization, or power mode recovery has completed + 0x1 + + + + + CMDPRT + Command protection level + 8 + 2 + read-only + + + CMDPRT_0 + Secure, normal access + 0 + + + CMDPRT_1 + Secure, privileged access + 0x1 + + + CMDPRT_2 + Nonsecure, normal access + 0x2 + + + CMDPRT_3 + Nonsecure, privileged access + 0x3 + + + + + CMDP + Command protection status flag + 11 + 1 + read-only + + + CMDP_0 + Command protection level and domain ID are stale + 0 + + + CMDP_1 + Command protection level (CMDPRT) and domain ID (CMDDID) are set + 0x1 + + + + + CMDDID + Command domain ID + 12 + 4 + read-only + + + DFDIF + Double Bit Fault Detect Interrupt Flag + 16 + 1 + read-write + oneToClear + + + DFDIF_0 + Double bit fault not detected during a valid flash read access + 0 + + + DFDIF_1 + Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + 0x1 + + + + + SALV_USED + Salvage Used for Erase operation + 17 + 1 + read-only + + + SALV_USED_0 + Salvage not used during last operation + 0 + + + SALV_USED_1 + Salvage used during the last erase operation + 0x1 + + + + + PEWEN + Program-Erase Write Enable Control + 24 + 2 + read-only + + + PEWEN_0 + Writes are not enabled + 0 + + + PEWEN_1 + Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + 0x1 + + + PEWEN_2 + Writes are enabled for one flash or IFR page (page programming) + 0x2 + + + + + PERDY + Program-Erase Ready Status Flag + 31 + 1 + read-write + oneToClear + + + PERDY_0 + Program or sector erase command operation not stalled + 0 + + + PERDY_1 + Program or sector erase command operation ready to execute + 0x1 + + + + + + + FCNFG + Flash Configuration Register + 0x4 + 32 + read-write + 0 + 0xFFFFFF + + + CCIE + Command Complete Interrupt Enable + 7 + 1 + read-write + + + CCIE_0 + Command complete interrupt disabled + 0 + + + CCIE_1 + Command complete interrupt enabled + 0x1 + + + + + ERSREQ + Mass Erase Request + 8 + 1 + read-only + + + ERSREQ_0 + No request or request complete + 0 + + + ERSREQ_1 + Request to run the Mass Erase operation + 0x1 + + + + + DFDIE + Double Bit Fault Detect Interrupt Enable + 16 + 1 + read-write + + + DFDIE_0 + Double bit fault detect interrupt disabled + 0 + + + DFDIE_1 + Double bit fault detect interrupt enabled + 0x1 + + + + + ERSIEN0 + Erase IFR Sector Enable - Block 0 + 24 + 4 + read-only + + + ERSIEN0_0 + Block 0 IFR Sector X is protected from erase by ERSSCR command + 0 + + + ERSIEN0_1 + Block 0 IFR Sector X is not protected from erase by ERSSCR command + 0x1 + + + + + ERSIEN1 + Erase IFR Sector Enable - Block 1 (for dual block configs) + 28 + 4 + read-only + + + ERSIEN1_0 + Block 1 IFR Sector X is protected from erase by ERSSCR command + 0 + + + ERSIEN1_1 + Block 1 IFR Sector X is not protected from erase by ERSSCR command + 0x1 + + + + + + + FCTRL + Flash Control Register + 0x8 + 32 + read-write + 0x100 + 0xFFFFFFF0 + + + RWSC + Read Wait-State Control + 0 + 4 + read-write + + + LSACTIVE + Low speed active mode + 8 + 1 + read-write + + + LSACTIVE_0 + Full speed active mode requested + 0 + + + LSACTIVE_1 + Low speed active mode requested + 0x1 + + + + + FDFD + Force Double Bit Fault Detect + 16 + 1 + read-write + + + FDFD_0 + FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + 0 + + + FDFD_1 + FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. + 0x1 + + + + + ABTREQ + Abort Request + 24 + 1 + read-write + + + ABTREQ_0 + No request to abort a command write sequence + 0 + + + ABTREQ_1 + Request to abort a command write sequence + 0x1 + + + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + FCCOB%s + Flash Common Command Object Registers + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCOBn + CCOBn + 0 + 32 + read-write + + + + + + + RF_FMCCFG + RadioFlash + RF_FMCCFG + 0x48982000 + + 0 + 0x4 + registers + + + + RFMCCFG + Radio Flash Memory Controller Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFCF0 + Radio Flash Control Field 0 + 0 + 2 + read-write + + + RFCF1 + Radio Flash Control Field 1 + 2 + 2 + read-write + + + RFCF2 + Radio Flash Control Field 2 + 4 + 3 + read-write + + + RFCF3 + Radio Flash Control Field 3 + 8 + 4 + read-write + + + + + + + RF_CMC1 + RF_CMC + RF_CMC1 + 0x48983000 + + 0 + 0x18 + registers + + + + RADIO_LP + Radio Low Power Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEP_EN + Sleep Enable + 0 + 1 + read-write + + + BLE_WKUP + Bluetooth Wakeup + 1 + 1 + read-write + + + CK + Clock Control + 2 + 2 + read-write + + + CK_0 + Normal configuration. When NBU CPU executes WFI and SLEEP_EN=1 (or if NBU CPU reset is asserted), and a sleep request from RFMC (LP_ENTER) NBU, MAN or WOR is asserted, the flash is put in low power, the sleep_rdy to RFMC asserts and the FRO will be disabled. + 0 + + + CK_1 + Configuration where NBU, FRO and flash are not used. When NBU CPU reset is asserted, or NBU CPU executes WFI and SLEEP_EN=1, the flash will be placed in low power, the FRO disabled, the sleep_rdy to RFMC will assert and the NBU CM3 and AHB clocks will be gated off. The RF_CMC and NBU CPU will be without a clock until the next reset, but low power requests (RFMC LP_ENTER, MAN or WOR) will by accepted by RFMC since RF_CMC's sleep_rdy output will remain asserted. + 0x1 + + + CK_2 + Configuration where NBU CPU is not used but FRO and flash can still be used. When NBU CPU reset is asserted, or NBU CPU executes WFI and SLEEP_EN=1, the clock to the NBU CPU will be gated. When RFMC (LP_ENTER), MAN or WOR request sleep, the flash is put in low power, the sleep_rdy to RFMC asserts and the FRO will be disabled as in configuration 00. + 0x2 + + + + + + + SOC_LP + SOC Low Power Control and Status Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUS_REQ + Bus Access Request + 0 + 1 + read-write + + + BUS_AWAKE + Bus Awake + 4 + 1 + read-only + + + + + IRQ_CTRL + Interrupt Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDY_FLAG + XTAL Ready Flag + 0 + 1 + read-write + oneToClear + + + RDY_IE + XTAL Ready Interrupt Enable + 4 + 1 + read-write + + + XTAL_RDY + XTAL Ready + 8 + 1 + read-only + + + + + TPM2_CFG + TPM2 Configuration Register + 0xC + 32 + read-write + 0x800 + 0xFFFFFFFF + + + CH0_MUX_SEL + Channel0 Input Mux Select + 0 + 1 + read-write + + + CH0_MUX_SEL_0 + TPM2_CH0 pin + 0 + + + CH0_MUX_SEL_1 + tof_timestamp_trig signal from radio + 0x1 + + + + + CH1_MUX_SEL + Channel1 Input Mux Select + 4 + 4 + read-write + + + CH1_MUX_SEL_0 + TPM2_CH1 pin + 0 + + + CH1_MUX_SEL_1 + dtest[0] signal from radio + 0x1 + + + CH1_MUX_SEL_2 + dtest[1] signal from radio + 0x2 + + + CH1_MUX_SEL_3 + dtest[2] signal from radio + 0x3 + + + CH1_MUX_SEL_4 + dtest[3] signal from radio + 0x4 + + + CH1_MUX_SEL_5 + dtest[4] signal from radio + 0x5 + + + CH1_MUX_SEL_6 + dtest[5] signal from radio + 0x6 + + + CH1_MUX_SEL_7 + dtest[6] signal from radio + 0x7 + + + CH1_MUX_SEL_8 + dtest[7] signal from radio + 0x8 + + + CH1_MUX_SEL_9 + dtest[8] signal from radio + 0x9 + + + CH1_MUX_SEL_10 + dtest[9] signal from radio + 0xA + + + CH1_MUX_SEL_11 + dtest[10] signal from radio + 0xB + + + CH1_MUX_SEL_12 + dtest[11] signal from radio + 0xC + + + CH1_MUX_SEL_13 + dtest[12] signal from radio + 0xD + + + CH1_MUX_SEL_14 + dtest[13] signal from radio + 0xE + + + + + CGC + Clock Gate Control + 8 + 1 + read-write + + + CGC_0 + TPM2 clock disabled + 0 + + + CGC_1 + TPM2 clock enabled + 0x1 + + + + + CLK_MUX_SEL + Clock Mux Select + 10 + 2 + read-write + + + CLK_MUX_SEL_0 + No clock + 0 + + + CLK_MUX_SEL_1 + Core Clock + 0x1 + + + CLK_MUX_SEL_2 + Radio Oscillator + 0x2 + + + + + + + RADIO_TRIM + Radio Trim Register + 0x10 + 32 + read-write + 0x73 + 0xFFFFFFFF + + + BG_TRIM + Bandgap Trim + 0 + 3 + read-write + + + BG_TRIM_0 + 787mV + 0 + + + BG_TRIM_1 + 794mV + 0x1 + + + BG_TRIM_2 + 800mV + 0x2 + + + BG_TRIM_3 + 806mV + 0x3 + + + BG_TRIM_4 + 812mV + 0x4 + + + BG_TRIM_5 + 819mV + 0x5 + + + BG_TRIM_6 + 825mV + 0x6 + + + BG_TRIM_7 + 831mV + 0x7 + + + + + CM3_PHANTOM + CM3 Phantom + 4 + 3 + read-only + + + CM3_PHANTOM_2 + CM3 disabled. The RF_CMC will hold the CM3 in reset + 0x2 + + + CM3_PHANTOM_7 + CM3 enabled. + 0x7 + + + + + + + RAM_PWR + RAM Power Control register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SD_EN + Shut Down Enable + 0 + 11 + read-write + + + DS_EN + Deep Sleep Enable + 16 + 11 + read-write + + + + + + + TPM2 + TPM + TPM + 0x48984000 + + 0 + 0x88 + registers + + + + VERID + Version ID + 0 + 32 + read-only + 0x6000003 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + STANDARD + Standard feature set. + 0x1 + + + FILT_COMBINE + Standard feature set with Filter and Combine registers implemented. + 0x3 + + + QUAD + Standard feature set with Quadrature registers implemented. + 0x5 + + + FILT_COMBINE_QUAD + Standard feature set with Filter, Combine and Quadrature registers implemented. + 0x7 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter + 0x4 + 32 + read-only + 0x200402 + 0xFFFFFFFF + + + CHAN + Channel Count + 0 + 8 + read-only + + + TRIG + Trigger Count + 8 + 8 + read-only + + + WIDTH + Counter Width + 16 + 8 + read-only + + + + + GLOBAL + TPM Global + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + NOUPDATE + No Update + 0 + 1 + read-write + + + NOUPDATE_0 + Internal double buffered registers update as normal. + 0 + + + NOUPDATE_1 + Internal double buffered registers do not update. + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + NOT_RESET + Module is not reset. + 0 + + + RESET + Module is reset. + 0x1 + + + + + + + SC + Status and Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Prescale Factor Selection + 0 + 3 + read-write + + + DIV_1 + Divide by 1 + 0 + + + DIV_2 + Divide by 2 + 0x1 + + + DIV_4 + Divide by 4 + 0x2 + + + DIV_8 + Divide by 8 + 0x3 + + + DIV_16 + Divide by 16 + 0x4 + + + DIV_32 + Divide by 32 + 0x5 + + + DIV_64 + Divide by 64 + 0x6 + + + DIV_128 + Divide by 128 + 0x7 + + + + + CMOD + Clock Mode Selection + 3 + 2 + read-write + + + DISABLE + TPM counter is disabled + 0 + + + COUNTER + TPM counter increments on every TPM counter clock + 0x1 + + + EXTCLK + TPM counter increments on rising edge of EXTCLK synchronized to the TPM counter clock + 0x2 + + + TRIG + TPM counter increments on rising edge of the selected external input trigger. + 0x3 + + + + + CPWMS + Center-Aligned PWM Select + 5 + 1 + read-write + + + UP + TPM counter operates in up counting mode. + 0 + + + UP_DOWN + TPM counter operates in up-down counting mode. + 0x1 + + + + + TOIE + Timer Overflow Interrupt Enable + 6 + 1 + read-write + + + DISABLE + Disable TOF interrupts. Use software polling or DMA request. + 0 + + + ENABLE + Enable TOF interrupts. An interrupt is generated when TOF equals one. + 0x1 + + + + + TOF + Timer Overflow Flag + 7 + 1 + read-write + oneToClear + + + NO_OVERFLOW + TPM counter has not overflowed. + 0 + + + OVERFLOW + TPM counter has overflowed. + 0x1 + + + + + DMA + DMA Enable + 8 + 1 + read-write + + + DISABLE + Disables DMA transfers. + 0 + + + ENABLE + Enables DMA transfers. + 0x1 + + + + + + + CNT + Counter + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Counter value + 0 + 32 + read-write + + + + + MOD + Modulo + 0x18 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + MOD + Modulo value + 0 + 32 + read-write + + + + + STATUS + Capture and Compare Status + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + oneToClear + + + CH0F + Channel 0 Flag + 0 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + CH1F + Channel 1 Flag + 1 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + TOF + Timer Overflow Flag + 8 + 1 + read-write + oneToClear + + + NO_OVERFLOW + TPM counter has not overflowed. + 0 + + + OVERFLOW + TPM counter has overflowed. + 0x1 + + + + + + + 2 + 0x8 + CHANNEL[%s] + no description available + 0x20 + + CSC + Channel (n) Status and Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA + DMA Enable + 0 + 1 + read-write + + + DISABLE + Disable DMA transfers. + 0 + + + ENABLE + Enable DMA transfers. + 0x1 + + + + + ELSA + Edge or Level Select + 2 + 1 + read-write + + + ELSB + Edge or Level Select + 3 + 1 + read-write + + + MSA + Channel Mode Select + 4 + 1 + read-write + + + MSB + Channel Mode Select + 5 + 1 + read-write + + + CHIE + Channel Interrupt Enable + 6 + 1 + read-write + + + DISABLE + Disable channel interrupts. + 0 + + + ENABLE + Enable channel interrupts. + 0x1 + + + + + CHF + Channel Flag + 7 + 1 + read-write + oneToClear + + + NO_EVENT + No channel event has occurred. + 0 + + + EVENT + A channel event has occurred. + 0x1 + + + + + + + CV + Channel (n) Value + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + Channel Value + 0 + 32 + read-write + + + + + + COMBINE + Combine Channel Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMBINE0 + Combine Channels 0 and 1 + 0 + 1 + read-write + + + NO_COMBINE + Channels 0 and 1 are independent. + 0 + + + COMBINE + Channels 0 and 1 are combined. + 0x1 + + + + + COMSWAP0 + Combine Channel 0 and 1 Swap + 1 + 1 + read-write + + + NO_SWAP + Even channel is used for input capture and 1st compare. + 0 + + + SWAP + Odd channel is used for input capture and 1st compare. + 0x1 + + + + + + + FILTER + Filter Control + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0FVAL + Channel 0 Filter Value + 0 + 4 + read-write + + + CH1FVAL + Channel 1 Filter Value + 4 + 4 + read-write + + + + + CONF + Configuration + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOZEEN + Doze Enable + 5 + 1 + read-write + + + COUNT + Internal TPM counter continues. + 0 + + + NO_COUNT + Internal TPM counter is paused and does not increment. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. + 0x1 + + + + + DBGMODE + Debug Mode + 6 + 2 + read-write + + + NO_COUNT + TPM counter is paused and does not increment. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. + 0 + + + COUNT + TPM counter continues. + 0x3 + + + + + GTBEEN + Global time base enable + 9 + 1 + read-write + + + DISABLE + All channels use the internally generated TPM counter as their timebase + 0 + + + ENABLE + All channels use an externally generated global timebase as their timebase + 0x1 + + + + + + + + + ZLL + ZLL + ZLL + 0x48A01000 + + 0 + 0xB0 + registers + + + + IRQSTS + INTERRUPT REQUEST STATUS + 0 + 32 + read-write + 0xF00000 + 0x80F00000 + + + SEQIRQ + Sequencer IRQ + 0 + 1 + read-write + oneToClear + + + SEQIRQ_0 + A Sequencer Interrupt has not occurred + 0 + + + SEQIRQ_1 + A Sequencer Interrupt has occurred + 0x1 + + + + + TXIRQ + TX IRQ + 1 + 1 + read-write + oneToClear + + + TXIRQ_0 + A TX Interrupt has not occurred + 0 + + + TXIRQ_1 + A TX Interrupt has occurred + 0x1 + + + + + RXIRQ + RX IRQ + 2 + 1 + read-write + oneToClear + + + RXIRQ_0 + A RX Interrupt has not occurred + 0 + + + RXIRQ_1 + A RX Interrupt has occurred + 0x1 + + + + + CCAIRQ + CCA IRQ + 3 + 1 + read-write + oneToClear + + + CCAIRQ_0 + A CCA Interrupt has not occurred + 0 + + + CCAIRQ_1 + A CCA Interrupt has occurred + 0x1 + + + + + RXWTRMRKIRQ + Receive Watermark IRQ + 4 + 1 + read-write + oneToClear + + + RXWTRMRKIRQ_0 + A Receive Watermark Interrupt has not occurred + 0 + + + RXWTRMRKIRQ_1 + A Receive Watermark Interrupt has occurred + 0x1 + + + + + FILTERFAIL_IRQ + Filter Fail IRQ + 5 + 1 + read-write + oneToClear + + + FILTERFAIL_IRQ_0 + A Filter Fail Interrupt has not occurred + 0 + + + FILTERFAIL_IRQ_1 + A Filter Fail Interrupt has occurred + 0x1 + + + + + PLL_UNLOCK_IRQ + PLL Unlock IRQ + 6 + 1 + read-write + oneToClear + + + PLL_UNLOCK_IRQ_0 + A PLL Unlock Interrupt has not occurred + 0 + + + PLL_UNLOCK_IRQ_1 + A PLL Unlock Interrupt has occurred + 0x1 + + + + + RX_FRM_PEND + RX Frame Pending + 7 + 1 + read-only + + + WAKE_IRQ + WAKE Interrupt Request + 8 + 1 + read-write + oneToClear + + + WAKE_IRQ_0 + A Wake Interrupt has not occurred + 0 + + + WAKE_IRQ_1 + A Wake Interrupt has occurred + 0x1 + + + + + ARB_GRANT_DEASSERTION_IRQ + arb_grant Deassertion IRQ + 9 + 1 + read-write + oneToClear + + + ARB_GRANT_DEASSERTION_IRQ_0 + An arb_grant Deassertion Interrupt has not occurred + 0 + + + ARB_GRANT_DEASSERTION_IRQ_1 + An arb_grant Deassertion Interrupt has occurred + 0x1 + + + + + TSM_IRQ + TSM IRQ + 10 + 1 + read-only + + + TSM_IRQ_0 + A TSM Interrupt has not occurred + 0 + + + TSM_IRQ_1 + A TSM Interrupt has occurred + 0x1 + + + + + ENH_PKT_STATUS + Enhanced Packet Status + 11 + 1 + read-only + + + ENH_PKT_STATUS_0 + The last packet received was neither 4e- nor 2015-compliant + 0 + + + ENH_PKT_STATUS_1 + The last packet received was 4e- or 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits) + 0x1 + + + + + PI + Poll Indication + 12 + 1 + read-only + + + PI_0 + the received packet was not a data request + 0 + + + PI_1 + the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not + 0x1 + + + + + SRCADDR + Source Address Match Status + 13 + 1 + read-only + + + CCA + CCA Status + 14 + 1 + read-only + + + CCA_0 + IDLE + 0 + + + CCA_1 + BUSY + 0x1 + + + + + CRCVALID + CRC Valid Status + 15 + 1 + read-only + + + CRCVALID_0 + Rx FCS != calculated CRC (incorrect) + 0 + + + CRCVALID_1 + Rx FCS = calculated CRC (correct) + 0x1 + + + + + TMR1IRQ + Timer 1 IRQ + 16 + 1 + read-write + oneToClear + + + TMR2IRQ + Timer 2 IRQ + 17 + 1 + read-write + oneToClear + + + TMR3IRQ + Timer 3 IRQ + 18 + 1 + read-write + oneToClear + + + TMR4IRQ + Timer 4 IRQ + 19 + 1 + read-write + oneToClear + + + TMR1MSK + Timer Comparator 1 Interrupt Mask bit + 20 + 1 + read-write + + + TMR1MSK_0 + allows interrupt when comparator matches event timer count + 0 + + + TMR1MSK_1 + Interrupt generation is disabled, but a TMR1IRQ flag can be set + 0x1 + + + + + TMR2MSK + Timer Comparator 2 Interrupt Mask bit + 21 + 1 + read-write + + + TMR2MSK_0 + allows interrupt when comparator matches event timer count + 0 + + + TMR2MSK_1 + Interrupt generation is disabled, but a TMR2IRQ flag can be set + 0x1 + + + + + TMR3MSK + Timer Comparator 3 Interrupt Mask bit + 22 + 1 + read-write + + + TMR3MSK_0 + allows interrupt when comparator matches event timer count + 0 + + + TMR3MSK_1 + Interrupt generation is disabled, but a TMR3IRQ flag can be set + 0x1 + + + + + TMR4MSK + Timer Comparator 4 Interrupt Mask bit + 23 + 1 + read-write + + + TMR4MSK_0 + allows interrupt when comparator matches event timer count + 0 + + + TMR4MSK_1 + Interrupt generation is disabled, but a TMR4IRQ flag can be set + 0x1 + + + + + RX_FRAME_LENGTH + Receive Frame Length + 24 + 7 + read-only + + + + + PHY_CTRL + PHY CONTROL + 0x4 + 32 + read-write + 0x807FF00 + 0xFFFFFFFF + + + XCVSEQ + 802.15.4 Transceiver Sequence Selector + 0 + 3 + read-write + + + XCVSEQ_0 + I (IDLE) + 0 + + + XCVSEQ_1 + R (RECEIVE) + 0x1 + + + XCVSEQ_2 + T (TRANSMIT) + 0x2 + + + XCVSEQ_3 + C (CCA) + 0x3 + + + XCVSEQ_4 + TR (TRANSMIT/RECEIVE) + 0x4 + + + XCVSEQ_5 + CCCA (CONTINUOUS CCA) + 0x5 + + + + + AUTOACK + Auto Acknowledge Enable + 3 + 1 + read-write + + + AUTOACK_0 + sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. + 0 + + + AUTOACK_1 + sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. + 0x1 + + + + + RXACKRQD + Receive Acknowledge Frame required + 4 + 1 + read-write + + + RXACKRQD_0 + An ordinary receive frame (any type of frame) follows the transmit frame. + 0 + + + RXACKRQD_1 + A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). + 0x1 + + + + + CCABFRTX + CCA Before TX + 5 + 1 + read-write + + + CCABFRTX_0 + no CCA required, transmit operation begins immediately. + 0 + + + CCABFRTX_1 + at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). + 0x1 + + + + + SLOTTED + Slotted Mode + 6 + 1 + read-write + + + TMRTRIGEN + Timer2 Trigger Enable + 7 + 1 + read-write + + + TMRTRIGEN_0 + programmed sequence initiates immediately upon write to XCVSEQ. + 0 + + + TMRTRIGEN_1 + allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register). + 0x1 + + + + + SEQMSK + Sequencer Interrupt Mask + 8 + 1 + read-write + + + SEQMSK_0 + allows completion of an autosequence to generate a zigbee interrupt + 0 + + + SEQMSK_1 + Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + TXMSK + TX Interrupt Mask + 9 + 1 + read-write + + + TXMSK_0 + allows completion of a TX operation to generate a zigbee interrupt + 0 + + + TXMSK_1 + Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + RXMSK + RX Interrupt Mask + 10 + 1 + read-write + + + RXMSK_0 + allows completion of a RX operation to generate a zigbee interrupt + 0 + + + RXMSK_1 + Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + CCAMSK + CCA Interrupt Mask + 11 + 1 + read-write + + + CCAMSK_0 + allows completion of a CCA operation to generate a zigbee interrupt + 0 + + + CCAMSK_1 + Completion of a CCA operation will set the CCA status bit, but a zigbee interrupt is not generated + 0x1 + + + + + RX_WMRK_MSK + RX Watermark Interrupt Mask + 12 + 1 + read-write + + + RX_WMRK_MSK_0 + allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt + 0 + + + RX_WMRK_MSK_1 + A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + FILTERFAIL_MSK + FilterFail Interrupt Mask + 13 + 1 + read-write + + + FILTERFAIL_MSK_0 + allows Packet Processor Filtering Failure to generate a zigbee interrupt + 0 + + + FILTERFAIL_MSK_1 + A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + PLL_UNLOCK_MSK + PLL Unlock Interrupt Mask + 14 + 1 + read-write + + + PLL_UNLOCK_MSK_0 + allows PLL unlock event to generate a zigbee interrupt + 0 + + + PLL_UNLOCK_MSK_1 + A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + CRC_MSK + CRC Mask + 15 + 1 + read-write + + + CRC_MSK_0 + sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received. + 0 + + + CRC_MSK_1 + sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received. + 0x1 + + + + + WAKE_MSK + Mask wakeup from DSM + 16 + 1 + read-write + + + WAKE_MSK_0 + Allows a wakeup from DSM to generate a zigbee interrupt + 0 + + + WAKE_MSK_1 + Wakeup from DSM will set the WAKE_IRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + ARB_GRANT_DEASSERTION_MSK + arb_grant Deassertion Interrupt Mask + 17 + 1 + read-write + + + ARB_GRANT_DEASSERTION_MSK_0 + allows arb_grant deassertion event to generate a zigbee interrupt + 0 + + + ARB_GRANT_DEASSERTION_MSK_1 + An arb_grant deassertion event will set the ARB_GRANT_DEASSERTION_IRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + TSM_MSK + Mask generating interrupt from TSM + 18 + 1 + read-write + + + TSM_MSK_0 + allows assertion of a TSM interrupt to generate a zigbee interrupt + 0 + + + TSM_MSK_1 + Assertion of a TSM interrupt will set the TSM_IRQ status bit, but a zigbee interrupt is not generated + 0x1 + + + + + TMR1CMP_EN + Timer 1 Compare Enable + 20 + 1 + read-write + + + TMR1CMP_EN_0 + Don't allow an Event Timer Match to T1CMP to set TMR1IRQ + 0 + + + TMR1CMP_EN_1 + Allow an Event Timer Match to T1CMP to set TMR1IRQ + 0x1 + + + + + TMR2CMP_EN + Timer 2 Compare Enable + 21 + 1 + read-write + + + TMR2CMP_EN_0 + Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ + 0 + + + TMR2CMP_EN_1 + Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ + 0x1 + + + + + TMR3CMP_EN + Timer 3 Compare Enable + 22 + 1 + read-write + + + TMR3CMP_EN_0 + Don't allow an Event Timer Match to T3CMP to set TMR3IRQ + 0 + + + TMR3CMP_EN_1 + Allow an Event Timer Match to T3CMP to set TMR3IRQ + 0x1 + + + + + TMR4CMP_EN + Timer 4 Compare Enable + 23 + 1 + read-write + + + TMR4CMP_EN_0 + Don't allow an Event Timer Match to T4CMP to set TMR4IRQ + 0 + + + TMR4CMP_EN_1 + Allow an Event Timer Match to T4CMP to set TMR4IRQ + 0x1 + + + + + TC2PRIME_EN + Timer 2 Prime Compare Enable + 24 + 1 + read-write + + + TC2PRIME_EN_0 + Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ + 0 + + + TC2PRIME_EN_1 + Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ + 0x1 + + + + + PROMISCUOUS + Promiscuous Mode Enable + 25 + 1 + read-write + + + PROMISCUOUS_0 + normal mode + 0 + + + PROMISCUOUS_1 + all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed. + 0x1 + + + + + TC3_POSTPONE_ON_SFD + Postpone TC3 Timeout On SFD Enable + 26 + 1 + read-write + + + TC3_POSTPONE_ON_SFD_0 + TC3 Abort will occur on TMR3 timeout, regardless of rx_sfd_detect + 0 + + + TC3_POSTPONE_ON_SFD_1 + TC3 Abort will be deferred on TMR3 timeout if rx_sfd_detect is asserted; otherwise the TC3 Abort will occur immediately + 0x1 + + + + + CCATYPE + Clear Channel Assessment Type + 27 + 2 + read-write + + + CCATYPE_0 + ENERGY DETECT + 0 + + + CCATYPE_1 + CCA MODE 1 + 0x1 + + + CCATYPE_2 + CCA MODE 2 + 0x2 + + + CCATYPE_3 + CCA MODE 3 + 0x3 + + + + + PANCORDNTR0 + Device is a PAN Coordinator on PAN0 + 29 + 1 + read-write + + + TC3TMOUT + TMR3 Timeout Enable + 30 + 1 + read-write + + + TC3TMOUT_0 + TMR3 is a software timer only + 0 + + + TC3TMOUT_1 + Enable TMR3 to abort Rx or CCCA operations. + 0x1 + + + + + TRCV_MSK + Transceiver Global Interrupt Mask + 31 + 1 + read-write + + + TRCV_MSK_0 + Enable any unmasked interrupt source to assert zigbee interrupt + 0 + + + TRCV_MSK_1 + Mask all interrupt sources from asserting zigbee interrupt + 0x1 + + + + + + + EVENT_TMR + EVENT TIMER + 0x8 + 32 + read-write + 0 + 0xF + + + EVENT_TMR_LD + Event Timer Load Enable + 0 + 1 + write-only + + + EVENT_TMR_ADD + Event Timer Add Enable + 1 + 1 + write-only + + + EVENT_TMR_FRAC + Event Timer Fractional Component + 4 + 4 + read-write + + + EVENT_TMR + Event Timer Integer Component + 8 + 24 + read-write + + + + + TIMESTAMP + TIMESTAMP + 0xC + 32 + read-only + 0 + 0xF + + + TIMESTAMP_FRAC + Timestamp Fractional + 4 + 4 + read-only + + + TIMESTAMP + Timestamp + 8 + 24 + read-only + + + + + T1CMP + T1 COMPARE + 0x10 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + T1CMP + TMR1 Compare Value + 0 + 24 + read-write + + + + + T2CMP + T2 COMPARE + 0x14 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + T2CMP + TMR2 Compare Value + 0 + 24 + read-write + + + + + T2PRIMECMP + T2 PRIME COMPARE + 0x18 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + T2PRIMECMP + TMR2 Prime Compare Value + 0 + 16 + read-write + + + + + T3CMP + T3 COMPARE + 0x1C + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + T3CMP + TMR3 Compare Value + 0 + 24 + read-write + + + + + T4CMP + T4 COMPARE + 0x20 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + T4CMP + TMR4 Compare Value + 0 + 24 + read-write + + + + + PA_PWR + PA POWER + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PA_PWR + PA Power + 0 + 7 + read-write + + + EXT_PA_PWR + External PA Power + 16 + 7 + read-only + + + EXT_PA_PWR_CHG + External PA Power Change Flag + 31 + 1 + read-write + oneToClear + + + + + CHANNEL_NUM0 + CHANNEL NUMBER 0 + 0x28 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + CHANNEL_NUM0 + Channel Number for PAN0 + 0 + 7 + read-write + + + + + LQI_AND_RSSI + LQI AND RSSI + 0x2C + 32 + read-only + 0 + 0xFF000000 + + + LQI_VALUE + LQI Value + 0 + 8 + read-only + + + RSSI + RSSI Value + 8 + 8 + read-only + + + CCA1_ED_FNL + Final Result for CCA Mode 1 and Energy Detect + 16 + 8 + read-only + + + + + MACSHORTADDRS0 + MAC SHORT ADDRESS 0 + 0x30 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACPANID0 + MAC PAN ID for PAN0 + 0 + 16 + read-write + + + MACSHORTADDRS0 + MAC SHORT ADDRESS FOR PAN0 + 16 + 16 + read-write + + + + + MACLONGADDRS0_LSB + MAC LONG ADDRESS 0 LSB + 0x34 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS0_LSB + MAC LONG ADDRESS for PAN0 LSB + 0 + 32 + read-write + + + + + MACLONGADDRS0_MSB + MAC LONG ADDRESS 0 MSB + 0x38 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS0_MSB + MAC LONG ADDRESS for PAN0 MSB + 0 + 32 + read-write + + + + + RX_FRAME_FILTER + RECEIVE FRAME FILTER + 0x3C + 32 + read-write + 0x30F + 0xFF40FFFF + + + BEACON_FT + Beacon Frame Type Enable + 0 + 1 + read-write + + + BEACON_FT_0 + reject all Beacon frames + 0 + + + BEACON_FT_1 + Beacon frame type enabled. + 0x1 + + + + + DATA_FT + Data Frame Type Enable + 1 + 1 + read-write + + + DATA_FT_0 + reject all Beacon frames + 0 + + + DATA_FT_1 + Data frame type enabled. + 0x1 + + + + + ACK_FT + Ack Frame Type Enable + 2 + 1 + read-write + + + ACK_FT_0 + reject all Acknowledge frames + 0 + + + ACK_FT_1 + Acknowledge frame type enabled. + 0x1 + + + + + CMD_FT + MAC Command Frame Type Enable + 3 + 1 + read-write + + + CMD_FT_0 + reject all MAC Command frames + 0 + + + CMD_FT_1 + MAC Command frame type enabled. + 0x1 + + + + + LLDN_FT + LLDN Frame Type Enable + 4 + 1 + read-write + + + LLDN_FT_0 + reject all LLDN frames + 0 + + + LLDN_FT_1 + LLDN frame type enabled (Frame Type 4). + 0x1 + + + + + MULTIPURPOSE_FT + Multipurpose Frame Type Enable + 5 + 1 + read-write + + + MULTIPURPOSE_FT_0 + reject all Multipurpose frames + 0 + + + MULTIPURPOSE_FT_1 + Multipurpose frame type enabled (Frame Type 5). + 0x1 + + + + + NS_FT + "Not Specified" Frame Type Enable + 6 + 1 + read-write + + + NS_FT_0 + reject all "Not Specified" frames + 0 + + + NS_FT_1 + Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this Frame Type + 0x1 + + + + + EXTENDED_FT + Extended Frame Type Enable + 7 + 1 + read-write + + + EXTENDED_FT_0 + reject all Extended frames + 0 + + + EXTENDED_FT_1 + Extended frame type enabled (Frame Type 7). + 0x1 + + + + + FRM_VER_FILTER + Frame Version selector. + 8 + 4 + read-write + + + ACTIVE_PROMISCUOUS + Active Promiscuous + 14 + 1 + read-write + + + ACTIVE_PROMISCUOUS_0 + normal operation + 0 + + + ACTIVE_PROMISCUOUS_1 + Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode + 0x1 + + + + + EXTENDED_FCS_CHK + Verify FCS on Frame Type Extended + 15 + 1 + read-write + + + EXTENDED_FCS_CHK_0 + Packet Processor will not check FCS for Frame Type EXTENDED (default) + 0 + + + EXTENDED_FCS_CHK_1 + Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED + 0x1 + + + + + FV2_BEACON_RECD + Frame Version 2 Beacon Packet Received + 16 + 1 + read-only + + + FV2_BEACON_RECD_0 + The last packet received was not Frame Type Beacon with Frame Version 2 + 0 + + + FV2_BEACON_RECD_1 + The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + FV2_DATA_RECD + Frame Version 2 Data Packet Received + 17 + 1 + read-only + + + FV2_DATA_RECD_0 + The last packet received was not Frame Type Data with Frame Version 2 + 0 + + + FV2_DATA_RECD_1 + The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + FV2_ACK_RECD + Frame Version 2 Acknowledge Packet Received + 18 + 1 + read-only + + + FV2_ACK_RECD_0 + The last packet received was not Frame Type Ack with Frame Version 2 + 0 + + + FV2_ACK_RECD_1 + The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + FV2_CMD_RECD + Frame Version 2 MAC Command Packet Received + 19 + 1 + read-only + + + FV2_CMD_RECD_0 + The last packet received was not Frame Type MAC Command with Frame Version 2 + 0 + + + FV2_CMD_RECD_1 + The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + LLDN_RECD + LLDN Packet Received + 20 + 1 + read-only + + + LLDN_RECD_0 + The last packet received was not Frame Type LLDN + 0 + + + LLDN_RECD_1 + The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets. + 0x1 + + + + + MULTIPURPOSE_RECD + Multipurpose Packet Received + 21 + 1 + read-only + + + MULTIPURPOSE_RECD_0 + last packet received was not Frame Type MULTIPURPOSE + 0 + + + MULTIPURPOSE_RECD_1 + The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets. + 0x1 + + + + + EXTENDED_RECD + Extended Packet Received + 23 + 1 + read-only + + + EXTENDED_RECD_0 + The last packet received was not Frame Type EXTENDED + 0 + + + EXTENDED_RECD_1 + The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets. + 0x1 + + + + + + + CCA_LQI_CTRL + CCA AND LQI CONTROL + 0x40 + 32 + read-write + 0x866004B + 0xFFFFFFFF + + + CCA1_THRESH + CCA Mode 1 Threshold + 0 + 8 + read-write + + + LQI_OFFSET_COMP + LQI Offset Compensation + 16 + 8 + read-write + + + SIMUL_CCA_RX + Simultaneous CCA and Receive Enable + 24 + 1 + read-write + + + SIMUL_CCA_RX_0 + Packets can't be received during CCA measurement + 0 + + + SIMUL_CCA_RX_1 + Packet reception is enabled during CCA measurement if preamble and SFD are detected + 0x1 + + + + + CCA3_AND_NOT_OR + CCA Mode 3 AND not OR + 27 + 1 + read-write + + + CCA3_AND_NOT_OR_0 + CCA1 or CCA2 + 0 + + + CCA3_AND_NOT_OR_1 + CCA1 and CCA2 + 0x1 + + + + + + + CCA2_CTRL + CCA2 CONTROL + 0x44 + 32 + read-write + 0x8230 + 0xFFFFFFF0 + + + CCA2_NUM_CORR_PEAKS + CCA Mode 2 Number of Correlation Peaks Detected + 0 + 4 + read-only + + + CCA2_MIN_NUM_CORR_TH + CCA Mode 2 Threshold Number of Correlation Peaks + 4 + 3 + read-write + + + CCA2_CORR_THRESH + CCA Mode 2 Correlation Threshold + 8 + 8 + read-write + + + + + DSM_CTRL + DSM CONTROL + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ZIGBEE_SLEEP_REQUEST + 802.15.4 Deep Sleep Mode Request for Manual DSM + 0 + 1 + read-write + + + + + MACSHORTADDRS1 + MAC SHORT ADDRESS FOR PAN1 + 0x54 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACPANID1 + MAC PAN ID for PAN1 + 0 + 16 + read-write + + + MACSHORTADDRS1 + MAC SHORT ADDRESS for PAN1 + 16 + 16 + read-write + + + + + MACLONGADDRS1_LSB + MAC LONG ADDRESS 1 LSB + 0x58 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS1_LSB + MAC LONG ADDRESS for PAN1 LSB + 0 + 32 + read-write + + + + + MACLONGADDRS1_MSB + MAC LONG ADDRESS 1 MSB + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS1_MSB + MAC LONG ADDRESS for PAN1 MSB + 0 + 32 + read-write + + + + + DUAL_PAN_CTRL + DUAL PAN CONTROL + 0x60 + 32 + read-write + 0 + 0xFF00FFF7 + + + ACTIVE_NETWORK + Active Network Selector + 0 + 1 + read-write + + + ACTIVE_NETWORK_0 + Select PAN0 + 0 + + + ACTIVE_NETWORK_1 + Select PAN1 + 0x1 + + + + + DUAL_PAN_AUTO + Activates automatic Dual PAN operating mode + 1 + 1 + read-write + + + PANCORDNTR1 + Device is a PAN Coordinator on PAN1 + 2 + 1 + read-write + + + CURRENT_NETWORK + Indicates which PAN is currently selected by hardware + 3 + 1 + read-only + + + CURRENT_NETWORK_0 + PAN0 is selected + 0 + + + CURRENT_NETWORK_1 + PAN1 is selected + 0x1 + + + + + ZB_DP_CHAN_OVRD_EN + Dual PAN Channel Override Enable + 4 + 1 + read-write + + + ZB_DP_CHAN_OVRD_SEL + Dual PAN Channel Override Selector + 5 + 1 + read-write + + + DUAL_PAN_DWELL + Dual PAN Channel Frequency Dwell Time + 8 + 8 + read-write + + + DUAL_PAN_REMAIN + Time Remaining before next PAN switch in auto Dual PAN mode + 16 + 6 + read-only + + + RECD_ON_PAN0 + Last Packet was Received on PAN0 + 22 + 1 + read-only + + + RECD_ON_PAN1 + Last Packet was Received on PAN1 + 23 + 1 + read-only + + + + + CHANNEL_NUM1 + CHANNEL NUMBER 1 + 0x64 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + CHANNEL_NUM1 + Channel Number for PAN1 + 0 + 7 + read-write + + + + + SAM_CTRL + SAM CONTROL + 0x68 + 32 + read-write + 0x80804000 + 0xFFFFFFFF + + + SAP0_EN + Enables SAP0 Partition of the SAM Table + 0 + 1 + read-write + + + SAP0_EN_0 + Disables SAP0 Partition + 0 + + + SAP0_EN_1 + Enables SAP0 Partition + 0x1 + + + + + SAA0_EN + Enables SAA0 Partition of the SAM Table + 1 + 1 + read-write + + + SAA0_EN_0 + Disables SAA0 Partition + 0 + + + SAA0_EN_1 + Enables SAA0 Partition + 0x1 + + + + + SAP1_EN + Enables SAP1 Partition of the SAM Table + 2 + 1 + read-write + + + SAP1_EN_0 + Disables SAP1 Partition + 0 + + + SAP1_EN_1 + Enables SAP1 Partition + 0x1 + + + + + SAA1_EN + Enables SAA1 Partition of the SAM Table + 3 + 1 + read-write + + + SAA1_EN_0 + Disables SAA1 Partition + 0 + + + SAA1_EN_1 + Enables SAA1 Partition + 0x1 + + + + + SAA0_START + First Index of SAA0 partition + 8 + 8 + read-write + + + SAP1_START + First Index of SAP1 partition + 16 + 8 + read-write + + + SAA1_START + First Index of SAA1 partition + 24 + 8 + read-write + + + + + SAM_TABLE + SOURCE ADDRESS MANAGEMENT TABLE + 0x6C + 32 + read-write + 0 + 0x4C00007F + + + SAM_INDEX + Contains the SAM table index to be enabled or invalidated + 0 + 7 + read-write + + + SAM_INDEX_WR + Enables SAM Table Contents to be updated + 7 + 1 + write-only + + + SAM_CHECKSUM + Software-computed source address checksum, to be installed into a table index + 8 + 16 + read-write + + + SAM_INDEX_INV + Invalidate the SAM table index selected by SAM_INDEX + 24 + 1 + write-only + + + SAM_INDEX_EN + Enable the SAM table index selected by SAM_INDEX + 25 + 1 + write-only + + + ACK_FRM_PND + State of AutoTxAck FramePending field when SAM Accelleration is Disabled + 26 + 1 + read-write + + + ACK_FRM_PND_CTRL + Manual Control for AutoTxAck FramePending field + 27 + 1 + read-write + + + ACK_FRM_PND_CTRL_0 + the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware + 0 + + + ACK_FRM_PND_CTRL_1 + the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND + 0x1 + + + + + FIND_FREE_IDX + Find First Free Index + 28 + 1 + write-only + + + INVALIDATE_ALL + Invalidate Entire SAM Table + 29 + 1 + write-only + + + SAM_BUSY + SAM Table Update Status Bit + 31 + 1 + read-only + + + + + SAM_MATCH + SOURCE ADDRESS MANAGEMENT MATCH + 0x70 + 32 + read-only + 0 + 0 + + + SAP0_MATCH + Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match + 0 + 7 + read-only + + + SAP0_ADDR_PRESENT + A Checksum Match is Present in the SAP0 Partition of the SAM Table + 7 + 1 + read-only + + + SAA0_MATCH + Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match + 8 + 7 + read-only + + + SAA0_ADDR_ABSENT + A Checksum Match is Absent in the SAA0 Partition of the SAM Table + 15 + 1 + read-only + + + SAP1_MATCH + Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match + 16 + 7 + read-only + + + SAP1_ADDR_PRESENT + A Checksum Match is Present in the SAP1 Partition of the SAM Table + 23 + 1 + read-only + + + SAA1_MATCH + Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match + 24 + 7 + read-only + + + SAA1_ADDR_ABSENT + A Checksum Match is Absent in the SAP1 Partition of the SAM Table + 31 + 1 + read-only + + + + + SAM_FREE_IDX + SAM FREE INDEX + 0x74 + 32 + read-only + 0 + 0 + + + SAP0_1ST_FREE_IDX + First non-enabled (invalid) index in the SAP0 partition + 0 + 8 + read-only + + + SAA0_1ST_FREE_IDX + First non-enabled (invalid) index in the SAA0 partition + 8 + 8 + read-only + + + SAP1_1ST_FREE_IDX + First non-enabled (invalid) index in the SAP1 partition + 16 + 8 + read-only + + + SAA1_1ST_FREE_IDX + First non-enabled (invalid) index in the SAA1 partition + 24 + 8 + read-only + + + + + SEQ_CTRL_STS + SEQUENCE CONTROL AND STATUS + 0x78 + 32 + read-write + 0x8 + 0xE0C000FF + + + FORCE_CLK_ON + Force On 802.15.4 phy_gck + 1 + 1 + read-write + + + FORCE_CLK_ON_0 + Allow TSM to control 802.15.4 phy_gck, for minimum power consumption (default) + 0 + + + FORCE_CLK_ON_1 + Force on 802.15.4 phy_gclk at all times, for debug purposes only + 0x1 + + + + + CLR_NEW_SEQ_INHIBIT + Overrides the automatic hardware locking of the programmed XCVSEQ while an autosequence is underway + 2 + 1 + read-write + + + EVENT_TMR_DO_NOT_LATCH + Overrides the automatic hardware latching of the Event Timer + 3 + 1 + read-write + + + LATCH_PREAMBLE + Stickiness Control for Preamble Detection + 4 + 1 + read-write + + + LATCH_PREAMBLE_0 + Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect + 0 + + + LATCH_PREAMBLE_1 + Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e., occurrences of preamble and SFD detection are latched and held until the start of the next autosequence + 0x1 + + + + + NO_RX_RECYCLE + Disable Automatic RX Sequence Recycling + 5 + 1 + read-write + + + FORCE_CRC_ERROR + Induce a CRC Error in Transmitted Packets + 6 + 1 + read-write + + + FORCE_CRC_ERROR_0 + normal operation + 0 + + + FORCE_CRC_ERROR_1 + Force the next transmitted packet to have a CRC error + 0x1 + + + + + CONTINUOUS_EN + Enable Continuous TX or RX Mode + 7 + 1 + read-write + + + CONTINUOUS_EN_0 + normal operation + 0 + + + CONTINUOUS_EN_1 + Continuous TX or RX mode is enabled (depending on XCVSEQ setting). + 0x1 + + + + + XCVSEQ_ACTUAL + Indicates the programmed sequence that has been recognized by the ZSM Sequence Manager + 8 + 3 + read-only + + + SEQ_IDLE + ZSM Sequence Idle Indicator + 11 + 1 + read-only + + + NEW_SEQ_INHIBIT + New Sequence Inhibit + 12 + 1 + read-only + + + RX_TIMEOUT_PENDING + Indicates a TMR3 RX Timeout is Pending + 13 + 1 + read-only + + + RX_MODE + RX Operation in Progress + 14 + 1 + read-only + + + TMR2_SEQ_TRIG_ARMED + indicates that TMR2 has been programmed and is armed to trigger a new autosequence + 15 + 1 + read-only + + + SEQ_T_STATUS + Status of the just-completed or ongoing Sequence T or Sequence TR + 16 + 6 + read-only + + + SW_ABORTED + Autosequence has terminated due to a Software abort. + 24 + 1 + read-only + + + TC3_ABORTED + autosequence has terminated due to an TMR3 timeout + 25 + 1 + read-only + + + PLL_ABORTED + Autosequence has terminated due to an PLL unlock event + 26 + 1 + read-only + + + EXT_ABORTED + Autosequence has terminated due to a Wake-On-Radio command + 27 + 1 + read-only + + + ARB_GRANT_DEASSERTION_ABORTED + Autosequence has terminated due to an arb_grant deassertion event + 28 + 1 + read-only + + + + + ACKDELAY + ACK DELAY + 0x7C + 32 + read-write + 0x2D0002 + 0xFFFFFFFF + + + ACKDELAY + ACK Delay + 0 + 7 + read-write + + + TXDELAY + TX Delay + 8 + 6 + read-write + + + RXDELAY + RX Delay + 16 + 6 + read-write + + + FAST_TX_WD_EN + Fast TX_WD enable/disable + 24 + 1 + read-write + + + FAST_TX_WD_EN_0 + Disable fast Tx warmdown sequence. + 0 + + + FAST_TX_WD_EN_1 + Enable fast Tx warmdown sequence. + 0x1 + + + + + FAST_TX_WD_DELAY + FAST_TX_WD_DELAY + 25 + 2 + read-write + + + + + FILTERFAIL_CODE + FILTER FAIL CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFC00 + + + FILTERFAIL_CODE + Filter Fail Code + 0 + 10 + read-only + + + FILTERFAIL_PAN_SEL + PAN Selector for Filter Fail Code + 15 + 1 + read-write + + + FILTERFAIL_PAN_SEL_0 + FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0 + 0 + + + FILTERFAIL_PAN_SEL_1 + FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1 + 0x1 + + + + + + + RX_WTR_MARK + RECEIVE WATER MARK + 0x84 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + RX_WTR_MARK + RECEIVE WATER MARK + 0 + 8 + read-write + + + + + SLOT_PRELOAD + SLOT PRELOAD + 0x8C + 32 + read-write + 0x74 + 0xFFFFFFFF + + + SLOT_PRELOAD + Slotted Mode Preload + 0 + 8 + read-write + + + + + SEQ_STATE + 802.15.4 SEQUENCE STATE + 0x90 + 32 + read-only + 0 + 0xC000C0E0 + + + SEQ_STATE + ZSM Sequence State + 0 + 5 + read-only + + + PREAMBLE_DET + Preamble Detected + 8 + 1 + read-only + + + SFD_DET + SFD Detected + 9 + 1 + read-only + + + FILTERFAIL_FLAG_SEL + Consolidated Filter Fail Flag + 10 + 1 + read-only + + + CRCVALID + CRC Valid Indicator + 11 + 1 + read-only + + + CRCVALID_0 + Rx FCS != calculated CRC (incorrect) + 0 + + + CRCVALID_1 + Rx FCS = calculated CRC (correct) + 0x1 + + + + + PLL_ABORT + Raw PLL Abort Signal + 12 + 1 + read-only + + + PLL_ABORTED + Autosequence has terminated due to an PLL unlock event + 13 + 1 + read-only + + + RX_BYTE_COUNT + Realtime Received Byte Count + 16 + 8 + read-only + + + CCCA_BUSY_CNT + Number of CCA Measurements resulting in Busy Channel + 24 + 6 + read-only + + + + + TMR_PRESCALE + TIMER PRESCALER + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + TMR_PRESCALE + Timer Prescaler + 0 + 3 + read-write + + + TMR_PRESCALE_2 + 500kHz (33.55 S) + 0x2 + + + TMR_PRESCALE_3 + 250kHz (67.11 S) + 0x3 + + + TMR_PRESCALE_4 + 125kHz (134.22 S) + 0x4 + + + TMR_PRESCALE_5 + 62.5kHz (268.44 S) -- default + 0x5 + + + TMR_PRESCALE_6 + 31.25kHz (536.87 S) + 0x6 + + + TMR_PRESCALE_7 + 15.625kHz (1073.74 S) + 0x7 + + + + + + + LENIENCY_LSB + LENIENCY LSB + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENIENCY_LSB + Leniency LSB Register + 0 + 32 + read-write + + + + + LENIENCY_MSB + LENIENCY MSB + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + LENIENCY_MSB + Leniency MSB Register + 0 + 11 + read-write + + + + + PART_ID + PART ID + 0xA0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + PART_ID + 802.15.4 Part ID + 0 + 8 + read-only + + + + + COEX_CTRL + COEXISTENCE CONTROL + 0xA4 + 32 + read-write + 0x304 + 0xFFFFFFFF + + + COEX_EN + Coexistence Enable + 0 + 1 + read-write + + + COEX_EN_0 + Coexistence function is disabled. + 0 + + + COEX_EN_1 + Coexistence function is enabled. + 0x1 + + + + + COEX_REQ_DELAY_EN + Coexistence Request Delay Enable + 1 + 1 + read-write + + + COEX_REQ_DELAY_EN_0 + arb_request is not delayed during R sequence. + 0 + + + COEX_REQ_DELAY_EN_1 + arb_request is delayed until preamble is detected during R sequence. + 0x1 + + + + + COEX_REQ_ON_PD + Coexistence Request on Preamble detected + 2 + 1 + read-write + + + COEX_REQ_ON_PD_0 + arb_request is delayed until SFD is detected during R sequence. + 0 + + + COEX_REQ_ON_PD_1 + arb_request is delayed until preamble is detected during R sequence. + 0x1 + + + + + COEX_TIMEOUT_MSK + Coexistence Timeout Interrupt Mask bit + 6 + 1 + read-write + + + COEX_TIMEOUT_MSK_0 + allows interrupt when coexistence timeout + 0 + + + COEX_TIMEOUT_MSK_1 + Interrupt generation is disabled, but a COEX_TIMEOUT_IRQ flag can be set + 0x1 + + + + + COEX_TIMEOUT_IRQ + Coexistence Timeout Interrupt + 7 + 1 + read-write + oneToClear + + + COEX_TIMEOUT + Coexistence timeout value + 8 + 8 + read-write + + + + + COEX_PRIORITY + COEXISTENCE PRIORITY + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIORITY_T + PRIORITY_T + 0 + 2 + read-write + + + PRIORITY_R_PRE + PRIORITY_R_PRE + 2 + 2 + read-write + + + PRIORITY_R_PKT + PRIORITY_R_PKT + 4 + 2 + read-write + + + PRIORITY_TACK + PRIORITY_TACK + 6 + 2 + read-write + + + PRIORITY_CCA + PRIORITY_CCA + 8 + 2 + read-write + + + PRIORITY_CCCA + PRIORITY_CCCA + 10 + 2 + read-write + + + PRIORITY_CTX + PRIORITY_CT + 12 + 2 + read-write + + + PRIORITY_RACK_PRE + PRIORITY_RACK_PRE + 14 + 2 + read-write + + + PRIORITY_RACK_PKT + PRIORITY_RACK_PKT + 16 + 2 + read-write + + + PRIORITY_OVRD + PRIORITY_OVRD + 29 + 2 + read-write + + + PRIORITY_OVRD_EN + PRIORITY_OVRD_EN + 31 + 1 + read-write + + + PRIORITY_OVRD_EN_0 + Disable overriding PRIORITY value. + 0 + + + PRIORITY_OVRD_EN_1 + Enable overriding PRIORITY value. + 0x1 + + + + + + + ENHACK_CTRL0 + ENHACK_CTRL 0 + 0xAC + 32 + read-write + 0xFF00 + 0xFFFFFFFF + + + ENHACK_EN + Enhanced Acknowledgment Enable + 0 + 1 + read-write + + + ENHACK_EN_0 + Enhanced acknowledgment is disabled. + 0 + + + ENHACK_EN_1 + Enhanced acknowledgment is enabled. + 0x1 + + + + + SW_LEN_RDY + Software enhanced acknowledgment frame Length field ready + 1 + 1 + read-write + + + SW_LEN_RDY_0 + Software enhanced acknowledgment frame Length field is not ready. + 0 + + + SW_LEN_RDY_1 + Software enhanced acknowledgment frame Length field is ready in RAM + 0x1 + + + + + SW_HIE_RDY + Software enhanced acknowledgment frame HIE field ready + 2 + 1 + read-write + + + SW_HIE_RDY_0 + Software enhanced acknowledgment frame HIE field is not ready. + 0 + + + SW_HIE_RDY_1 + Software enhanced acknowledgment frame HIE field is ready in RAM + 0x1 + + + + + EMPTY_SECURITY_ENABLED_OVRD + Override value of Security Enabled field in Empty Enhanced Acknowledgment + 4 + 1 + read-write + + + EMPTY_SRC_ADDR_MODE + Source Address Mode field in Empty Enhanced Acknowledgment + 5 + 2 + read-write + + + SW_MHR_LENGTH + Software calculated MHR(excludes the HIE field) Length in bytes. + 8 + 8 + read-write + + + HW_FRAME_PENDING + Hardware calculated Frame Pending field + 16 + 1 + read-only + + + EMPTY_SECURITY_ENABLED_OVRD_EN + Override enable of Security Enabled field in Empty Enhanced Acknowledgment + 18 + 1 + read-write + + + EMPTY_SECURITY_ENABLED_OVRD_EN_0 + Security Enabled field in Empty Enhanced Acknowledgment frame is 0. + 0 + + + EMPTY_SECURITY_ENABLED_OVRD_EN_1 + Security Enabled field in Empty Enhanced Acknowledgment frame is from EMPTY_SECURITY_ENABLED_OVRD. + 0x1 + + + + + ACK_ABORT_MSK + Enhanced Acknowledgment Abort IRQ Mask bit + 26 + 1 + read-write + + + ACK_ABORT_MSK_0 + allows interrupt when HIE field is not ready by software. + 0 + + + ACK_ABORT_MSK_1 + Interrupt generation is disabled, but a ACK_ABORT_IRQ flag can be set + 0x1 + + + + + ACK_ABORT_IRQ + Enhanced Acknowledgment Abort IRQ + 27 + 1 + read-write + oneToClear + + + EMPTY_ACK_MSK + Empty Enhanced Acknowledgment IRQ Mask bit + 28 + 1 + read-write + + + EMPTY_ACK_MSK_0 + allows interrupt when Empty Enhanced Acknowledgment + 0 + + + EMPTY_ACK_MSK_1 + Interrupt generation is disabled, but a EMPTY_ACK_IRQ flag can be set + 0x1 + + + + + EMPTY_ACK_IRQ + Empty Enhanced Acknowledgment IRQ + 29 + 1 + read-write + oneToClear + + + RECYC_MSK + Recycle IRQ Mask bit + 30 + 1 + read-write + + + RECYC_MSK_0 + allows interrupt when recycle + 0 + + + RECYC_MSK_1 + Interrupt generation is disabled, but a RECYC_IRQ flag can be set + 0x1 + + + + + RECYC_IRQ + Recycle IRQ + 31 + 1 + read-write + oneToClear + + + + + + + GENFSK + GENERIC FSK + GENFSK + 0x48A02000 + + 0 + 0x10C + registers + + + + IRQ_CTRL + IRQ CONTROL + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQ_END_IRQ + Sequence End Interrupt + 0 + 1 + read-write + oneToClear + + + CLEAR + Sequence End Interrupt is not asserted. + 0 + + + ASSERTED + Sequence End Interrupt is asserted. + 0x1 + + + + + TX_IRQ + TX Interrupt + 1 + 1 + read-write + oneToClear + + + CLEAR + TX Interrupt is not asserted. + 0 + + + ASSERTED + TX Interrupt is asserted. + 0x1 + + + + + RX_IRQ + RX Interrupt + 2 + 1 + read-write + oneToClear + + + CLEAR + RX Interrupt is not asserted. + 0 + + + ASSERTED + RX Interrupt is asserted. + 0x1 + + + + + NTW_ADR_IRQ + Network Address Match Interrupt + 3 + 1 + read-write + oneToClear + + + CLEAR + Network Address Match Interrupt is not asserted. + 0 + + + ASSERTED + Network Address Match Interrupt is asserted. + 0x1 + + + + + T1_IRQ + Timer1 (T1) Compare Interrupt + 4 + 1 + read-write + oneToClear + + + CLEAR + Timer1 (T1) Compare Interrupt is not asserted. + 0 + + + ASSERTED + Timer1 (T1) Compare Interrupt is asserted. + 0x1 + + + + + T2_IRQ + Timer2 (T2) Compare Interrupt + 5 + 1 + read-write + oneToClear + + + CLEAR + Timer2 (T2) Compare Interrupt is not asserted. + 0 + + + ASSERTED + Timer2 (T2) Compare Interrupt is asserted. + 0x1 + + + + + PLL_UNLOCK_IRQ + PLL Unlock Interrupt + 6 + 1 + read-write + oneToClear + + + CLEAR + PLL Unlock Interrupt is not asserted. + 0 + + + ASSERTED + PLL Unlock Interrupt is asserted. + 0x1 + + + + + WAKE_IRQ + Wake Interrrupt + 7 + 1 + read-write + oneToClear + + + CLEAR + Wake Interrupt is not asserted. + 0 + + + ASSERTED + Wake Interrupt is asserted. + 0x1 + + + + + RX_WATERMARK_IRQ + RX Watermark Interrupt + 8 + 1 + read-write + oneToClear + + + CLEAR + RX Watermark Interrupt is not asserted. + 0 + + + ASSERTED + RX Watermark Interrupt is asserted. + 0x1 + + + + + TSM_IRQ + TSM Interrupt + 9 + 1 + read-only + + + CLEAR + TSM0_IRQ and TSM1_IRQ are both clear. + 0 + + + ASSERTED + Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS. + 0x1 + + + + + CRC_VALID + CRC Valid + 10 + 1 + read-only + + + ACK_IRQ + Auto ACK Interrupt + 11 + 1 + read-write + oneToClear + + + CLEAR + Auto ACK Interrupt is not asserted. + 0 + + + ASSERTED + Auto ACK Interrupt is asserted. + 0x1 + + + + + PHRFFAIL_IRQ + Received Frame PHR Fail Interrupt + 12 + 1 + read-write + oneToClear + + + CLEAR + Received frame PHR Fail Interrupt is not asserted. + 0 + + + ASSERTED + Received frame PHR Fail Interrupt is asserted. + 0x1 + + + + + FILTERFAIL_IRQ + Received Frame Filter Fail Interrupt + 13 + 1 + read-write + oneToClear + + + CLEAR + A Filter Fail Interrupt has not occurred. + 0 + + + ASSERTED + A Filter Fail Interrupt has occurred. + 0x1 + + + + + CCA_IRQ + CCA Interrupt + 14 + 1 + read-write + oneToClear + + + CLEAR + A CCA Interrupt has not occurred + 0 + + + ASSERTED + A CCA Interrupt has occurred + 0x1 + + + + + MS_IRQ + Mode Switch Interrupt + 15 + 1 + read-write + oneToClear + + + CLEAR + A Mode Switch frame is not received + 0 + + + ASSERTED + A Mode Switch frame is received + 0x1 + + + + + SEQ_END_IRQ_EN + SEQ_END_IRQ Enable + 16 + 1 + read-write + + + DISABLED + Sequence End Interrupt is not enabled. + 0 + + + ENABLED + Sequence End Interrupt is enabled. + 0x1 + + + + + TX_IRQ_EN + TX_IRQ Enable + 17 + 1 + read-write + + + DISABLED + TX Interrupt is not enabled. + 0 + + + ENABLED + TX Interrupt is enabled. + 0x1 + + + + + RX_IRQ_EN + RX_IRQ Enable + 18 + 1 + read-write + + + DISABLED + RX Interrupt is not enabled. + 0 + + + ENABLED + RX Interrupt is enabled. + 0x1 + + + + + NTW_ADR_IRQ_EN + NTW_ADR_IRQ Enable + 19 + 1 + read-write + + + DISABLED + Network Address Match Interrupt is not enabled. + 0 + + + ENABLED + Network Address Match Interrupt is enabled. + 0x1 + + + + + T1_IRQ_EN + T1_IRQ Enable + 20 + 1 + read-write + + + DISABLED + Timer1 (T1) Compare Interrupt is not enabled. + 0 + + + ENABLED + Timer1 (T1) Compare Interrupt is enabled. + 0x1 + + + + + T2_IRQ_EN + T2_IRQ Enable + 21 + 1 + read-write + + + DISABLED + Timer1 (T2) Compare Interrupt is not enabled. + 0 + + + ENABLED + Timer1 (T2) Compare Interrupt is enabled. + 0x1 + + + + + PLL_UNLOCK_IRQ_EN + PLL_UNLOCK_IRQ Enable + 22 + 1 + read-write + + + DISABLED + PLL Unlock Interrupt is not enabled. + 0 + + + ENABLED + PLL Unlock Interrupt is enabled. + 0x1 + + + + + WAKE_IRQ_EN + WAKE_IRQ Enable + 23 + 1 + read-write + + + DISABLED + Wake Interrupt is not enabled. + 0 + + + ENABLED + Wake Interrupt is enabled. + 0x1 + + + + + RX_WATERMARK_IRQ_EN + RX_WATERMARK_IRQ Enable + 24 + 1 + read-write + + + DISABLED + RX Watermark Interrupt is not enabled. + 0 + + + ENABLED + RX Watermark Interrupt is enabled. + 0x1 + + + + + TSM_IRQ_EN + TSM_IRQ Enable + 25 + 1 + read-write + + + DISABLED + TSM Interrupt is not enabled. + 0 + + + ENABLED + TSM Interrupt is enabled. + 0x1 + + + + + GENERIC_FSK_IRQ_EN + GENERIC_FSK_IRQ Master Enable + 26 + 1 + read-write + + + DISABLED + All GENERIC_FSK Interrupts are disabled. + 0 + + + ENABLED + All GENERIC_FSK Interrupts can be enabled. + 0x1 + + + + + ACK_IRQ_EN + ACK_IRQ Enable + 27 + 1 + read-write + + + DISABLED + Auto ACK Interrupt is not enabled. + 0 + + + ENABLED + Auto ACK Interrupt is enabled. + 0x1 + + + + + PHRFAIL_IRQ_EN + PHRFAIL_IRQ Enable + 28 + 1 + read-write + + + DISABLED + PHRFAIL Interrupt is not enabled. + 0 + + + ENABLED + PHRFAIL Interrupt is enabled. + 0x1 + + + + + FILTERFAIL_IRQ_EN + FILTERFAIL_IRQ Enable + 29 + 1 + read-write + + + DISABLED + FILTERFAIL Interrupt is not enabled. + 0 + + + ENABLED + FILTERFAIL Interrupt is enabled. + 0x1 + + + + + CCA_IRQ_EN + CCA_IRQ Enable + 30 + 1 + read-write + + + DISABLED + CCA Interrupt is not enabled. + 0 + + + ENABLED + CCA Interrupt is enabled. + 0x1 + + + + + MS_IRQ_EN + MS_IRQ Enable + 31 + 1 + read-write + + + DISABLED + MS Interrupt is not enabled. + 0 + + + ENABLED + MS Interrupt is enabled. + 0x1 + + + + + + + EVENT_TMR + EVENT TIMER + 0x4 + 32 + read-only + 0 + 0 + + + EVENT_TMR + Event Timer + 0 + 32 + read-only + + + + + T1_CMP + T1 COMPARE + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + T1_CMP + Timer1 (T1) Compare Value + 0 + 32 + read-write + + + + + T2_CMP + T2 COMPARE + 0xC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + T2_CMP + Timer2 (T2) Compare Value + 0 + 32 + read-write + + + + + TIMESTAMP + TIMESTAMP + 0x10 + 32 + read-only + 0 + 0 + + + TIMESTAMP + Received Packet Timestamp + 0 + 32 + read-only + + + + + XCVR_CTRL + TRANSCEIVER CONTROL + 0x14 + 32 + read-write + 0x7FF00 + 0xFFFFFFFF + + + SEQCMD + Sequence Commands, also named as "XCVSEQ(Transceiver Sequence)" + 0 + 5 + read-write + + + IDLE + Same as command ABORT + 0 + + + TX_START_NOW + TX Start Now + 0x1 + + + TX_START_T1 + TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + 0x2 + + + TX_START_T2 + TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + 0x3 + + + TX_CANCEL + TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress + 0x4 + + + RX_START_NOW + RX Start Now + 0x5 + + + RX_START_T1 + RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + 0x6 + + + RX_START_T2 + RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + 0x7 + + + RX_STOP_T1 + RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + 0x8 + + + RX_STOP_T2 + RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + 0x9 + + + RX_CANCEL + RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress + 0xA + + + ABORT + Abort All - Cancels all pending events and abort any sequence-in-progress + 0xB + + + TR_START_NOW + TR Start Now + 0xC + + + TR_START_T1 + TR Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + 0xD + + + TR_START_T2 + TR Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + 0xE + + + TR_START_CANCEL + TR Cancel -- Cancels pending TR events but do not abort a TR-in-progress + 0xF + + + CCA_START_NOW + CCA Start Now + 0x10 + + + CCA_START_T1 + CCA Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + 0x11 + + + CCA_START_T2 + CCA Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + 0x12 + + + CCA_START_CANCEL + CCA Cancel -- Cancels pending CCA events but do not abort a CCA-in-progress + 0x13 + + + + + LENGTH_EXT + Extracted Length Field + 8 + 11 + read-only + + + CMDDEC_CS + Command Decode + 24 + 5 + read-only + + + XCVR_BUSY + Transceiver Busy + 31 + 1 + read-only + + + XCVR_BUSY_0 + IDLE + 0 + + + XCVR_BUSY_1 + BUSY + 0x1 + + + + + + + XCVR_STS + TRANSCEIVER STATUS + 0x18 + 32 + read-only + 0x800000 + 0xFFFFFFFF + + + LQI + Link Quality Indicator + 0 + 8 + read-only + + + LQI_VALID + LQI Valid Indicator + 15 + 1 + read-only + + + CLEAR + LQI is not yet valid for RX packet. + 0 + + + SET + LQI is valid for RX packet. + 0x1 + + + + + RSSI + RSSI Value + 16 + 8 + read-only + + + + + XCVR_CFG + TRANSCEIVER CONFIGURATION + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_WHITEN_DIS + TX Whitening Disable + 0 + 1 + read-write + + + RX_DEWHITEN_DIS + RX De-Whitening Disable + 1 + 1 + read-write + + + SW_CRC_EN + Software CRC Enable + 2 + 1 + read-write + + + STOP_POSTPONE_ON_AA + Postpone Stop Command Timeout On Access Address Match Enable + 3 + 1 + read-write + + + STOP_POSTPONE_ON_AA_0 + STOP Abort will occur on RX_STOP_T1 or RX_STOP_T1 Event Timer match, regardless of NTW_ADR_MCH + 0 + + + STOP_POSTPONE_ON_AA_1 + STOP Abort will be deferred on RX_STOP_T1 or RX_STOP_T1 Event Timer match, if NTW_ADR_MCH is asserted; otherwise the RX_STOP Abort will occur immediately + 0x1 + + + + + PREAMBLE_SZ + Preamble Size + 4 + 9 + read-write + + + GEN_PREAMBLE + Preamble pattern + 16 + 8 + read-write + + + PREAMBLE_SEL + Preamble Select + 24 + 3 + read-write + + + PREAMBLE_AUTO + The controller hardware selects the preamble pattern based on the first transmitted bit of Network Address, such that the last bit of preamble is the opposite polarity from the first bit of Network Address, forcing a bit transition at this boundary. + 0 + + + GEN_PREAMBLE + Preamble is programmed by register GEN_PREAMBLE[7:0] + 0x1 + + + PREAMBLE_01 + Preamble is 0b01 + 0x2 + + + PREAMBLE_10 + Preamble is 0b10 + 0x3 + + + + + T1_CMP_EN + Timer1 (T1) Compare Enable + 30 + 1 + read-write + + + T2_CMP_EN + Timer2 (T2) Compare Enable + 31 + 1 + read-write + + + + + CHANNEL_NUM0 + CHANNEL NUMBER 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHANNEL_NUM0 + Channel Number for PAN0 + 0 + 7 + read-write + + + + + TX_POWER + TRANSMIT POWER + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_POWER + Transmit Power + 0 + 6 + read-write + + + + + NTW_ADR_CTRL + NETWORK ADDRESS CONTROL + 0x28 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + NTW_ADR_EN + Network Address Enable + 0 + 4 + read-write + + + NTW_ADR_EN_1 + Enable Network Address 0 for correlation + 0x1 + + + NTW_ADR_EN_2 + Enable Network Address 1 for correlation + 0x2 + + + NTW_ADR_EN_4 + Enable Network Address 2 for correlation + 0x4 + + + NTW_ADR_EN_8 + Enable Network Address 3 for correlation + 0x8 + + + + + NTW_ADR_MCH + Network Address Match + 4 + 4 + read-only + + + NTW_ADR_MCH_1 + Network Address 0 has matched + 0x1 + + + NTW_ADR_MCH_2 + Network Address 1 has matched + 0x2 + + + NTW_ADR_MCH_4 + Network Address 2 has matched + 0x4 + + + NTW_ADR_MCH_8 + Network Address 3 has matched + 0x8 + + + + + NTW_ADR_SZ + Network Address Size + 8 + 2 + read-write + + + NTW_ADR_SZ_0 + Network Address 0/1/2/3 requires a 8-bit correlation + 0 + + + NTW_ADR_SZ_1 + Network Address 0/1/2/3 requires a 16-bit correlation + 0x1 + + + NTW_ADR_SZ_2 + Network Address 0/1/2/3 requires a 24-bit correlation + 0x2 + + + NTW_ADR_SZ_3 + Network Address 0/1/2/3 requires a 32-bit correlation + 0x3 + + + + + NTW_ADR_THR + Network Address Threshold + 16 + 3 + read-write + + + + + NTW_ADR_0 + NETWORK ADDRESS 0 + 0x2C + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_0 + Network Address 0 + 0 + 32 + read-write + + + + + NTW_ADR_1 + NETWORK ADDRESS 1 + 0x30 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_1 + Network Address 1 + 0 + 32 + read-write + + + + + NTW_ADR_2 + NETWORK ADDRESS 2 + 0x34 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_2 + Network Address 2 + 0 + 32 + read-write + + + + + NTW_ADR_3 + NETWORK ADDRESS 3 + 0x38 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_3 + Network Address 2 + 0 + 32 + read-write + + + + + RX_WATERMARK + RECEIVE WATERMARK + 0x3C + 32 + read-write + 0x1FFF0FFF + 0xFFFFFFFF + + + RX_WATERMARK + Receive Watermark + 0 + 13 + read-write + + + BYTE_COUNTER + Byte Counter + 16 + 13 + read-only + + + + + DSM_CTRL + DSM CONTROL + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + GEN_SLEEP_REQUEST + GENERIC_FSK Deep Sleep Mode Request + 0 + 1 + read-write + + + + + PART_ID + PART ID + 0x44 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PART_ID + Part ID + 0 + 8 + read-only + + + + + SLOT_PRELOAD + SLOT PRELOAD + 0x48 + 32 + read-write + 0x2A8 + 0xFFFFFFFF + + + SLOT_PRELOAD + Slotted Mode Preload + 0 + 16 + read-write + + + + + SLOT_TIME + SLOT TIME + 0x4C + 32 + read-write + 0x8E8 + 0xFFFFFFFF + + + SLOT_TIME + Duration of the Backoff Slot + 0 + 16 + read-write + + + + + TURNAROUND_TIME + TURNAROUND TIME + 0x50 + 32 + read-write + 0x3E8 + 0xFFFFFFFF + + + TURNAROUND_TIME + RX-to-TX or TX-to-RX turnaround time + 0 + 16 + read-write + + + + + ACKDELAY + ACK DELAY + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACKDELAY + ACK Delay + 0 + 10 + read-write + + + + + RXDELAY + RX DELAY + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXDELAY + RX Delay + 0 + 10 + read-write + + + + + TXDELAY + TX DELAY + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDELAY + TX Delay + 0 + 10 + read-write + + + + + PACKET_CFG + PACKET CONFIGURATION + 0x60 + 32 + read-write + 0xC00040 + 0xFFFFFFFF + + + LENGTH_SZ + LENGTH Size + 0 + 5 + read-write + + + LENGTH_BIT_ORD + LENGTH Bit Order + 5 + 1 + read-write + + + LENGTH_BIT_ORD_0 + LS Bit First + 0 + + + LENGTH_BIT_ORD_1 + MS Bit First + 0x1 + + + + + SYNC_ADDR_SZ + Sync Address Size + 6 + 2 + read-write + + + H0_SZ + H0 Size + 16 + 5 + read-write + + + AA_PLAYBACK_CNT + AA PLAYBACK COUNT + 22 + 1 + read-write + + + AA_PLAYBACK_CNT_0 + AA is not through CRC and not playback to Link layer. + 0 + + + AA_PLAYBACK_CNT_1 + AA is through CRC and palyback to Link Layer. + 0x1 + + + + + LL_FETCH_AA + Link layer fetches AA from PHY + 23 + 1 + read-write + + + LL_FETCH_AA_0 + Link layer does not fetch AA from PHY + 0 + + + LL_FETCH_AA_1 + Link layer fetches AA from PHY when AA_PLAYBACK_CNT is 0 + 0x1 + + + + + H1_SZ + H1 Size + 24 + 5 + read-write + + + H1_FAIL + H1 Violated Status Bit + 29 + 1 + read-only + + + H0_FAIL + H0 Violated Status Bit + 30 + 1 + read-only + + + LENGTH_FAIL + Maximum Length Violated Status Bit + 31 + 1 + read-only + + + + + H0_CFG + H0 CONFIGURATION + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + H0_MATCH + H0 Match Register + 0 + 16 + read-write + + + H0_MASK + H0 Mask Register + 16 + 16 + read-write + + + + + H1_CFG + H1 CONFIGURATION + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + H1_MATCH + H1 Match Register + 0 + 16 + read-write + + + H1_MASK + H1 Mask Register + 16 + 16 + read-write + + + + + CRC_CFG + CRC CONFIGURATION + 0x6C + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CRC_IGNORE + CRC Ignore + 24 + 1 + read-write + + + ASSERT_CRC_FAILURE + RX_IRQ will not be asserted for a received packet which fails CRC verification. + 0 + + + ALLOW_CRC_FAILURE + RX_IRQ will be asserted even for a received packet which fails CRC verification. + 0x1 + + + + + CRC_VALID + CRC Valid + 28 + 1 + read-only + + + INVALID + CRC of RX packet is not valid. + 0 + + + VALID + CRC of RX packet is valid. + 0x1 + + + + + + + LENGTH_ADJ + LENGTH ADJUSTMENT + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENGTH_ADJ + Length Adjustment + 0 + 11 + read-write + + + + + TIMESTAMP_RX_DONE + TIMESTAMP_RX_DONE + 0x74 + 32 + read-only + 0 + 0 + + + TIMESTAMP_RX_DONE + Received Packet Timestamp. Captured at Rx done. + 0 + 32 + read-only + + + + + TIMESTAMP_TX_DONE + TIMESTAMP_TX_DONE + 0x78 + 32 + read-only + 0 + 0 + + + TIMESTAMP_TX_DONE + Received Packet Timestamp. Captured at Tx done. + 0 + 32 + read-only + + + + + MULT_PKT_CTRL + MULT_PKT_CTRL + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + SEG_SZ + RAM Segment Size + 0 + 4 + read-write + + + PKT_INDEX + Packet Index + 8 + 7 + read-only + + + SEG_BASE_ADDR + Segment Offset Address + 16 + 12 + read-only + + + RESET_PKT_IDX + Reset the PKT_INDEX to zero + 30 + 1 + write-only + + + MULT_PKT_EN + Enable to send or receive multiple packets + 31 + 1 + read-write + + + DISABLED + Send or receive multiple packets is not enabled. + 0 + + + ENABLED + Send or receive multiple packets is enabled. + 0x1 + + + + + + + RPA_WL_STATUS + RPA AND WHITE LIST STATUS + 0x80 + 32 + read-write + 0xF0F003F + 0xFFFFFFFF + + + WL_MATCH_INDEX + The matched white list index of the identity address resolved(RPA is enabled) or peer address received(RPA is not enabled) + 0 + 6 + read-only + + + PEER_RESOLVED_INDEX + The matched RPA index of peer address + 16 + 4 + read-only + + + LOCAL_RESOLVED_INDEX + The matched RPA index of local address + 24 + 4 + read-only + + + SEARCH_WL + Search Identity Address in White List + 31 + 1 + read-write + + + + + LENGTH_MAX + MAXIMUM LENGTH + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENGTH_MAX + Maximum Length for Received Packets + 16 + 7 + read-write + + + REC_BAD_PKT + Receive Bad Packets + 23 + 1 + read-write + + + REC_BAD_PKT_0 + packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed + 0 + + + REC_BAD_PKT_1 + packets which fail H0, H1, or LENGTH_MAX are received in their entirety + 0x1 + + + + + + + EVENT_TMR_LD + EVENT TIMER LOAD + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + EVENT_TMR_LD + Event Timer Load + 0 + 32 + write-only + + + + + EVENT_TMR_ADD + EVENT TIMER ADD + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + EVENT_TMR_ADD + Event Timer Add + 0 + 32 + write-only + + + + + ENH_FEATURE + ENHANCED FEATURES + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GENLL_MODE + Linklayer Mode Select + 0 + 4 + read-write + + + GENLL_MODE0 + GLL Mode + 0 + + + GENLL_MODE1 + PAN Mode + 0x1 + + + GENLL_MODE2 + FAN Mode + 0x2 + + + GENLL_MODE3 + Hybrid Dual PAN Mode + 0x3 + + + GENLL_MODE6 + FCP Mode + 0x6 + + + GENLL_MODE9 + Bluetooth LE Uncoded Mode + 0x9 + + + GENLL_MODE10 + Bluetooth LE LR Mode + 0xA + + + GENLL_MODE11 + Bluetooth LE Concurrent Mode (RX configuration only; TX uses either Bluetooth LE UNCODED or Bluetooth LE LR configuration) + 0xB + + + GENLL_MODE15 + GTM Mode + 0xF + + + + + SEL_RXIRQ + Select the RX IRQ assert time + 5 + 1 + read-write + + + CLEAR + RX_IRQ is asserted at the end of RX_PKT state. + 0 + + + ASSERTED + RX_IRQ is asserted at the end of RXEN_DLY state. This to be used for delaying RX_IRQ to accept TERM2 bits in Bluetooth LE-LR and CTE bits as needed. + 0x1 + + + + + DATARATE_CONFIG_SEL + Select the data rate configuration bank + 6 + 1 + read-write + + + CLEAR + Select the data rate as per configuration bank 0 + 0 + + + ASSERTED + Select the data rate as per configuration bank 1 + 0x1 + + + + + STAY_IN_RX + Stay in receive + 7 + 1 + read-write + + + CLEAR + Linklayer will warmdown after an RX_IRQ + 0 + + + ASSERTED + Linklayer will recycle and stay in receive even after an RX_IRQ. + 0x1 + + + + + PHR_TYPE + PHR Type + 8 + 3 + read-write + + + GFSK + The packet type is GFSK + 0 + + + MSK + The packet type is MSK + 0x1 + + + SUNFSK + The packet type is SUN FSK + 0x2 + + + LECIMFSK + The packet type is LECIM FSK + 0x3 + + + + + SW_BUILD_ACK + Software builds the ACK packet in RAM + 11 + 1 + read-write + + + CLEAR + Hardware builds part of or the whole of the auto ACK frame + 0 + + + ASSERTED + Software builds the whole auto ACK frame in RAM. + 0x1 + + + + + ACKBUF_SEL + ACK frame is in 64-byte dedicated RAM or TX buffer RAM + 12 + 1 + read-write + + + CLEAR + ACK frame is in 64-byte dedicated RAM + 0 + + + ASSERTED + ACK frame is in TX buffer RAM + 0x1 + + + + + AUTOACK + Auto Acknowledge Enable + 13 + 1 + read-write + + + AUTOACK_0 + sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. + 0 + + + AUTOACK_1 + sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. + 0x1 + + + + + RXACKRQD + Receive Acknowledge Frame required + 14 + 1 + read-write + + + RXACKRQD_0 + An ordinary receive frame (any type of frame) follows the transmit frame. + 0 + + + RXACKRQD_1 + A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). + 0x1 + + + + + SLOTTED + Slotted Mode + 15 + 1 + read-write + + + LENGTH_ACK + Length of the ACK frame(or part of the ACK frame) in RAM + 16 + 11 + read-write + + + BLE_V5P1_CTE_EN + Bluetooth LE version 5.1 CTE feature enable + 31 + 1 + read-write + + + BLE_V5P1_CTE_EN_0 + Do not support Bluetooth LE version 5.1 CTE feature. + 0 + + + BLE_V5P1_CTE_EN_1 + Support Bluetooth LE version 5.1 CTE feature, which means the link layer hardware can parse the CTE field length and extend the RX_EN signal accordingly. + 0x1 + + + + + + + RX_FRAME_FILTER + RECEIVE FRAME FILTER + 0x94 + 32 + read-write + 0x60F + 0xFFFFFFFF + + + BEACON_FT + Beacon Frame Type Enable + 0 + 1 + read-write + + + BEACON_FT_0 + reject all Beacon frames + 0 + + + BEACON_FT_1 + Beacon frame type enabled. + 0x1 + + + + + DATA_FT + Data Frame Type Enable + 1 + 1 + read-write + + + DATA_FT_0 + reject all Beacon frames + 0 + + + DATA_FT_1 + Data frame type enabled. + 0x1 + + + + + ACK_FT + Ack Frame Type Enable + 2 + 1 + read-write + + + ACK_FT_0 + reject all Acknowledge frames + 0 + + + ACK_FT_1 + Acknowledge frame type enabled. + 0x1 + + + + + CMD_FT + MAC Command Frame Type Enable + 3 + 1 + read-write + + + CMD_FT_0 + reject all MAC Command frames + 0 + + + CMD_FT_1 + MAC Command frame type enabled. + 0x1 + + + + + LLDN_FT + LLDN Frame Type Enable + 4 + 1 + read-write + + + LLDN_FT_0 + reject all LLDN frames + 0 + + + LLDN_FT_1 + LLDN frame type enabled (Frame Type 4). + 0x1 + + + + + MULTIPURPOSE_FT + Multipurpose Frame Type Enable + 5 + 1 + read-write + + + MULTIPURPOSE_FT_0 + reject all Multipurpose frames + 0 + + + MULTIPURPOSE_FT_1 + Multipurpose frame type enabled (Frame Type 5). + 0x1 + + + + + FRAGMENT_FT + Fragment Frame Type Enable + 6 + 1 + read-write + + + FRAGMENT_FT_0 + reject all Fragment frames + 0 + + + FRAGMENT_FT_1 + Fragment frame type enabled (Frame Type 6). + 0x1 + + + + + EXTENDED_FT + Extended Frame Type Enable + 7 + 1 + read-write + + + EXTENDED_FT_0 + reject all Extended frames + 0 + + + EXTENDED_FT_1 + Extended frame type enabled (Frame Type 7). + 0x1 + + + + + NS_FT + "Not Specified" Frame Type Enable + 8 + 1 + read-write + + + NS_FT_0 + reject all "Not Specified" frames + 0 + + + NS_FT_1 + Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this Frame Type + 0x1 + + + + + FRM_VER_FILTER + Frame Version selector. + 9 + 4 + read-write + + + EXTENDED_FCS_CHK + Verify FCS on Frame Type Extended + 15 + 1 + read-write + + + EXTENDED_FCS_CHK_0 + Packet Processor will not check FCS for Frame Type EXTENDED (default) + 0 + + + EXTENDED_FCS_CHK_1 + Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED + 0x1 + + + + + FV2_BEACON_RECD + Frame Version 2 Beacon Packet Received + 16 + 1 + read-only + + + FV2_BEACON_RECD_0 + The last packet received was not Frame Type Beacon with Frame Version 2 + 0 + + + FV2_BEACON_RECD_1 + The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + FV2_DATA_RECD + Frame Version 2 Data Packet Received + 17 + 1 + read-only + + + FV2_DATA_RECD_0 + The last packet received was not Frame Type Data with Frame Version 2 + 0 + + + FV2_DATA_RECD_1 + The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + FV2_ACK_RECD + Frame Version 2 Acknowledge Packet Received + 18 + 1 + read-only + + + FV2_ACK_RECD_0 + The last packet received was not Frame Type Ack with Frame Version 2 + 0 + + + FV2_ACK_RECD_1 + The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + FV2_CMD_RECD + Frame Version 2 MAC Command Packet Received + 19 + 1 + read-only + + + FV2_CMD_RECD_0 + The last packet received was not Frame Type MAC Command with Frame Version 2 + 0 + + + FV2_CMD_RECD_1 + The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + 0x1 + + + + + LLDN_RECD + LLDN Packet Received + 20 + 1 + read-only + + + LLDN_RECD_0 + The last packet received was not Frame Type LLDN + 0 + + + LLDN_RECD_1 + The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets. + 0x1 + + + + + MULTIPURPOSE_RECD + Multipurpose Packet Received + 21 + 1 + read-only + + + MULTIPURPOSE_RECD_0 + last packet received was not Frame Type MULTIPURPOSE + 0 + + + MULTIPURPOSE_RECD_1 + The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets. + 0x1 + + + + + FRAGMENT_RECD + Fragment Packet Received + 22 + 1 + read-only + + + FRAGMENT_RECD_0 + last packet received was not Frame Type FRAGMENT + 0 + + + FRAGMENT_RECD_1 + The last packet received was Frame Type FRAGMENT, and FRAGMENT_FT=1 to allow such packets. + 0x1 + + + + + EXTENDED_RECD + Extended Packet Received + 23 + 1 + read-only + + + EXTENDED_RECD_0 + The last packet received was not Frame Type EXTENDED + 0 + + + EXTENDED_RECD_1 + The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets. + 0x1 + + + + + RXCYC_SEL + Rx Recycle Time Select + 28 + 1 + read-write + + + RXCYC_SEL_0 + Recycle when fail happens. + 0 + + + RXCYC_SEL_1 + Recycle when Rx done and fail happens. + 0x1 + + + + + FILTER_FAIL_IGNORE + Filter Fail Ignore + 29 + 1 + read-write + + + FILTER_FAIL_IGNORE_0 + RX_IRQ will not be asserted when filter fail. + 0 + + + FILTER_FAIL_IGNORE_1 + RX_IRQ will be asserted when filter fail. + 0x1 + + + + + PROMISCUOUS + Promiscuous Mode Enable + 30 + 1 + read-write + + + PROMISCUOUS_0 + normal mode + 0 + + + PROMISCUOUS_1 + all packet filtering except frame length checking (FrameLength>=5) is bypassed. + 0x1 + + + + + ENH_PKT_STATUS + Enhanced Packet Status + 31 + 1 + read-only + + + ENH_PKT_STATUS_0 + The last packet received was not 2015-compliant + 0 + + + ENH_PKT_STATUS_1 + The last packet received was 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits) + 0x1 + + + + + + + FILTERFAIL_CODE + FILTER FAIL CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILTERFAIL_CODE_PAN + Filter Fail Code When in PAN Mode + 0 + 10 + read-only + + + FILTERFAIL_CODE_FAN + Filter Fail Code When in FAN Mode + 16 + 2 + read-only + + + FILTERFAIL_PAN_SEL + PAN Selector for Filter Fail Code + 30 + 1 + read-write + + + FILTERFAIL_PAN_SEL_0 + FILTERFAIL_CODE_PAN/FILTERFAIL_CODE_FAN will report the FILTERFAIL status of PAN0 + 0 + + + FILTERFAIL_PAN_SEL_1 + FILTERFAIL_CODE_PAN/FILTERFAIL_CODE_FAN will report the FILTERFAIL status of PAN1 + 0x1 + + + + + FILTERFAIL_FLAG_SEL + Consolidated Filter Fail Flag + 31 + 1 + read-only + + + + + LENIENCY_LSB + LENIENCY LSB + LENIENCY_LSB + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + LENIENCY_LSB + Leniency LSB Register + 0 + 32 + read-write + + + + + RPA_CTRL + RPA CONTROL + LENIENCY_LSB + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + RPA_VALID_ENTRY + Here bits [7:0] corresponds to validity of 8th to 1st entry in RPA list respectively + 0 + 8 + read-write + + + IGNORE_RPA_FAIL + no description available + 27 + 1 + read-write + + + CLEAR + link layer aborts the Rx process when LOCAL_RPA_FAIL_IRQ or PEER_RPA_FAIL_IRQ + 0 + + + ASSERTED + link layer ignores LOCAL_RPA_FAIL_IRQ and PEER_RPA_FAIL_IRQ. + 0x1 + + + + + IGNORE_DIRECT_FAIL + no description available + 28 + 1 + read-write + + + CLEAR + link layer aborts the Rx process when DIRECT_ID_FAIL_IRQ + 0 + + + ASSERTED + link layer ignores DIRECT_ID_FAIL_IRQ. + 0x1 + + + + + ADV_DIRECT_IND_SENT + When set, it means the link layer is advertiser who has sent an ADV_DIRECT_IND + 29 + 1 + read-write + + + RPA_EN + no description available + 30 + 1 + read-write + + + CLEAR + The RPA check is disabled. + 0 + + + ASSERTED + The RPA check is enabled. + 0x1 + + + + + ADV_CHANNEL_EN + no description available + 31 + 1 + read-write + + + CLEAR + The packet to be received is in Data Channel PDU. + 0 + + + ASSERTED + The packet to be received is in Advertising Channel PDU. + 0x1 + + + + + + + LENIENCY_MSB + LENIENCY MSB + LENIENCY_MSB + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENIENCY_MSB + Leniency MSB Register + 0 + 13 + read-write + + + + + WL_CTRL + WHITE LIST CONTROL + LENIENCY_MSB + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_EN + no description available + 0 + 1 + read-write + + + CLEAR + White list search is not enabled + 0 + + + ASSERTED + White list search is enabled + 0x1 + + + + + WL_SEL + no description available + 1 + 1 + read-write + + + CLEAR + Select white list 0 + 0 + + + ASSERTED + Select white list 1 + 0x1 + + + + + IGNORE_WL_FAIL + no description available + 3 + 1 + read-write + + + CLEAR + link layer aborts the Rx process when WL_FAIL_IRQ + 0 + + + ASSERTED + link layer ignores WL_FAIL_IRQ. + 0x1 + + + + + + + DUAL_PAN_CTRL + DUAL PAN CONTROL + 0xA4 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + ACTIVE_NETWORK + Active Network Selector + 0 + 1 + read-write + + + ACTIVE_NETWORK_0 + Select PAN0 + 0 + + + ACTIVE_NETWORK_1 + Select PAN1 + 0x1 + + + + + DUAL_PAN_AUTO + Activates automatic Dual PAN operating mode + 1 + 1 + read-write + + + CURRENT_NETWORK + Indicates which PAN is currently selected by hardware + 2 + 1 + read-only + + + CURRENT_NETWORK_0 + PAN0 is selected + 0 + + + CURRENT_NETWORK_1 + PAN1 is selected + 0x1 + + + + + DUAL_PAN_DWELL + Dual PAN Channel Frequency Dwell Time + 8 + 8 + read-write + + + DUAL_PAN_REMAIN + Time Remaining before next PAN switch in auto Dual PAN mode + 16 + 6 + read-only + + + MODE_PAN0 + PAN0 Mode Select + 24 + 1 + read-write + + + MODE_PAN0_0 + PAN0 is in PAN mode + 0 + + + MODE_PAN0_1 + PAN0 is in FAN mode + 0x1 + + + + + MODE_PAN1 + PAN1 Mode Select + 25 + 1 + read-write + + + MODE_PAN1_0 + PAN1 is in PAN mode + 0 + + + MODE_PAN1_1 + PAN1 is in FAN mode + 0x1 + + + + + DP_CHAN_OVRD_EN + Dual PAN Channel Override Enable + 26 + 1 + read-write + + + DP_CHAN_OVRD_SEL + Dual PAN Channel Override Selector + 27 + 1 + read-write + + + PANCORDNTR0 + Device is a PAN Coordinator on PAN0 + 28 + 1 + read-write + + + PANCORDNTR1 + Device is a PAN Coordinator on PAN1 + 29 + 1 + read-write + + + RECD_ON_PAN0 + Last Packet was Received on PAN0 + 30 + 1 + read-only + + + RECD_ON_PAN1 + Last Packet was Received on PAN1 + 31 + 1 + read-only + + + + + GTM_PDU + GTM MODE PDU + MACSHORTADDRS1 + 0xA8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_PDU + GTM MODE PDU + 0 + 32 + read-write + + + + + MACSHORTADDRS1 + MAC SHORT ADDRESS FOR PAN1 + MACSHORTADDRS1 + 0xA8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACPANID1 + MAC PAN ID for PAN1 + 0 + 16 + read-write + + + MACSHORTADDRS1 + MAC SHORT ADDRESS for PAN1 + 16 + 16 + read-write + + + + + WL_VALID_ENTRY1 + VALID ENTRY OF WHITE LIST 1 + MACSHORTADDRS1 + 0xA8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + WL_VALID_ENTRY1 + Here bits [31:0] corresponds to validity of 32th to 1st entry in white list 1 respectively + 0 + 32 + read-write + + + + + DIRECT_PEER_ADDR_LSB + DIRECT_PEER_ADDR[31:0] + MACLONGADDRS1_LSB + 0xAC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DIRECT_PEER_ADDR_LSB + Lower 32 bit of 48-bit address of the direct peer device. + 0 + 32 + read-write + + + + + GTM_CFG + GTM MODE CONFIGURATION + MACLONGADDRS1_LSB + 0xAC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_PKT_NUM + GTM MODE PACKET NUMBER + 0 + 12 + read-write + + + GTM_PDU_TYPE + GTM MODE PDU TYPE SELECTION + 24 + 4 + read-write + + + GTM_PDU_TYPE0 + PRBS9 Sequence + 0 + + + GTM_PDU_TYPE1 + Programmable 8-bit Pattern (from register GTM_PDU[7:0], reused from MACSHORTADDRS1[7:0]) + 0x1 + + + GTM_PDU_TYPE2 + PRBS-13 Sequence + 0x2 + + + GTM_PDU_TYPE3 + PRBS-15 Sequence + 0x3 + + + GTM_PDU_TYPE4 + Programmable 32-bit Pattern (from register GTM_PDU[31:0], reused from {MACSHORTADDRS1,MACPANID1}) + 0x4 + + + GTM_PDU_TYPE5 + Programmable packet from Packet RAM (in this case, PKT_LEN is ignored) + 0x5 + + + + + GTM_IPD_CHECK_DIS + GTM MODE INTER-PACKET DURATION CHECK DISABLE + 30 + 1 + read-write + + + GTM_PKT_COUNT_CHECK_DIS + GTM MODE PACKET NUMBER CHECK DISABLE + 31 + 1 + read-write + + + + + MACLONGADDRS1_LSB + MAC LONG ADDRESS 1 LSB + MACLONGADDRS1_LSB + 0xAC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS1_LSB + MAC LONG ADDRESS for PAN1 LSB + 0 + 32 + read-write + + + + + DIRECT_PEER_ADDR_MSB + DIRECT_PEER_ADDR[47:32] + MACLONGADDRS1_MSB + 0xB0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DIRECT_PEER_ADDR_MSB + Higher 16 bit of 48-bit address of the direct peer device. + 0 + 16 + read-write + + + DIRECT_PEER_ADDR_TYPE + no description available + 31 + 1 + read-write + + + CLEAR + Direct peer device address type is public. + 0 + + + ASSERTED + Direct peer device address type is random. + 0x1 + + + + + + + GTM_IPD + GTM MODE INTER-PACKET DURATION + MACLONGADDRS1_MSB + 0xB0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_IPD + GTM MODE INTER-PACKET DURATION + 0 + 20 + read-write + + + + + MACLONGADDRS1_MSB + MAC LONG ADDRESS 1 MSB + MACLONGADDRS1_MSB + 0xB0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS1_MSB + MAC LONG ADDRESS for PAN1 MSB + 0 + 32 + read-write + + + + + CHANNEL_NUM1 + CHANNEL NUMBER 1 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHANNEL_NUM1 + Channel Number for PAN1 + 0 + 7 + read-write + + + + + MACSHORTADDRS0 + MAC SHORT ADDRESS 0 + MACSHORTADDRS0 + 0xB8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACPANID0 + MAC PAN ID for PAN0 + 0 + 16 + read-write + + + MACSHORTADDRS0 + MAC SHORT ADDRESS FOR PAN0 + 16 + 16 + read-write + + + + + WL_VALID_ENTRY0 + VALID ENTRY OF WHITE LIST 0 + MACSHORTADDRS0 + 0xB8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + WL_VALID_ENTRY0 + Here bits [31:0] corresponds to validity of 32th to 1st entry in white list 0 respectively + 0 + 32 + read-write + + + + + GTM_FIRST_SFD2WD + GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN + MACLONGADDRS0_LSB + 0xBC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_FIRST_SFD2WD + GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN + 0 + 20 + read-write + + + + + MACLONGADDRS0_LSB + MAC LONG ADDRESS 0 LSB + MACLONGADDRS0_LSB + 0xBC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS0_LSB + MAC LONG ADDRESS for PAN0 LSB + 0 + 32 + read-write + + + + + WL_SEARCH_ADDR_LSB + WL_SEARCH_ADDR[31:0] + MACLONGADDRS0_LSB + 0xBC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + WL_SEARCH_ADDR_LSB + Lower 32 bit of 48-bit address to be searched in white list. + 0 + 32 + read-write + + + + + GTM_RX_RECYCLE_TIME + GTM MODE RX RECYCLE TIME + MACLONGADDRS0_MSB + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_RX_RECYCLE_TIME + GTM MODE RX RECYCLE TIME + 0 + 20 + read-write + + + + + MACLONGADDRS0_MSB + MAC LONG ADDRESS 0 MSB + MACLONGADDRS0_MSB + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS0_MSB + MAC LONG ADDRESS for PAN0 MSB + 0 + 32 + read-write + + + + + WL_SEARCH_ADDR_MSB + WL_SEARCH_ADDR[47:32] + MACLONGADDRS0_MSB + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + WL_SEARCH_ADDR_MSB + Higher 16 bit of 48-bit address to be searched in white list. + 0 + 16 + read-write + + + WL_SEARCH_ADDR_TYPE + no description available + 31 + 1 + read-write + + + CLEAR + The address type is public. + 0 + + + ASSERTED + The address type is random. + 0x1 + + + + + + + CCA_LQI_CTRL + CCA AND LQI CONTROL + 0xC4 + 32 + read-write + 0x4B00 + 0xFFFFFFFF + + + CCABFRTX + CCA Before TX + 0 + 1 + read-write + + + CCABFRTX_0 + no CCA required, transmit operation begins immediately. + 0 + + + CCABFRTX_1 + at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). + 0x1 + + + + + SIMUL_CCA_RX + Simultaneous CCA and Receive Enable + 1 + 1 + read-write + + + SIMUL_CCA_RX_0 + Packets can't be received during CCA measurement + 0 + + + SIMUL_CCA_RX_1 + Packet reception is enabled during CCA measurement if preamble and SFD are detected + 0x1 + + + + + CCA + CCA Status + 7 + 1 + read-only + + + CCA_0 + IDLE + 0 + + + CCA_1 + BUSY + 0x1 + + + + + CCA1_THRESH + CCA Mode 1 Threshold + 8 + 8 + read-write + + + CCA1_ED_FNL + Final Result for CCA Mode 1 and Energy Detect + 16 + 8 + read-only + + + + + WARMUP_TIME + TX/RX WARMUP TIME + 0xC8 + 32 + read-only + 0x70005A + 0xFFFFFFFF + + + RX_WARMUP + Receive Warmup Time + 0 + 8 + read-only + + + TX_WARMUP + Transmit Warmup Time + 16 + 8 + read-only + + + + + RXEN_DLY + RX_EN Delay Time + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXEN_DLY + When RXEN_DLY is not zero, the RX_EN signal will delay (RXEN_DLY +1) microseconds to de-assert after packet is received + 0 + 10 + read-write + + + RXEN_DLY_OVERRIDE + RX_EN delay to de-assert time override enable. + 31 + 1 + read-write + + + RXEN_DLY_OVERRIDE_0 + For Bluetooth LE case, RX_EN signal will delay to de-assert accroding to the length of TERM2 or CTE(when BLE_V5P1_CTE_EN is enabled) field parsed by hardware + 0 + + + RXEN_DLY_OVERRIDE_1 + For all receive case, RX_EN signal will delay to de-assert accroding to register RXEN_DLY[9:0]. + 0x1 + + + + + + + SAM_CTRL + SAM CONTROL + 0xD4 + 32 + read-write + 0x80804000 + 0xFFFFFFFF + + + SAP0_EN + Enables SAP0 Partition of the SAM Table + 0 + 1 + read-write + + + SAP0_EN_0 + Disables SAP0 Partition + 0 + + + SAP0_EN_1 + Enables SAP0 Partition + 0x1 + + + + + SAA0_EN + Enables SAA0 Partition of the SAM Table + 1 + 1 + read-write + + + SAA0_EN_0 + Disables SAA0 Partition + 0 + + + SAA0_EN_1 + Enables SAA0 Partition + 0x1 + + + + + SAP1_EN + Enables SAP1 Partition of the SAM Table + 2 + 1 + read-write + + + SAP1_EN_0 + Disables SAP1 Partition + 0 + + + SAP1_EN_1 + Enables SAP1 Partition + 0x1 + + + + + SAA1_EN + Enables SAA1 Partition of the SAM Table + 3 + 1 + read-write + + + SAA1_EN_0 + Disables SAA1 Partition + 0 + + + SAA1_EN_1 + Enables SAA1 Partition + 0x1 + + + + + SAA0_START + First Index of SAA0 partition + 8 + 8 + read-write + + + SAP1_START + First Index of SAP1 partition + 16 + 8 + read-write + + + SAA1_START + First Index of SAA1 partition + 24 + 8 + read-write + + + + + SAM_TABLE + SOURCE ADDRESS MANAGEMENT TABLE + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SAM_INDEX + Contains the SAM table index to be enabled or invalidated + 0 + 7 + read-write + + + SAM_INDEX_WR + Enables SAM Table Contents to be updated + 7 + 1 + write-only + + + SAM_CHECKSUM + Software-computed source address checksum, to be installed into a table index + 8 + 16 + read-write + + + SAM_INDEX_INV + Invalidate the SAM table index selected by SAM_INDEX + 24 + 1 + write-only + + + SAM_INDEX_EN + Enable the SAM table index selected by SAM_INDEX + 25 + 1 + write-only + + + ACK_FRM_PND + State of AutoTxAck FramePending field when SAM Accelleration is Disabled + 26 + 1 + read-write + + + ACK_FRM_PND_CTRL + Manual Control for AutoTxAck FramePending field + 27 + 1 + read-write + + + ACK_FRM_PND_CTRL_0 + the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware + 0 + + + ACK_FRM_PND_CTRL_1 + the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND + 0x1 + + + + + FIND_FREE_IDX + Find First Free Index + 28 + 1 + write-only + + + INVALIDATE_ALL + Invalidate Entire SAM Table + 29 + 1 + write-only + + + SRCADDR + Source Address Match Status + 30 + 1 + read-only + + + SAM_BUSY + SAM Table Update Status Bit + 31 + 1 + read-only + + + + + SAM_MATCH + SOURCE ADDRESS MANAGEMENT MATCH + 0xDC + 32 + read-only + 0xFF7FFF7F + 0xFFFFFFFF + + + SAP0_MATCH + Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match + 0 + 7 + read-only + + + SAP0_ADDR_PRESENT + A Checksum Match is Present in the SAP0 Partition of the SAM Table + 7 + 1 + read-only + + + SAA0_MATCH + Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match + 8 + 7 + read-only + + + SAA0_ADDR_ABSENT + A Checksum Match is Absent in the SAA0 Partition of the SAM Table + 15 + 1 + read-only + + + SAP1_MATCH + Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match + 16 + 7 + read-only + + + SAP1_ADDR_PRESENT + A Checksum Match is Present in the SAP1 Partition of the SAM Table + 23 + 1 + read-only + + + SAA1_MATCH + Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match + 24 + 7 + read-only + + + SAA1_ADDR_ABSENT + A Checksum Match is Absent in the SAP1 Partition of the SAM Table + 31 + 1 + read-only + + + + + SAM_FREE_IDX + SAM FREE INDEX + 0xE0 + 32 + read-only + 0x80808080 + 0xFFFFFFFF + + + SAP0_1ST_FREE_IDX + First non-enabled (invalid) index in the SAP0 partition + 0 + 8 + read-only + + + SAA0_1ST_FREE_IDX + First non-enabled (invalid) index in the SAA0 partition + 8 + 8 + read-only + + + SAP1_1ST_FREE_IDX + First non-enabled (invalid) index in the SAP1 partition + 16 + 8 + read-only + + + SAA1_1ST_FREE_IDX + First non-enabled (invalid) index in the SAA1 partition + 24 + 8 + read-only + + + + + MISC1 + MISCELLANEOUS(1) + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRC_ADDR_CHECKSUM + Hardware-computed received source address checksum + 0 + 16 + read-only + + + SW_ABORTED + Autosequence has terminated due to a Software abort. + 16 + 1 + read-only + + + PLL_ABORTED + Autosequence has terminated due to an PLL unlock event. + 17 + 1 + read-only + + + EXT_ABORTED + Autosequence has terminated due to a Wake-On-Radio command + 18 + 1 + read-only + + + ARB_GRANT_DEASSERTION_ABORTED + Autosequence has terminated due to an arb_grant deassertion event + 19 + 1 + read-only + + + FAST_TX_WU_OVRD + FAST_TX_WU override + 28 + 1 + read-write + + + FAST_TX_WU_OVRD_0 + If TSM enables Fast Warmup Capability, LL will request it when TX in RT or (CCA+TX) + 0 + + + FAST_TX_WU_OVRD_1 + If TSM enables Fast Warmup Capability, LL will request it at every TX. User should insure channel is not changed since last sequence. + 0x1 + + + + + FAST_RX_WU_OVRD + FAST_RX_WU override + 29 + 1 + read-write + + + FAST_RX_WU_OVRD_0 + If TSM enables Fast Warmup Capability, LL will request it when RX in TR + 0 + + + FAST_RX_WU_OVRD_1 + If TSM enables Fast Warmup Capability, LL will request it at every RX. User should insure channel is not changed since last sequence. + 0x1 + + + + + PI + Poll Indication + 30 + 1 + read-only + + + PI_0 + the received packet was not a data request + 0 + + + PI_1 + the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not + 0x1 + + + + + RX_FRM_PEND + RX Frame Pending + 31 + 1 + read-only + + + + + SEQ_STS + SEQUENCE STATUS + 0xE8 + 32 + read-only + 0 + 0xFFFFFFFF + + + TX_START_T1_PEND + TX T1 Start Pending Status + 0 + 1 + read-only + + + TX_START_T2_PEND + TX T2 Start Pending Status + 1 + 1 + read-only + + + TX_IN_WARMUP + TX Warmup Status + 2 + 1 + read-only + + + TX_IN_PROGRESS + TX in Progress Status + 3 + 1 + read-only + + + TX_IN_WARMDN + TX Warmdown Status + 4 + 1 + read-only + + + RX_START_T1_PEND + RX T1 Start Pending Status + 5 + 1 + read-only + + + RX_START_T2_PEND + RX T2 Start Pending Status + 6 + 1 + read-only + + + RX_STOP_T1_PEND + RX T1 Stop Pending Status + 7 + 1 + read-only + + + RX_STOP_T2_PEND + RX T2 Start Pending Status + 8 + 1 + read-only + + + RX_IN_WARMUP + RX Warmup Status + 9 + 1 + read-only + + + RX_IN_SEARCH + RX Search Status + 10 + 1 + read-only + + + RX_IN_PROGRESS + RX in Progress Status + 11 + 1 + read-only + + + RX_IN_WARMDN + RX Warmdown Status + 12 + 1 + read-only + + + TR_START_T1_PEND + TR T1 Start Pending Status + 13 + 1 + read-only + + + TR_START_T2_PEND + TR T2 Start Pending Status + 14 + 1 + read-only + + + CCA_START_T1_PEND + CCA T1 Start Pending Status + 15 + 1 + read-only + + + CCA_START_T2_PEND + CCA T2 Start Pending Status + 16 + 1 + read-only + + + SEQ_T_STATUS + Status of the just-completed or ongoing Sequence T or Sequence TR + 24 + 5 + read-only + + + + + PHR_MISC + PHR MISCELLANEOUS + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + SUNFSK_MS + Mode Switch Bit + 0 + 1 + read-only + + + SUNFSK_MSP + Mode Switch Parameter Bit + 1 + 2 + read-only + + + SUNFSK_FEC + New Mode FEC Bit + 3 + 1 + read-only + + + SUNFSK_NM + New Mode Bit + 4 + 7 + read-only + + + PHR_FAIL_IGNORE + Ignore PHR Fail + 24 + 1 + read-write + + + + + GTM_CTRL + GTM CONTROL + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTM_IN_RX + Enable GTM Receive Mode + 0 + 1 + read-write + + + DISABLED + GTM receive mode is not enabled. + 0 + + + ENABLED + GTM receive mode is enabled. + 0x1 + + + + + GTM_IN_TX + Enable GTM Transmit Mode + 1 + 1 + read-write + + + DISABLED + GTM transmit mode is not enabled. + 0 + + + ENABLED + GTM transmit mode is enabled. + 0x1 + + + + + + + GTM_BAD_CNT + GTM BAD PACKET COUNTER + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + GTM_BAD_PKT_COUNT + GTM Bad Packet Counter + 0 + 13 + read-only + + + + + GTM_GOOD_CNT + GTM GOOD PACKET COUNTER + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + GTM_GOOD_PKT_COUNT + GTM Good Packet Counter + 0 + 13 + read-only + + + + + GTM_PKT_CNT + GTM PACKET COUNTER + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + GTM_PKT_COUNT + GTM Packet Counter + 0 + 13 + read-only + + + + + COEX_CTRL + COEXISTENCE CONTROL + 0x100 + 32 + read-write + 0x300 + 0xFFFFFFFF + + + COEX_EN + Coexistence Enable + 0 + 1 + read-write + + + COEX_EN_0 + Coexistence function is disabled. + 0 + + + COEX_EN_1 + Coexistence function is enabled. + 0x1 + + + + + COEX_REQ_DELAY_EN + Coexistence Request Delay Enable + 1 + 1 + read-write + + + COEX_REQ_DELAY_EN_0 + arb_request is not delayed during R sequence. + 0 + + + COEX_REQ_DELAY_EN_1 + arb_request is delayed until preamble or Access Address is detected during R sequence. + 0x1 + + + + + COEX_REQ_ON_PD + Coexistence Request on Preamble detected + 2 + 1 + read-write + + + COEX_REQ_ON_PD_0 + arb_request is delayed until Access Address is detected during R sequence. + 0 + + + COEX_REQ_ON_PD_1 + arb_request is delayed until preamble is detected during R sequence. + 0x1 + + + + + COEX_TIMEOUT + Coexistence timeout value + 8 + 8 + read-write + + + + + COEX_PRIORITY + COEXISTENCE PRIORITY + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIORITY_T + PRIORITY_T + 0 + 2 + read-write + + + PRIORITY_R_PRE + PRIORITY_R_PRE + 2 + 2 + read-write + + + PRIORITY_R_PKT + PRIORITY_R_PKT + 4 + 2 + read-write + + + PRIORITY_TACK + PRIORITY_TACK + 6 + 2 + read-write + + + PRIORITY_CCA + PRIORITY_CCA + 8 + 2 + read-write + + + PRIORITY_CTX + PRIORITY_CT + 12 + 2 + read-write + + + PRIORITY_RACK_PRE + PRIORITY_RACK_PRE + 14 + 2 + read-write + + + PRIORITY_RACK_PKT + PRIORITY_RACK_PKT + 16 + 2 + read-write + + + PRIORITY_OVRD + PRIORITY_OVRD + 29 + 2 + read-write + + + PRIORITY_OVRD_EN + PRIORITY_OVRD_EN + 31 + 1 + read-write + + + PRIORITY_OVRD_EN_0 + Disable overriding PRIORITY value. + 0 + + + PRIORITY_OVRD_EN_1 + Enable overriding PRIORITY value. + 0x1 + + + + + + + IRQ_CTRL2 + IRQ CONTROL 2 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARB_GRANT_DEASSERTION_IRQ + arb_grant Deassertion IRQ + 0 + 1 + read-write + oneToClear + + + ARB_GRANT_DEASSERTION_IRQ_0 + An arb_grant Deassertion Interrupt has not occurred + 0 + + + ARB_GRANT_DEASSERTION_IRQ_1 + An arb_grant Deassertion Interrupt has occurred + 0x1 + + + + + COEX_TIMEOUT_IRQ + Coexistence Timeout Interrupt + 1 + 1 + read-write + oneToClear + + + EVENT_TIMER_OVER_FLOW_IRQ + Event Timer Overflow Interrupt + 2 + 1 + read-write + oneToClear + + + WL_FAIL_IRQ + White List Check Fail Interrupt + 3 + 1 + read-write + oneToClear + + + DIRECT_ID_FAIL_IRQ + Direct Case Check Fail Interrupt + 4 + 1 + read-write + oneToClear + + + PEER_RPA_FAIL_IRQ + Peer RPA Check Fail Interrupt + 5 + 1 + read-write + oneToClear + + + LOCAL_RPA_FAIL_IRQ + Local RPA Check Fail Interrupt + 6 + 1 + read-write + oneToClear + + + ARB_GRANT_DEASSERTION_IRQ_EN + arb_grant Deassertion Interrupt enable + 16 + 1 + read-write + + + ARB_GRANT_DEASSERTION_IRQ_EN_0 + An arb_grant deassertion event will set the ARB_GRANT_DEASSERTION_IRQ status bit, but no interrupt is not generated + 0 + + + ARB_GRANT_DEASSERTION_IRQ_EN_1 + allows arb_grant deassertion event to generate an interrupt + 0x1 + + + + + COEX_TIMEOUT_IRQ_EN + Coexistence Timeout Interrupt enable bit + 17 + 1 + read-write + + + COEX_TIMEOUT_IRQ_EN_0 + Interrupt generation is disabled, but a COEX_TIMEOUT_IRQ flag can be set + 0 + + + COEX_TIMEOUT_IRQ_EN_1 + allows interrupt when coexistence timeout + 0x1 + + + + + EVENT_TIMER_OVER_FLOW_IRQ_EN + Event Timer Overflow Interrupt enable bit + 18 + 1 + read-write + + + EVENT_TIMER_OVER_FLOW_IRQ_EN_0 + Interrupt generation is disabled, but an EVENT_TIMER_OVER_FLOW_IRQ flag can be set + 0 + + + EVENT_TIMER_OVER_FLOW_IRQ_EN_1 + allows interrupt when Event Timer overflow + 0x1 + + + + + WL_FAIL_IRQ_EN + no description available + 19 + 1 + read-write + + + CLEAR + WL_FAIL Interrupt is not enabled. + 0 + + + ASSERTED + WL_FAIL Interrupt is enabled. + 0x1 + + + + + DIRECT_ID_FAIL_IRQ_EN + no description available + 20 + 1 + read-write + + + CLEAR + DIRECT_ID_FAIL Interrupt is not enabled. + 0 + + + ASSERTED + DIRECT_ID_FAIL Interrupt is enabled. + 0x1 + + + + + PEER_RPA_FAIL_IRQ_EN + no description available + 21 + 1 + read-write + + + CLEAR + PEER_RPA_FAIL Interrupt is not enabled. + 0 + + + ASSERTED + PEER_RPA_FAIL Interrupt is enabled. + 0x1 + + + + + LOCAL_RPA_FAIL_IRQ_EN + no description available + 22 + 1 + read-write + + + CLEAR + LOCAL_RPA_FAIL Interrupt is not enabled. + 0 + + + ASSERTED + LOCAL_RPA_FAIL Interrupt is enabled. + 0x1 + + + + + + + + + RADIO_CTRL + RADIO_MISC + RADIO_CTRL + 0x48A06000 + + 0 + 0x34 + registers + + + + LL_STATUS + LL Status Register + 0 + 32 + read-only + 0x7 + 0xFFFFFFFF + + + LL_PRESENT + LL present status + 0 + 6 + read-only + + + BLE_VERSION + Bluetooth LE Version + 8 + 4 + read-only + + + BLE_VERSION_0 + No Bluetooth LE + 0 + + + BLE_VERSION_1 + Bluetooth LE 5.1 + 0x1 + + + BLE_VERSION_2 + Bluetooth LE 5.2 + 0x2 + + + BLE_VERSION_3 + Bluetooth LE 5.3 + 0x3 + + + BLE_VERSION_15 + Bluetooth LE Upgrade + 0xF + + + + + + + LL_CTRL + LL Control Register + 0x4 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + ACTIVE_LL + link layer control register + 0 + 2 + read-write + + + ACTIVE_LL_0 + Bluetooth LE LL is selected + 0 + + + ACTIVE_LL_1 + ZIGBEE LL is selected + 0x1 + + + ACTIVE_LL_2 + GENERIC LL is selected + 0x2 + + + ACTIVE_LL_3 + Disabled (default) + 0x3 + + + + + + + RF_CTRL + Radio Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RBME_MODE_OVRD_EN + RBME Mode Override Enable + 0 + 1 + read-write + + + RBME_MODE_OVRD_EN_0 + RBME Mode Override Disable + 0 + + + RBME_MODE_OVRD_EN_1 + RBME Mode Override Enable + 0x1 + + + + + RBME_MODE_OVRD + RBME Mode Override + 1 + 3 + read-write + + + RX_CON_EN_OVRD_EN + rx_con_en Override Enable + 4 + 1 + read-write + + + RX_CON_EN_OVRD_EN_0 + rx_con_en Override Disable + 0 + + + RX_CON_EN_OVRD_EN_1 + rx_con_en Override Enable + 0x1 + + + + + RX_CON_EN_OVRD + rx_con_en Override + 5 + 1 + read-write + + + BLE_LR_EN_OVRD_EN + ble_lr_en Override Enable + 6 + 1 + read-write + + + BLE_LR_EN_OVRD_EN_0 + ble_lr_en Override Disable + 0 + + + BLE_LR_EN_OVRD_EN_1 + ble_lr_en Override Enable + 0x1 + + + + + BLE_LR_EN_OVRD + ble_lr_en Override + 7 + 1 + read-write + + + RIF_SEL_2MBPS_OVRD_EN + rif_sel_2mbps Override Enable + 8 + 1 + read-write + + + RIF_SEL_2MBPS_OVRD_EN_0 + rif_sel_2mbps Override Disable + 0 + + + RIF_SEL_2MBPS_OVRD_EN_1 + rif_sel_2mbps Override Enable + 0x1 + + + + + RIF_SEL_2MBPS_OVRD + rif_sel_2mbps Override + 9 + 1 + read-write + + + WOR_RX_FAIL_WAKEUP_EN + WOR RX Fail Wakeup Enable + 28 + 1 + read-write + + + WOR_RX_FAIL_WAKEUP_EN_0 + The wor_rx_fail interrupt doesn't assert rfmc_wakeup. + 0 + + + WOR_RX_FAIL_WAKEUP_EN_1 + The wor_rx_fail interrupt asserts rfmc_wakeup. + 0x1 + + + + + BRIC_WAKEUP_EN + BRIC Wakeup Enable + 29 + 1 + read-write + + + BRIC_WAKEUP_EN_0 + The BRIC interrupt doesn't assert rfmc_wakeup. + 0 + + + BRIC_WAKEUP_EN_1 + The BRIC interrupt asserts rfmc_wakeup. + 0x1 + + + + + GENERIC_WAKEUP_EN + Generic LL Wakeup Enable + 30 + 1 + read-write + + + GENERIC_WAKEUP_EN_0 + The Generic LL interrupt doesn't assert rfmc_wakeup. + 0 + + + GENERIC_WAKEUP_EN_1 + The Genecir LL interrupt asserts rfmc_wakeup. + 0x1 + + + + + ZIGBEE_WAKEUP_EN + Zigbee LL Wakeup Enable + 31 + 1 + read-write + + + ZIGBEE_WAKEUP_EN_0 + The Zigbee LL interrupt doesn't assert rfmc_wakeup. + 0 + + + ZIGBEE_WAKEUP_EN_1 + The Zigbee LL interrupt asserts rfmc_wakeup. + 0x1 + + + + + + + RF_CLK_CTRL + Radio Clock Control Register + 0xC + 32 + read-write + 0x801FFF00 + 0xFFFFFFFF + + + ZBLL_CLK_EN_OVRD + ZBLL Clock Enable Override + 0 + 1 + read-write + + + ZBLL_CLK_EN_OVRD_0 + ZBLL clock force on is disabled. + 0 + + + ZBLL_CLK_EN_OVRD_1 + ZBLL clock force on is enabled. + 0x1 + + + + + GENLL_CLK_EN_OVRD + GENLL Clock Enable Override + 1 + 1 + read-write + + + GENLL_CLK_EN_OVRD_0 + GENLL clock force on is disabled. + 0 + + + GENLL_CLK_EN_OVRD_1 + GENLL clock force on is enabled. + 0x1 + + + + + BTLL_CLK_EN_OVRD + BTLL Clock Enable Override + 2 + 1 + read-write + + + BTLL_CLK_EN_OVRD_0 + BTLL clock force on is disabled. + 0 + + + BTLL_CLK_EN_OVRD_1 + BTLL clock force on is enabled. + 0x1 + + + + + BTU_EBRAM_CLK_ON_OVRD + BTU EBRAM Clock Enable Override + 3 + 1 + read-write + + + BTU_EBRAM_CLK_ON_OVRD_0 + btu_ebram_clk is not forced on. + 0 + + + BTU_EBRAM_CLK_ON_OVRD_1 + btu_ebram_clk is forced on. + 0x1 + + + + + BT_ECLK_DIV + BE_ECLK Divider + 4 + 1 + read-write + + + BT_ECLK_DIV_0 + ref_clk is not divided as bt_eclk. + 0 + + + BT_ECLK_DIV_1 + ref_clk is divided by 2 as bt_eclk. + 0x1 + + + + + NBU_HCLK_EN + NBU HCLK Enable + 8 + 1 + read-write + + + NBU_HCLK_EN_0 + nbu hclk/cpu_hclk are disabled. + 0 + + + NBU_HCLK_EN_1 + nbu hclk/cpu_hclk are enabled. + 0x1 + + + + + CM3_HCLK_EN + CM3 HCLK Enable + 9 + 1 + read-write + + + CM3_HCLK_EN_0 + cm3_hclk is disabled. + 0 + + + CM3_HCLK_EN_1 + cm3_hclk is enabled. + 0x1 + + + + + BLE_AHB_CLK_EN + BLE_AHB CLOCK Enable + 10 + 1 + read-write + + + BLE_AHB_CLK_EN_0 + ble_ahb_clk is disabled. + 0 + + + BLE_AHB_CLK_EN_1 + ble_ahb_clk is enabled. + 0x1 + + + + + NBU_PKB_CLK_EN + NBU PKB Clock Enable + 11 + 1 + read-write + + + NBU_PKB_CLK_EN_0 + nbu_pkb_clk is disabled. + 0 + + + NBU_PKB_CLK_EN_1 + nbu_pkb_clk is enabled. + 0x1 + + + + + BT_16M_CLK_EN + BT 16M Clock Enable + 12 + 1 + read-write + + + BT_16M_CLK_EN_0 + bt_16m_clk is disabled. + 0 + + + BT_16M_CLK_EN_1 + bt_16m_clk is enabled. + 0x1 + + + + + RTU_CLK_EN + RTU Clock Enable + 13 + 1 + read-write + + + RTU_CLK_EN_0 + rtu_clk is disabled. + 0 + + + RTU_CLK_EN_1 + rtu_clk is enabled. + 0x1 + + + + + BT_4M_CLK_EN + BT 4M Clock Enable + 14 + 1 + read-write + + + BT_4M_CLK_EN_0 + bt_4m_clk is disabled. + 0 + + + BT_4M_CLK_EN_1 + bt_4m_clk is enabled. + 0x1 + + + + + BT_REF_4M_CLK_EN + BT REF 4M Clock Enable + 15 + 1 + read-write + + + BT_REF_4M_CLK_EN_0 + bt_ref_4m_clk is disabled. + 0 + + + BT_REF_4M_CLK_EN_1 + bt_ref_4m_clk is enabled. + 0x1 + + + + + BT_XCVR_4M_CLK_EN + BT XCVR 4M Clock Enable + 16 + 1 + read-write + + + BT_XCVR_4M_CLK_EN_0 + bt_xcvr_4m_clk is disabled. + 0 + + + BT_XCVR_4M_CLK_EN_1 + bt_xcvr_4m_clk is enabled. + 0x1 + + + + + BT_XCVR_32M_CLK_EN + BT XCVR 32M Clock Enable + 17 + 1 + read-write + + + BT_XCVR_32M_CLK_EN_0 + bt_xcvr_32m_clk is disabled. + 0 + + + BT_XCVR_32M_CLK_EN_1 + bt_xcvr_32m_clk is enabled. + 0x1 + + + + + BT_ECLK_EN + BT_ECLK Enable + 18 + 1 + read-write + + + BT_ECLK_EN_0 + bt_eclk is disabled. + 0 + + + BT_ECLK_EN_1 + bt_eclk is enabled. + 0x1 + + + + + BLE_AES_CLK_EN + BLE_AES_CLK Enable + 19 + 1 + read-write + + + BLE_AES_CLK_EN_0 + bt_aes_clk is disabled. + 0 + + + BLE_AES_CLK_EN_1 + bt_aes_clk is enabled. + 0x1 + + + + + UART_CLK_EN + UART Clock Enable + 20 + 1 + read-write + + + UART_CLK_EN_0 + uart_clk is disabled. + 0 + + + UART_CLK_EN_1 + uart_clk is enabled. + 0x1 + + + + + MAN_DS_EN + Manual deep sleep control enable + 29 + 1 + read-write + + + MAN_DS_EN_0 + Disable the control of rfmc_man_deep_sleep_enable for nbu_hclk. + 0 + + + MAN_DS_EN_1 + Enable the control of rfmc_man_deep_sleep_enable for nbu_hclk. + 0x1 + + + + + WOR_DS_EN + WOR deep sleep control enable + 30 + 1 + read-write + + + WOR_DS_EN_0 + Disable the control of rfmc_wor_deep_sleep_enable for nbu_hclk. + 0 + + + WOR_DS_EN_1 + Enable the control of rfmc_wor_deep_sleep_enable for nbu_hclk. + 0x1 + + + + + BT_CLK_REQ_EN + BT_CLK_REQ control enable + 31 + 1 + read-write + + + BT_CLK_REQ_EN_0 + Disable the control of bt_clk_req for nbu_hclk. + 0 + + + BT_CLK_REQ_EN_1 + Enable the control of bt_clk_req for nbu_hclk. + 0x1 + + + + + + + COEX_CTRL + COEXISTENCE CONTROL + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RF_NOT_ALLOWED_EN + RF_NOT_ALLOWED PER-LINK-LAYER ENABLE + 0 + 4 + read-write + + + RF_NOT_ALLOWED_ASSERTED + RF_NOT_ALLOWED_ASSERTED + 4 + 1 + read-write + oneToClear + + + RF_NOT_ALLOWED_ASSERTED_0 + Assertion on RF_NOT_ALLOWED has not occurred + 0 + + + RF_NOT_ALLOWED_ASSERTED_1 + Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared + 0x1 + + + + + RF_NOT_ALLOWED + RF_NOT_ALLOWED + 5 + 1 + read-only + + + RF_NOT_ALLOWED_OVRD + RF_NOT_ALLOWED Override + 6 + 1 + read-write + + + RF_NOT_ALLOWED_OVRD_EN + RF_NOT_ALLOWED Override Enable + 7 + 1 + read-write + + + RF_NOT_ALLOWED_OVRD_EN_0 + RF_NALLOWED Override Disable + 0 + + + RF_NOT_ALLOWED_OVRD_EN_1 + RF_NALLOWED Override Enable + 0x1 + + + + + RF_NALLOWED_INV + RF_NALLOWED Invert + 8 + 1 + read-write + + + RF_NALLOWED_INV_0 + rf_nallowed is not inverted. + 0 + + + RF_NALLOWED_INV_1 + rf_nallowed is inverted. + 0x1 + + + + + RF_ACTIVE_INV + RF_ACTIVE Invert + 9 + 1 + read-write + + + RF_ACTIVE_INV_0 + rf_active is not inverted. + 0 + + + RF_ACTIVE_INV_1 + rf_active is inverted. + 0x1 + + + + + RF_PRIORITY_INV + RF_PRIORITY Invert + 10 + 2 + read-write + + + RF_PRIORITY_INV_0 + rf_priority[0] is not inverted. + #x0 + + + RF_PRIORITY_INV_1 + rf_priority[0] is inverted. + #x1 + + + + + RF_STATUS_INV + RF_STATUS Invert + 12 + 1 + read-write + + + RF_STATUS_INV_0 + rf_status is not inverted. + 0 + + + RF_STATUS_INV_1 + rf_status is inverted. + 0x1 + + + + + COEX_SEL + COEX_SEL + 13 + 1 + read-write + + + COEX_SEL_0 + Select coexistence signals from LL. + 0 + + + COEX_SEL_1 + Select coexistence signals from TSM. + 0x1 + + + + + + + UID_MSB + Radio Control Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RADIO_UID_MSB + The most signficant 8bits of the 40bit Radio UID. + 0 + 8 + read-only + + + + + UID_LSB + Radio Control Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RADIO_UID_LSB + The least signficant 32bits of the 40bit Radio UID. + 0 + 32 + read-only + + + + + PACKET_RAM_CTRL + PACKET RAM Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PB_PROTECT + PB_PROTECT + 0 + 1 + read-write + + + PB_PROTECT_0 + Incoming receive data can overwrite the existing contents of the RX section of the Packet Buffer. + 0 + + + PB_PROTECT_1 + Incoming receive data is been blocked from overwriting the existing contents of the RX section of the Packet Buffer. + 0x1 + + + + + + + BLE_PHY_CTRL + BLE PHY Interface Control Register + 0x20 + 32 + read-write + 0xF0F1222 + 0xFFFFFFFF + + + CTE_AVG_SAMP_SEL + Sampling select + 0 + 2 + read-write + + + READ_START_OFFSET_1M + Start sending Rx data to NBU after a programmable number of symbols are received from PHY - 1M + 4 + 4 + read-write + + + READ_START_OFFSET_2M + Start sending Rx data to NBU after a programmable number of symbols are received from PHY - 2M + 8 + 4 + read-write + + + READ_START_OFFSET_LR + Start sending Rx data to NBU after a programmable number of symbols are received from PHY - LR + 12 + 4 + read-write + + + GUARD_TIME_1M + Guard time offset for 1M + 16 + 8 + read-write + + + GUARD_TIME_2M + Guard time offset for 2M + 24 + 6 + read-write + + + AVG_IQ_DISABLE + Disable IQ sample averaging + 30 + 1 + read-write + + + CTE_SINGLE_BUF + Config for using single buffer for Rx data and CTE samples + 31 + 1 + read-write + + + + + DTEST_CTRL + DTEST Control register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTEST_PAGE + DTEST PAGE Number + 0 + 7 + read-write + + + DTEST_EN + DTEST_EN control + 7 + 1 + read-write + + + DTEST_EN_0 + disable dtest feature + 0 + + + DTEST_EN_1 + enable dtest feature + 0x1 + + + + + DTEST_OUT_REG_EN + Enable/Disable register dtest signal + 8 + 1 + read-write + + + DTEST_OUT_REG_EN_0 + output dtest signal directly + 0 + + + DTEST_OUT_REG_EN_1 + output dtest signal after registered + 0x1 + + + + + RAW_MODE_I + Select rx_dig_i as DTEST RX_IQ page + 9 + 1 + read-write + + + RAW_MODE_Q + Select rx_dig_q as DTEST RX_IQ page + 10 + 1 + read-write + + + DTEST_SHIFT + DTEST shift control + 11 + 3 + read-write + + + + + DTEST_PIN_CTRL2 + DTEST PIN Control 2 register + 0x30 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + DTEST_PIN8_MUX_SEL + DTEST_PIN8_MUX_SEL + 0 + 4 + read-write + + + DTEST_PIN8_OVRD_SEL + DTEST_PIN8_OVRD_SEL + 4 + 4 + read-write + + + DTEST_PIN8_OVRD_SEL_0 + override is disabled + 0 + + + DTEST_PIN8_OVRD_SEL_1 + aa_sfd_matched + 0x1 + + + DTEST_PIN8_OVRD_SEL_2 + rx_pd_fnd + 0x2 + + + DTEST_PIN8_OVRD_SEL_3 + agc_gain_change + 0x3 + + + DTEST_PIN8_OVRD_SEL_4 + tsm_combined_tx_en + 0x4 + + + DTEST_PIN8_OVRD_SEL_5 + tsm_combined_rx_en + 0x5 + + + DTEST_PIN8_OVRD_SEL_6 + crc_fail + 0x6 + + + DTEST_PIN8_OVRD_SEL_7 + decode_data_out + 0x7 + + + DTEST_PIN8_OVRD_SEL_8 + tx_data_out + 0x8 + + + DTEST_PIN8_OVRD_SEL_9 + nbu_testbus[14] + 0x9 + + + DTEST_PIN8_OVRD_SEL_10 + nbu_testbus[15] + 0xA + + + + + DTEST_PIN9_MUX_SEL + DTEST_PIN9_MUX_SEL + 8 + 4 + read-write + + + DTEST_PIN9_OVRD_SEL + DTEST_PIN9_OVRD_SEL + 12 + 4 + read-write + + + DTEST_PIN9_OVRD_SEL_0 + override is disabled + 0 + + + DTEST_PIN9_OVRD_SEL_1 + aa_sfd_matched + 0x1 + + + DTEST_PIN9_OVRD_SEL_2 + rx_pd_fnd + 0x2 + + + DTEST_PIN9_OVRD_SEL_3 + agc_gain_change + 0x3 + + + DTEST_PIN9_OVRD_SEL_4 + tsm_combined_tx_en + 0x4 + + + DTEST_PIN9_OVRD_SEL_5 + tsm_combined_rx_en + 0x5 + + + DTEST_PIN9_OVRD_SEL_6 + crc_fail + 0x6 + + + DTEST_PIN9_OVRD_SEL_7 + decode_data_out + 0x7 + + + DTEST_PIN9_OVRD_SEL_8 + tx_data_out + 0x8 + + + DTEST_PIN9_OVRD_SEL_9 + nbu_testbus[14] + 0x9 + + + DTEST_PIN9_OVRD_SEL_10 + nbu_testbus[15] + 0xA + + + + + DTEST_PIN10_MUX_SEL + DTEST_PIN10_MUX_SEL + 16 + 4 + read-write + + + DTEST_PIN10_OVRD_SEL + DTEST_PIN10_OVRD_SEL + 20 + 4 + read-write + + + DTEST_PIN10_OVRD_SEL_0 + override is disabled + 0 + + + DTEST_PIN10_OVRD_SEL_1 + aa_sfd_matched + 0x1 + + + DTEST_PIN10_OVRD_SEL_2 + rx_pd_fnd + 0x2 + + + DTEST_PIN10_OVRD_SEL_3 + agc_gain_change + 0x3 + + + DTEST_PIN10_OVRD_SEL_4 + tsm_combined_tx_en + 0x4 + + + DTEST_PIN10_OVRD_SEL_5 + tsm_combined_rx_en + 0x5 + + + DTEST_PIN10_OVRD_SEL_6 + crc_fail + 0x6 + + + DTEST_PIN10_OVRD_SEL_7 + decode_data_out + 0x7 + + + DTEST_PIN10_OVRD_SEL_8 + tx_data_out + 0x8 + + + DTEST_PIN10_OVRD_SEL_9 + nbu_testbus[14] + 0x9 + + + DTEST_PIN10_OVRD_SEL_10 + nbu_testbus[15] + 0xA + + + + + DTEST_PIN11_MUX_SEL + DTEST_PIN11_MUX_SEL + 24 + 4 + read-write + + + DTEST_PIN11_OVRD_SEL + DTEST_PIN11_OVRD_SEL + 28 + 4 + read-write + + + DTEST_PIN11_OVRD_SEL_0 + override is disabled + 0 + + + DTEST_PIN11_OVRD_SEL_1 + aa_sfd_matched + 0x1 + + + DTEST_PIN11_OVRD_SEL_2 + rx_pd_fnd + 0x2 + + + DTEST_PIN11_OVRD_SEL_3 + agc_gain_change + 0x3 + + + DTEST_PIN11_OVRD_SEL_4 + tsm_combined_tx_en + 0x4 + + + DTEST_PIN11_OVRD_SEL_5 + tsm_combined_rx_en + 0x5 + + + DTEST_PIN11_OVRD_SEL_6 + crc_fail + 0x6 + + + DTEST_PIN11_OVRD_SEL_7 + decode_data_out + 0x7 + + + DTEST_PIN11_OVRD_SEL_8 + tx_data_out + 0x8 + + + DTEST_PIN11_OVRD_SEL_9 + nbu_testbus[14] + 0x9 + + + DTEST_PIN11_OVRD_SEL_10 + nbu_testbus[15] + 0xA + + + + + + + + + WOR_REGS + WOR + WOR + 0x48A06100 + + 0 + 0xAC + registers + + + RF_WOR + 52 + + + + CTRL + WAKE-ON-RADIO CONTROL REGISTER + 0 + 32 + read-write + 0x70000 + 0xFFFFFFFF + + + WOR_EN + WAKE-ON-RADIO Enable + 0 + 1 + read-write + + + SCHEDULING_MODE + WAKE-ON-RADIO Scheduling Mode + 1 + 1 + read-write + + + WOR_PROTOCOL + WAKE-ON-RADIO Protocol Selector + 2 + 2 + read-write + + + SLOTS_USED + WAKE-ON-RADIO Number Of Slots Used + 4 + 3 + read-write + + + SKIP_FIRST_DSM + WAKE-ON-RADIO Skip DSM On First Slot + 7 + 1 + read-write + + + MAN_DSM_SEL + Manual DSM Selector + 8 + 2 + read-write + + + RX_SLOT_FAIL_THRESH + RX Slot Fail Thresh + 10 + 5 + read-write + + + DSM_GUARDBAND + WAKE-ON-RADIO DSM Guardband + 16 + 4 + read-write + + + WOR_RESUME + WAKE-ON-RADIO Resume + 24 + 1 + write-only + + + WOR_DEBUG_REG + WAKE-ON-RADIO Debug Register Enable + 25 + 1 + read-write + + + AUTO_CAL + Auto calculate and track the drift enable + 28 + 1 + read-write + + + SW_CAL + Enable the WOR SW to calculate the drift. Only when AUTO_CAL is set. + 29 + 1 + read-write + + + TIME_REC + Enable the WOR HW to record the timing information to the Packet RAM. + 30 + 1 + read-write + + + WOR_RX_FAIL_IRQ_EN + WOR_RX_FAIL_IRQ Enable + 31 + 1 + read-write + + + + + TIMEOUT + WAKE-ON-RADIO TIMEOUT REGISTER + 0x4 + 32 + read-write + 0xFF0000 + 0xFFFFFFFF + + + RECEIVE_TIMEOUT + WAKE-ON-RADIO Receive Timeout + 0 + 16 + read-write + + + WAKE_ON_NTH_SLOT + WAKE-ON-RADIO Force Wake On Nth Slot + 16 + 8 + read-write + + + WOR_SLOT_COUNT + WAKE-ON-RADIO Absolute Slot Count + 24 + 8 + read-only + + + + + TIMESTAMP1 + WAKE-ON-RADIO TIMESTAMP 1 + 0x8 + 32 + read-only + 0 + 0 + + + TIMESTAMP1 + WAKE-ON-RADIO TIMESTAMP1 + 0 + 32 + read-only + + + + + TIMESTAMP2 + WAKE-ON-RADIO TIMESTAMP 2 + 0xC + 32 + read-only + 0 + 0 + + + TIMESTAMP2 + WAKE-ON-RADIO TIMESTAMP2 + 0 + 32 + read-only + + + + + TIMESTAMP3 + WAKE-ON-RADIO TIMESTAMP 3 + 0x10 + 32 + read-only + 0 + 0 + + + TIMESTAMP3 + WAKE-ON-RADIO TIMESTAMP3 + 0 + 32 + read-only + + + + + STATUS + WAKE-ON-RADIO STATUS REGISTER + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMESTAMP0_STS + WAKE-ON-RADIO Timestamp 0 Status + 0 + 3 + read-only + + + TIMESTAMP1_STS + WAKE-ON-RADIO Timestamp 1 Status + 3 + 3 + read-only + + + TIMESTAMP2_STS + WAKE-ON-RADIO Timestamp 2 Status + 6 + 3 + read-only + + + TIMESTAMP3_STS + WAKE-ON-RADIO Timestamp 3 Status + 9 + 3 + read-only + + + SLOT + WAKE-ON-RADIO Current Slot + 12 + 2 + read-only + + + WOR_NO_RF_FLAG + WAKE-ON-RADIO NO_RF Slot Flag + 16 + 1 + read-only + + + WOR_MAX_SLOT_FLAG + WAKE-ON-RADIO Maximum Slot Count Reached Flag + 17 + 1 + read-only + + + WOR_DSM_EXIT_FLAG + WAKE-ON-RADIO Early DSM Exit Flag + 18 + 1 + read-only + + + WOR_STATE + WAKE-ON-RADIO Current State + 20 + 4 + read-only + + + WOR_RX_FAIL_IRQ + WOR RX Fail Interrupt Flag + 31 + 1 + read-write + oneToClear + + + + + WW_CTRL + WINDOW-WIDENING CONTROL REGISTER + 0x18 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + WW_EN + Window-widening Enable + 0 + 1 + read-write + + + WW_RESET_ON_RX + Window-widening Reset on Received Good Packet + 1 + 1 + read-write + + + WW_NULL + Window-widening Null Command + 2 + 1 + write-only + + + WW_ADD + Window-widening Add Command + 3 + 1 + write-only + + + WW_DSM_FACTOR + Window-widening DSM Factor + 8 + 6 + read-write + + + WW_RUN_FACTOR + Window-widening Runtime Factor + 16 + 5 + read-write + + + WW_INCREASE + Window-widening Manual Increase Amount + 24 + 8 + read-write + + + + + HOP_CTRL + FREQUENCY HOP CONTROL REGISTER + 0x1C + 32 + read-write + 0x300000 + 0xFFFFFFFF + + + HOP_TBL_CFG + Hop Table Configuration + 0 + 3 + read-write + + + NEW_HOP_IDX + New Hop Table Index + 8 + 7 + read-write + + + UPDATE_HOP_IDX + Update Hop Table Index + 15 + 1 + write-only + + + HOP_SEQ_LENGTH + New Hop Table Index + 16 + 8 + read-write + + + + + SLOT0_DESC0 + SLOT 0 DESCRIPTOR (LSB) + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT0_DESC0 + Slot 0 Descriptor (LSB's) + 0 + 32 + read-write + + + + + SLOT0_DESC1 + SLOT 0 DESCRIPTOR (MSB) + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT0_DESC1 + Slot 0 Descriptor (MSB's) + 0 + 6 + read-write + + + WOR_HOP_IDX + Current Hop Table Index + 8 + 7 + read-only + + + WOR_HOP_FREQ_WORD + Current Hop Frequency Word + 16 + 16 + read-only + + + + + SLOT1_DESC0 + SLOT 1 DESCRIPTOR (LSB) + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT1_DESC0 + Slot 1 Descriptor (LSB's) + 0 + 32 + read-write + + + + + SLOT1_DESC1 + SLOT 1 DESCRIPTOR (MSB) + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT1_DESC1 + Slot 1 Descriptor (MSB's) + 0 + 6 + read-write + + + + + SLOT2_DESC0 + SLOT 2 DESCRIPTOR (LSB) + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT2_DESC0 + Slot 2 Descriptor (LSB's) + 0 + 32 + read-write + + + + + SLOT2_DESC1 + SLOT 2 DESCRIPTOR (MSB) + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT2_DESC1 + Slot 2 Descriptor (MSB's) + 0 + 6 + read-write + + + + + SLOT3_DESC0 + SLOT 3 DESCRIPTOR (LSB) + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT3_DESC0 + Slot 3 Descriptor (LSB's) + 0 + 32 + read-write + + + + + SLOT3_DESC1 + SLOT 3 DESCRIPTOR (MSB) + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOT3_DESC1 + Slot 3 Descriptor (MSB's) + 0 + 6 + read-write + + + + + AUTO_DRIFT1 + Auto Drift Calculation Register 1 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_DRIFT_SET + Software calculated drift. + 0 + 7 + read-write + + + CAL_DSM_FACTOR + Hardware calculated drift. + 16 + 7 + read-only + + + + + AUTO_DRIFT2 + Auto Drift Calculation Register 2 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + AA_SFD_DLY + The time duration of Preamble and Sync Address plus the RX warm up duration. + 0 + 16 + read-write + + + + + AUTO_DRIFT3 + Auto Drift Calculation Register 3 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_MGN + The time margin applied to the start time and timeout. + 0 + 16 + read-write + + + + + AUTO_DRIFT4 + Auto Drift Calculation Register 4 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + TINT_DIV_MILLION + User programed value to help the hardware to calculate the drift + 0 + 24 + read-write + + + + + TIME + Timer Count + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIME + Current 32kHz reference clock time (used by the MAN low power controller). + 0 + 24 + read-only + + + + + ENTER_TIME_CAPT + MAN Low Power Entry Time Captured + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + ENTER_TIME_CAPT + Captured Timer count for MAN entry to low power + 0 + 24 + read-only + + + + + WKUP_TIME_CAPT + MAN Low Power Wakeup Time Captured + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + WKUP_TIME_CAPT + Captured Timer count for MAN exit from low power + 0 + 24 + read-only + + + + + ENTER_TIME + MAN Low Power Entry Time Stamp + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENTER_TIME + Timer count at which to initiate low power entry by the MAN. + 0 + 24 + read-write + + + + + WKUP_TIME + MAN Low Power Wakeup Time Stamp + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WKUP_TIME + Timer count at which to complete low power wakeup by the MAN. + 0 + 24 + read-write + + + + + + + RBME + RBME + RBME + 0x48A06200 + + 0 + 0x100 + registers + + + + CRCW_CFG + CRC/WHITENER CONFIG REGISTER + 0 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + CRCW_EN + CRC calculation enable + 0 + 1 + read-write + + + CRCW_EC_EN + CRC Error Correction Enable + 1 + 1 + read-write + + + CRC_ZERO + CRC zero + 2 + 1 + read-only + + + CRC_EARLY_FAIL + CRC error correction fail + 3 + 1 + read-only + + + CRC_RES_OUT_VLD + CRC result output valid + 4 + 1 + read-only + + + CRC_EC_OFFSET + CRC error correction offset + 16 + 11 + read-only + + + CRC_EC_DONE + CRC error correction done + 28 + 1 + read-only + + + CRC_EC_FAIL + CRC error correction fail + 29 + 1 + read-only + + + + + CRC_EC_MASK + CRC ERROR CORRECTION MASK + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CRC_EC_MASK + CRC error correction mask + 0 + 32 + read-only + + + + + CRC_RES_OUT + CRC RESULT + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CRC_RES_OUT + CRC result output + 0 + 32 + read-only + + + + + CRCW_CFG2 + CRC/WHITENER CONFIG 2 REGISTER + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_EC_SPKT_BYTES + Error Correction Short Packet Bytes + 0 + 8 + read-write + + + CRC_EC_SPKT_WND + Error correction short packet burst error window + 8 + 4 + read-write + + + CRC_EC_LPKT_WND + Error correction long packet burst error window + 12 + 4 + read-write + + + + + CRCW_CFG3 + CRC CONFIGURATION + 0x10 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CRC_SZ + CRC Size (in octets) + 0 + 3 + read-write + + + CRC_START_BYTE + Configure CRC Start Point + 8 + 4 + read-write + + + CRC_REF_IN + CRC Reflect In + 16 + 1 + read-write + + + CRC_REF_IN_0 + Does not manipulate input data stream + 0 + + + CRC_REF_IN_1 + reflect each byte in the input stream bitwise + 0x1 + + + + + CRC_REF_OUT + CRC Reflect Out + 17 + 1 + read-write + + + CRC_REF_OUT_0 + Does not manipulate CRC result + 0 + + + CRC_REF_OUT_1 + CRC result is to be reflected bitwise (operated on entire word) + 0x1 + + + + + CRC_BYTE_ORD + CRC Byte Order + 18 + 1 + read-write + + + CRC_BYTE_ORD_0 + LS Byte First + 0 + + + CRC_BYTE_ORD_1 + MS Byte First + 0x1 + + + + + + + CRC_INIT + CRC INITIALIZATION + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_SEED + CRC Seed Value + 0 + 32 + read-write + + + + + CRC_POLY + CRC POLYNOMIAL + 0x18 + 32 + read-write + 0x10210000 + 0xFFFFFFFF + + + CRC_POLY + CRC Polynomial. + 0 + 32 + read-write + + + + + CRC_XOR_OUT + CRC XOR OUT + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_XOR_OUT + CRC XOR OUT Register + 0 + 32 + read-write + + + + + WHITEN_CFG + WHITENER CONFIGURATION + 0x20 + 32 + read-write + 0x1FF0918 + 0xFFFFFFFF + + + WHITEN_START + Configure Whitener Start Point + 0 + 2 + read-write + + + WHITEN_START_0 + no whitening + 0 + + + WHITEN_START_1 + start whitening at start-of-H0 + 0x1 + + + WHITEN_START_2 + start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR + 0x2 + + + WHITEN_START_3 + start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR + 0x3 + + + + + WHITEN_END + Configure end-of-whitening + 2 + 1 + read-write + + + WHITEN_END_0 + end whiten at end-of-payload + 0 + + + WHITEN_END_1 + end whiten at end-of-crc + 0x1 + + + + + WHITEN_B4_CRC + Congifure for Whitening-before-CRC + 3 + 1 + read-write + + + WHITEN_B4_CRC_0 + CRC before whiten/de-whiten + 0 + + + WHITEN_B4_CRC_1 + Whiten/de-whiten before CRC + 0x1 + + + + + WHITEN_POLY_TYPE + Whiten Polynomial Type + 4 + 1 + read-write + + + WHITEN_REF_IN + Whiten Reflect Input + 5 + 1 + read-write + + + WHITEN_PAYLOAD_REINIT + Configure for Whitener re-initialization + 6 + 1 + read-write + + + WHITEN_PAYLOAD_REINIT_0 + Does not re-initialize Whitener LFSR at start-of-payload + 0 + + + WHITEN_PAYLOAD_REINIT_1 + Re-initialize Whitener LFSR at start-of-payload + 0x1 + + + + + WHITEN_SIZE + Length of Whitener LFSR + 8 + 4 + read-write + + + WHITEN_INIT + Initialization value for whitening/de-whitening + 16 + 9 + read-write + + + + + WHITEN_POLY + WHITENER POLYNOMIAL + 0x24 + 32 + read-write + 0x21 + 0xFFFFFFFF + + + WHITEN_POLY + Whitener Polynomial + 0 + 9 + read-write + + + + + WHITEN_SZ_THR + WHITENER SIZE THRESHOLD + 0x28 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + WHITEN_SZ_THR + Whitener Size Threshold + 0 + 12 + read-write + + + + + FEC_CFG1 + FEC CONFIG REGISTER 1 + 0x2C + 32 + read-write + 0x300 + 0xFFFFFFFF + + + FEC_EN + FEC enable + 0 + 1 + read-write + + + FEC_EN_0 + Disable FEC encoder and decoder + 0 + + + FEC_EN_1 + Enable FEC encoder and decoder + 0x1 + + + + + FEC_SWAP + FEC output swap + 1 + 1 + read-write + + + FECOV_EN + Enable dynamic overide of FEC + 2 + 1 + read-write + + + FECOV_EN_0 + Disable FEC override + 0 + + + FECOV_EN_1 + The override of FEC is only used in Bluetooth LE LR cases, dynamically depending on the LR AA detected + 0x1 + + + + + INTV_EN + Enable interleaver reigster + 4 + 1 + read-write + + + FEC_START_BYTE + FEC Start Byte + 5 + 3 + read-write + + + NTERM + Number of term bits + 8 + 3 + read-write + + + + + RBME_RST + RBME SOFT RESET REGISTER + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RBME_RST + RBME reset signal + 0 + 1 + read-write + + + RBME_RST_0 + Disable soft reset + 0 + + + RBME_RST_1 + Enable soft reset. When this bit is write to 1, the soft reset to RBME happens immediately. Then all internal registers and functions will be reset. + 0x1 + + + + + RBME_CLK_EN_OVRD + RBME Clock Enable override + 1 + 1 + read-write + + + + + FEC_CFG2 + FEC CONFIG REGISTER 2 + 0x34 + 32 + read-write + 0x3F7F10 + 0xFFFFFFFF + + + TB_LENGTH + Trace-back length + 0 + 5 + read-write + + + SAT_VL + Saturation value for PM + 8 + 8 + read-write + + + LARGE_VL + Large value used at startup phase, assigned to the initial PMs. + 16 + 7 + read-write + + + SDIDX + Index of startup state. PM(startStIdx)=0 + 24 + 3 + read-write + + + + + SPREAD_CFG + SPREADER CONFIG REGISTER + 0x3C + 32 + read-write + 0xC0200 + 0xFFFFFFFF + + + SP_EN + Spreader Enable bit + 0 + 1 + read-write + + + SP_EN_0 + Disable spreader + 0 + + + SP_EN_1 + Enable spreader + 0x1 + + + + + SPOV_EN + Spreader Override Enable + 1 + 1 + read-write + + + SPOV_EN_0 + Does not allow active override of the spreading enable + 0 + + + SPOV_EN_1 + Allows active override of the spreading enable + 0x1 + + + + + CI_TX + Bluetooth LE + 2 + 1 + read-write + + + CI_TX_0 + FEC Block 2 coded using S=8 + 0 + + + CI_TX_1 + FEC Block 2 coded using S=2 + 0x1 + + + + + SP_START_BYTE + Spread Start Byte + 3 + 3 + read-write + + + SP_FACTOR + Spreading Factor + 8 + 3 + read-write + + + SP_FACTOR_0 + Factor = 1(No spreading and despreading) + 0 + + + SP_FACTOR_1 + Factor = 2 + 0x1 + + + SP_FACTOR_2 + Factor = 4 + 0x2 + + + SP_FACTOR_3 + Factor = 8 + 0x3 + + + SP_FACTOR_4 + Factor = 16 + 0x4 + + + + + SP_SEQ + Spreading Bit Sequence + 16 + 16 + read-write + + + + + WHT_CFG + WHITEN CONFIG REGISTER + 0x40 + 32 + read-write + 0x2001000 + 0xFFFFFFFF + + + W1_EN + Enable first whitener + 0 + 1 + read-write + + + WFIRST + Whitens before CRC + 2 + 1 + read-write + + + WTOV_EN + Allows overwrite of the whitening + 3 + 1 + read-write + + + WT_OUT_SEL + Selected Output + 12 + 4 + read-write + + + WT_TPOGY + Whiten 1 Polynomial Type + 24 + 2 + read-write + + + + + PKT_SZ + PACKET SIZE REGISTER + 0x44 + 32 + read-write + 0x224000 + 0xFFFFFFFF + + + MAX_PKT_SZ + Maximum Packet Size In Bits + 0 + 16 + read-write + + + DEF_PKT_SZ + Default Packet Size + 16 + 16 + read-write + + + + + CRC_PHR_SZ + LENGTH OF PHR CONFIG REGISTER + 0x48 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + PHR_SZ + PHR Size Config + 0 + 4 + read-write + + + + + FCP_CFG + FCP SUPPORT CONFIG REGISTER + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FCP_SUPPORT + FCP Suppport + 0 + 1 + read-write + + + FCP_SUPPORT_0 + Disable FCP support + 0 + + + FCP_SUPPORT_1 + Enable FCP support + 0x1 + + + + + + + FRAME_OVER_SZ + FRAME OVERRIDE SIZE REGISTER + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + STD_FRM_OV_EN + Overrides actvie STD frame length from link layer enable bit + 0 + 1 + read-write + + + STD_FRM_OV_EN_0 + Disable override actvie STD frame length from link layer + 0 + + + STD_FRM_OV_EN_1 + Enable override actvie STD frame length from link layer + 0x1 + + + + + STD_FRM_OV + Value to overide the STD frame length (bits) + 16 + 11 + read-write + + + + + FEC_BSZ_OV_B4SP + OVERRIDE OF FEC BLOCK SIZE REGISTER + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEC_BSZ_OV_B4SP_EN + Override of the FEC block size for data + 0 + 1 + read-write + + + FEC_BSZ_OV_B4SP_EN_0 + Disable Override actvie STD frame length from link layer + 0 + + + FEC_BSZ_OV_B4SP_EN_1 + Enable Override actvie STD frame length from link layer + 0x1 + + + + + FEC_BSZ_OV + Value of the override in bits. It is for test purpose. + 16 + 16 + read-write + + + + + LEG0_CFG + LEG0 CONFIG REGISTER + 0x58 + 32 + read-write + 0xF202DD00 + 0xFFFFFFFF + + + LEG0_INV_EN + Whiten invert enable bit + 0 + 1 + read-write + + + LEG0_INV_EN_0 + Disable whiten invert for LEG0 + 0 + + + LEG0_INV_EN_1 + Enable whiten invert for LEG0 + 0x1 + + + + + LEG0_SUP + LEG0 support register + 1 + 1 + read-write + + + LEG0_SUP_0 + Disable LEG0 support + 0 + + + LEG0_SUP_1 + Enable LEG0 support + 0x1 + + + + + LEG0_XOR_BYTE + LEG0 whitening masking byte + 8 + 8 + read-write + + + LEG0_XOR_RP_BYTE + LEG0 repeat bytes masking + 16 + 8 + read-write + + + LEG0_XOR_FST_BYTE + FEC first byte masking + 24 + 8 + read-write + + + + + NPAYL_OVER_SZ + OVERRIDE PAYLOAD LENGTH REGISTER + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + NPAYL_OV_EN + Override the internal payload length computation + 0 + 1 + read-write + + + NPAYL_OV_EN_0 + Disable override the internal payload length + 0 + + + NPAYL_OV_EN_1 + Enable override the internal payload length + 0x1 + + + + + FT_FEC_FLUSH + Value to overide the payload length (bits) + 8 + 5 + read-write + + + NPAYL_OV + no description available + 16 + 11 + read-write + + + + + RAM_S_ADDR + PACKET RAM SOURCE ADDRESS + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_S_ADDR + Packet RAM source address. This address is ram physical address. + 0 + 14 + read-write + + + + + RAM_D_ADDR + PACKET RAM DESTINATION ADDRESS + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_D_ADDR + Packet RAM destination address, this address is ram physical address. + 0 + 14 + read-write + + + + + RAM_IF_CFG + PACKET RAM INTERFACE CONFIG REGISTER + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_IF_TX_EN + RAM interface TX enable bit + 0 + 1 + read-write + + + RAM_IF_TX_EN_0 + Disable RAM interface TX + 0 + + + RAM_IF_TX_EN_1 + Enable RAM interface TX + 0x1 + + + + + RAM_IF_RX_EN + RAM interface RX enable + 1 + 1 + read-write + + + RAM_IF_RX_EN_0 + Disable RAM interface RX + 0 + + + RAM_IF_RX_EN_1 + Enable RAM interface RX + 0x1 + + + + + RAM_IF_IE + RAM interface interrupt enable bit + 4 + 1 + read-write + + + RAM_IF_IE_0 + Disable RAM interface interrupt + 0 + + + RAM_IF_IE_1 + Enable RAM interface interrupt + 0x1 + + + + + RAM_IF_IC + RAM interface interrupt clear + 5 + 1 + read-write + + + RAM_IF_IC_0 + To do nothing to RAM interface interrupt + 0 + + + RAM_IF_IC_1 + To clear RAM interface interrupt + 0x1 + + + + + H2S_EN + Hard bit convert to soft bit enable + 6 + 1 + read-write + + + H2S_EN_0 + Disable hard bit to soft bits coversion + 0 + + + H2S_EN_1 + Enable hard bit to soft bits coversion + 0x1 + + + + + SOFT_HD_SEL_RD + Soft and hard bit selection of write operation + 8 + 1 + read-write + + + SOFT_HD_SEL_RD_0 + Hard bit selection of write operation + 0 + + + SOFT_HD_SEL_RD_1 + Soft bit selection of write operation + 0x1 + + + + + SOFT_HD_SEL_WR + Soft and hard bit selection of read operation + 9 + 1 + read-write + + + SOFT_HD_SEL_WR_0 + Hard bit selection of read operation + 0 + + + SOFT_HD_SEL_WR_1 + Soft bit selection of read operation + 0x1 + + + + + WR_IRQ + Write to RAM complete flag + 10 + 1 + read-only + + + WR_IRQ_0 + Writing to RAM not complete + 0 + + + WR_IRQ_1 + Writing to RAM complete + 0x1 + + + + + RD_IRQ + Read to RAM complete flag + 11 + 1 + read-only + + + RD_IRQ_0 + Reading to RAM not complete + 0 + + + RD_IRQ_1 + Reading to RAM complete + 0x1 + + + + + + + + + BRIC + BRIC + BRIC + 0x48A06700 + + 0 + 0xFF + registers + + + + 4 + 0x4 + KEY0_[%s] + KEY0 Registers (PKB) + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEY0_x + KEY0 written through PKB interface + 0 + 32 + write-only + + + + + 4 + 0x4 + KEY1_[%s] + KEY1 Registers (PKB) + 0x10 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEY1_x + KEY1 written through PKB interface + 0 + 32 + write-only + + + + + BRIC_CONFIG + BRIC CONFIG register + 0x20 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + KEY_INDEX + KEY INDEX + 0 + 8 + read-write + + + IPS_XFR_ERR_EN + Enable (0x1) ips_xfr_err generation on IPS access during HW mode + 8 + 1 + read-write + + + IPS_XFR_WAIT_EN + Enable (0x1) ips_xfr_wait generation on IPS access during HW mode + 9 + 1 + read-write + + + HI_MODE + Indicates HW mode request to BRIC is active + 10 + 1 + read-only + + + HI_READY + Indicates HW mode is in progress and any SW access during this time is responded with an IPS_ERROR or IPS_WAIT depending on the configuration + 11 + 1 + read-only + + + DIS_PKB_ERR_RESP + Disable (0x1) PKB error response (Error response will be forced to zero) + 12 + 1 + read-write + + + + + + + LTC + LTC + LTC + 0x48A06800 + + 0 + 0x7F4 + registers + + + + MD + Mode Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENC + Encrypt/Decrypt. + 0 + 1 + read-write + + + DECRYPT + Decrypt. + 0 + + + ENCRYPT + Encrypt. + 0x1 + + + + + ICV_TEST + ICV Checking / Test AES fault detection. + 1 + 1 + read-write + + + AS + Algorithm State + 2 + 2 + read-write + + + UPDATE + Update + 0 + + + INITIALIZE + Initialize + 0x1 + + + FINALIZE + Finalize + 0x2 + + + INITFINAL + Initialize/Finalize + 0x3 + + + + + AAI + Additional Algorithm information + 4 + 9 + read-write + + + ALG + Algorithm + 16 + 8 + read-write + + + AES + AES + 0x10 + + + + + + + KS + Key Size Register + 0x8 + 32 + write-only + 0x10 + 0xFFFFFFFF + + + KS + Key Size + 0 + 5 + write-only + + + + + DS + Data Size Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS + Data Size + 0 + 12 + read-write + + + + + ICVS + ICV Size Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICVS + ICV Size, in Bytes + 0 + 5 + read-write + + + + + COM + Command Register + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + ALL + Reset All Internal Logic + 0 + 1 + write-only + + + NO_RESET + Do Not Reset + 0 + + + RESET_ALL + Reset all CHAs in use by this CCB. + 0x1 + + + + + AES + Reset AESA + 1 + 1 + write-only + + + NO_RESET + Do Not Reset + 0 + + + RESET_AESA + Reset AES Accelerator + 0x1 + + + + + + + CTL + Control Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IM + Interrupt Mask + 0 + 1 + read-write + + + INT_NOT_MASKED + Interrupt not masked. + 0 + + + INT_MASKED + Interrupt masked + 0x1 + + + + + IFE + Input FIFO DMA Enable + 8 + 1 + read-write + + + IFE_DISABLED + DMA Request and Done signals disabled for the Input FIFO. + 0 + + + IFE_ENABLED + DMA Request and Done signals enabled for the Input FIFO. + 0x1 + + + + + IFR + Input FIFO DMA Request Size + 9 + 1 + read-write + + + IFR_1 + DMA request size is 1 entry. + 0 + + + IFR_4 + DMA request size is 4 entries. + 0x1 + + + + + OFE + Output FIFO DMA Enable + 12 + 1 + read-write + + + OFE_DISABLED + DMA Request and Done signals disabled for the Output FIFO. + 0 + + + OFE_ENABLED + DMA Request and Done signals enabled for the Output FIFO. + 0x1 + + + + + OFR + Output FIFO DMA Request Size + 13 + 1 + read-write + + + OFR_1 + DMA request size is 1 entry. + 0 + + + OFR_4 + DMA request size is 4 entries. + 0x1 + + + + + IFS + Input FIFO Byte Swap + 16 + 1 + read-write + + + IFS_NO_SWAP + Do Not Byte Swap Data. + 0 + + + IFS_SWAP + Byte Swap Data. + 0x1 + + + + + OFS + Output FIFO Byte Swap + 17 + 1 + read-write + + + OFS_NO_SWAP + Do Not Byte Swap Data. + 0 + + + OFS_SWAP + Byte Swap Data. + 0x1 + + + + + KIS + Key Register Input Byte Swap + 20 + 1 + read-write + + + KIS_NO_SWAP + Do Not Byte Swap Data. + 0 + + + KIS_SWAP + Byte Swap Data. + 0x1 + + + + + KOS + Key Register Output Byte Swap + 21 + 1 + read-write + + + KOS_NO_SWAP + Do Not Byte Swap Data. + 0 + + + KOS_SWAP + Byte Swap Data. + 0x1 + + + + + CIS + Context Register Input Byte Swap + 22 + 1 + read-write + + + CIS_NO_SWAP + Do Not Byte Swap Data. + 0 + + + CIS_SWAP + Byte Swap Data. + 0x1 + + + + + COS + Context Register Output Byte Swap + 23 + 1 + read-write + + + COS_NO_SWAP + Do Not Byte Swap Data. + 0 + + + COS_SWAP + Byte Swap Data. + 0x1 + + + + + KAL + Key Register Access Lock + 31 + 1 + read-write + + + KAL_READABLE + Key Register is readable. + 0 + + + KAL_NOT_READABLE + Key Register is not readable. + 0x1 + + + + + + + CW + Clear Written Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + CM + Clear the Mode Register + 0 + 1 + write-only + + + CDS + Clear the Data Size Register + 2 + 1 + write-only + + + CICV + Clear the ICV Size Register + 3 + 1 + write-only + + + CCR + Clear the Context Register + 5 + 1 + write-only + + + CKR + Clear the Key Register + 6 + 1 + write-only + + + COF + Clear Output FIFO + 30 + 1 + write-only + + + CIF + Clear Input FIFO + 31 + 1 + write-only + + + + + STA + Status Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + AB + AESA Busy + 1 + 1 + read-only + + + AESA_IDLE + AESA Idle + 0 + + + AESA_BUSY + AESA Busy. + 0x1 + + + + + DI + Done Interrupt + 16 + 1 + read-write + oneToClear + + + EI + Error Interrupt + 20 + 1 + read-only + + + NOT_ERROR_INT + Not Error. + 0 + + + ERROR_INT + Error Interrupt. + 0x1 + + + + + + + ESTA + Error Status Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + ERRID1 + Error ID 1 + 0 + 4 + read-only + + + MODE_ERROR + Mode Error + 0x1 + + + DATA_SIZE_ERROR + Data Size Error + 0x2 + + + KEY_SIZE_ERROR + Key Size Error + 0x3 + + + DATA_OUT_OF_SEQ_ERROR + Data Arrived out of Sequence Error + 0x6 + + + ICV_CHECK_FAIL + ICV Check Failed + 0xA + + + INTERNAL_HARD_FAIL + Internal Hardware Failure + 0xB + + + CCM_AAD_SIZE_ERROR + CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) + 0xC + + + INVALID_ENGINE_SEL_ERROR + Invalid Crypto Engine Selected + 0xF + + + + + CL1 + algorithms + 8 + 4 + read-only + + + GEN_ERROR + General Error + 0 + + + AES_ERROR + AES + 0x1 + + + + + + + AADSZ + AAD Size Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + AADSZ + AAD size in Bytes, mod 16 + 0 + 4 + read-write + + + AL + AAD Last + 31 + 1 + read-write + + + + + 14 + 0x4 + CTX_[%s] + Context Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + 4 + 0x4 + KEY_[%s] + Key Registers + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY + KEY + 0 + 32 + read-write + + + + + VID1 + Version ID Register + 0x4F0 + 32 + read-only + 0x340100 + 0xFFFFFFFF + + + MIN_REV + Minor revision number. + 0 + 8 + read-only + + + MAJ_REV + Major revision number. + 8 + 8 + read-only + + + IP_ID + ID(0x0034). + 16 + 16 + read-only + + + + + VID2 + Version ID 2 Register + 0x4F4 + 32 + read-only + 0x101 + 0xFFFFFFFF + + + ECO_REV + ECO revision number. + 0 + 8 + read-only + + + ARCH_ERA + Architectural ERA. + 8 + 8 + read-only + + + + + CHAVID + CHA Version ID Register + 0x4F8 + 32 + read-only + 0x50 + 0xFFFFFFFF + + + AESREV + AES Revision Number + 0 + 4 + read-only + + + AESVID + AES Version ID + 4 + 4 + read-only + + + + + FIFOSTA + FIFO Status Register + 0x7C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + IFL + Input FIFO Level + 0 + 7 + read-only + + + IFF + Input FIFO Full + 15 + 1 + read-only + + + OFL + Output FIFO Level + 16 + 7 + read-only + + + OFF + Output FIFO Full + 31 + 1 + read-only + + + + + IFIFO + Input Data FIFO + 0x7E0 + 32 + write-only + 0 + 0xFFFFFFFF + + + IFIFO + IFIFO + 0 + 32 + write-only + + + + + OFIFO + Output Data FIFO + 0x7F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + OFIFO + Output FIFO + 0 + 32 + read-only + + + + + + + XCVR_RX_DIG + 2P4GHZ_RX_DIG + XCVR_RX_DIG + 0x48A07000 + + 0 + 0x200 + registers + + + + CTRL0 + RXDIG Control 0 + 0 + 32 + read-write + 0x20003000 + 0xFFFFFFFF + + + ADC_CLIP_EN + ADC Output Clip Enable + 0 + 1 + read-write + + + ADC_CLIP_EN_0 + ADC clip is disabled. + 0 + + + ADC_CLIP_EN_1 + ADC clip is enabled. + 0x1 + + + + + RX_IQMC_EN + IQ Mismatch Compensation Enable + 1 + 1 + read-write + + + RX_IQMC_EN_0 + IQ mismatch compensation is disabled. + 0 + + + RX_IQMC_EN_1 + IQ mismatch compensation is enabled. + 0x1 + + + + + DIG_MIXER_FREQ + Digital Mixer Frequency + 2 + 9 + read-write + + + CIC_ORDER + CIC Order(Stage) Selection + 11 + 1 + read-write + + + CIC_ORDER_0 + 4-stage CIC + 0 + + + CIC_ORDER_1 + 3-stage CIC + 0x1 + + + + + CIC_RATE + CIC Decimation Rate + 12 + 3 + read-write + + + CIC_RATE_0 + Decimation Rate is 1. + 0 + + + CIC_RATE_1 + Decimation Rate is 2. + 0x1 + + + CIC_RATE_2 + Decimation Rate is 4. + 0x2 + + + CIC_RATE_3 + Decimation Rate is 8. + 0x3 + + + CIC_RATE_4 + Decimation Rate is 16. + 0x4 + + + CIC_RATE_5 + Decimation Rate is 32. + 0x5 + + + + + RX_DIG_GAIN + RX Digital Gain Value + 16 + 3 + read-write + + + RX_DIG_GAIN_0 + Digital gain value is 1.000. + 0 + + + RX_DIG_GAIN_1 + Digital gain value is 1.125. + 0x1 + + + RX_DIG_GAIN_2 + Digital gain value is 1.250. + 0x2 + + + RX_DIG_GAIN_3 + Digital gain value is 1.375. + 0x3 + + + RX_DIG_GAIN_4 + Digital gain value is 1.500. + 0x4 + + + RX_DIG_GAIN_5 + Digital gain value is 1.625. + 0x5 + + + RX_DIG_GAIN_6 + Digital gain value is 1.750. + 0x6 + + + RX_DIG_GAIN_7 + Digital gain value is 1.875. + 0x7 + + + + + RX_ACQ_FILT_LEN + Acquisition Filter Length + 20 + 1 + read-write + + + RX_ACQ_FILT_LEN_0 + Acquisition filter length is 24. + 0 + + + RX_ACQ_FILT_LEN_1 + Acquisition filter length is 16. + 0x1 + + + + + RX_ACQ_FILT_BYPASS + Acquisition Filter Bypass + 21 + 1 + read-write + + + RX_ACQ_FILT_BYPASS_0 + Acquisition filter is enabled + 0 + + + RX_ACQ_FILT_BYPASS_1 + Acquisition filter is bypassed + 0x1 + + + + + RX_SRC_EN + RX Sample Rate Converter Enable + 22 + 1 + read-write + + + RX_SRC_EN_0 + SRC is disabled. + 0 + + + RX_SRC_EN_1 + SRC is enabled. + 0x1 + + + + + RX_IQ_8B_OUT_MODE + RX 8-bit IQ Output Mode + 23 + 3 + read-write + + + RX_IQ_8B_OUT_MODE_0 + Disable 8-bit IQ output + 0 + + + RX_IQ_8B_OUT_MODE_1 + {I[10],I[9:3]}, {Q[10],Q[9:3]} + 0x1 + + + RX_IQ_8B_OUT_MODE_2 + {I[10],I[8:2]}, {Q[10],Q[8:2]} + 0x2 + + + RX_IQ_8B_OUT_MODE_3 + {I[10],I[7:1]}, {Q[10],Q[7:1]} + 0x3 + + + RX_IQ_8B_OUT_MODE_4 + Dynamic scaling + 0x4 + + + + + RX_FSK_ZB_SEL + PHY/Demodulator selection + 27 + 1 + read-write + + + RX_FSK_ZB_SEL_0 + 2.4GHz PHY is selected + 0 + + + RX_FSK_ZB_SEL_1 + 15.4 PHY is selected + 0x1 + + + + + CIC_CNTR_FREE_RUN_EN + CIC Dec Counter Free Run Enable + 29 + 1 + read-write + + + RX_AGC_EN + AGC Enable + 30 + 1 + read-write + + + RX_AGC_EN_0 + AGC is disabled + 0 + + + RX_AGC_EN_1 + AGC is enabled + 0x1 + + + + + DR_OVRD_IN_CTE + DATARATE_CONFIG_SEL Override In CTE + 31 + 1 + read-write + + + + + CTRL0_DRS + RXDIG Control 0 DRS + 0x4 + 32 + read-write + 0x20C0 + 0xFFFFFFFF + + + DIG_MIXER_FREQ + Digital Mixer Frequency + 2 + 9 + read-write + + + CIC_ORDER + CIC Order(Stage) Selection + 11 + 1 + read-write + + + CIC_ORDER_0 + 4-stage CIC + 0 + + + CIC_ORDER_1 + 3-stage CIC + 0x1 + + + + + CIC_RATE + CIC Decimation Rate + 12 + 3 + read-write + + + CIC_RATE_0 + Decimation Rate is 1. + 0 + + + CIC_RATE_1 + Decimation Rate is 2. + 0x1 + + + CIC_RATE_2 + Decimation Rate is 4. + 0x2 + + + CIC_RATE_3 + Decimation Rate is 8. + 0x3 + + + CIC_RATE_4 + Decimation Rate is 16. + 0x4 + + + CIC_RATE_5 + Decimation Rate is 32. + 0x5 + + + + + + + CTRL1 + RXDIG Control 1 + 0x8 + 32 + read-write + 0x180 + 0xFFFFFFFF + + + RX_SAMPLE_BUF_BYPASS + Bypass Sample Buffer + 0 + 1 + read-write + + + RX_SAMPLE_BUF_BYPASS_IN_CTE + Bypass Sample Buffer During CTE + 4 + 1 + read-write + + + RX_SAMPLE_BUF_AUTO_GATE + Sample Buffer Automatically Gate Off + 5 + 1 + read-write + + + DC_RESID_EN + DC_RESID Enable + 6 + 1 + read-write + + + DIS_WB_NORM_AA_FOUND + Disable WB-NORM when AA found + 7 + 1 + read-write + + + RX_NB_NORM_EN + Narrow-Band Normalizer Enable + 8 + 1 + read-write + + + RX_NB_NORM_EN_0 + Narrow-Band normalizer is disabled. + 0 + + + RX_NB_NORM_EN_1 + Narrow-Band normalizer is enabled. + 0x1 + + + + + RX_HIGH_RES_NORM_SEL + High Resolution Phase Source Select + 9 + 1 + read-write + + + RX_HIGH_RES_NORM_SEL_0 + From RX_NORM_NB + 0 + + + RX_HIGH_RES_NORM_SEL_1 + From RX_NORM_WB + 0x1 + + + + + RX_DEMOD_FILT_BYPASS + Demod Channel Filter Bypass + 10 + 1 + read-write + + + RX_DEMOD_FILT_BYPASS_0 + Demod channel filter is enabled. + 0 + + + RX_DEMOD_FILT_BYPASS_1 + Demod channel filter is bypassed. + 0x1 + + + + + RX_FRAC_CORR_OVRD + Fractional Correction Coefficient Override Value + 12 + 3 + read-write + + + RX_FRAC_CORR_OVRD_EN + Fractional Correction Coefficient Override Enable + 15 + 1 + read-write + + + RX_CFO_EST_OVRD + CFO Estimation Override Value + 16 + 10 + read-write + + + RX_CFO_EST_OVRD_EN + CFO Estimation Override Enable + 26 + 1 + read-write + + + RX_CFO_EST_OVRD_EN_0 + CFO override is enabled + 0 + + + RX_CFO_EST_OVRD_EN_1 + CFO override is disabled + 0x1 + + + + + RX_MIXER_IDX_OUT_MODE + RX_DIG Mixer Index Output Mode + 27 + 1 + read-write + + + RX_IQ_PH_AVG_WIN + RX IQ Phase Output Average Window Config + 28 + 3 + read-write + + + RX_IQ_PH_AVG_WIN_0 + Disable RX IQ and/or Phase output average function + 0 + + + RX_IQ_PH_AVG_WIN_1 + Average window size = 4 + 0x1 + + + RX_IQ_PH_AVG_WIN_2 + Average window size = 8 + 0x2 + + + RX_IQ_PH_AVG_WIN_3 + Average window size = 16 + 0x3 + + + RX_IQ_PH_AVG_WIN_4 + Average window size = 32 + 0x4 + + + RX_IQ_PH_AVG_WIN_5 + Average window size = 64 + 0x5 + + + RX_IQ_PH_AVG_WIN_6 + Average window size = 128 + 0x6 + + + RX_IQ_PH_AVG_WIN_7 + Average window size = 256 + 0x7 + + + + + RX_IQ_PH_OUTPUT_COND + RX IQ or Phase Output Conditioning + 31 + 1 + read-write + + + RX_IQ_PH_OUTPUT_COND_0 + Output IQ and/or Phase all-time + 0 + + + RX_IQ_PH_OUTPUT_COND_1 + Only output IQ and/or Phase during localization sample slot + 0x1 + + + + + + + DFT_CTRL + RXDIG DFT Control + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_RX_PH_OUT_SEL + DFT RXDIG Phase Output Selection + 8 + 2 + read-write + + + DFT_RX_PH_OUT_SEL_0 + Disable DFT phase output + 0 + + + DFT_RX_PH_OUT_SEL_1 + Sel wide-band phase output + 0x1 + + + DFT_RX_PH_OUT_SEL_2 + Sel narrow-band phase output + 0x2 + + + DFT_RX_PH_OUT_SEL_3 + Disable DFT phase output + 0x3 + + + + + DFT_RX_IQ_OUT_SEL + DFT I/Q Output Selection + 10 + 3 + read-write + + + DFT_RX_IQ_OUT_SEL_0 + Disabled + 0 + + + DFT_RX_IQ_OUT_SEL_1 + Select IF_MIXER + 0x1 + + + DFT_RX_IQ_OUT_SEL_2 + Select CIC + 0x2 + + + DFT_RX_IQ_OUT_SEL_3 + Select ACQ channel filter + 0x3 + + + DFT_RX_IQ_OUT_SEL_4 + Select SRC + 0x4 + + + DFT_RX_IQ_OUT_SEL_5 + Select CFO_MIXER + 0x5 + + + DFT_RX_IQ_OUT_SEL_6 + Select FRAC_CORR + 0x6 + + + DFT_RX_IQ_OUT_SEL_7 + Select DC_RESID + 0x7 + + + + + DFT_RSSI_MAG_OUT_SEL + DFT RSSI Magnitude Output Selection + 13 + 3 + read-write + + + DFT_RSSI_MAG_OUT_SEL_0 + Disabled + 0 + + + DFT_RSSI_MAG_OUT_SEL_1 + WB-RSSI fast magnitude + 0x1 + + + DFT_RSSI_MAG_OUT_SEL_2 + WB-RSSI slow magnitude + 0x2 + + + DFT_RSSI_MAG_OUT_SEL_3 + NB-RSSI mag IIR + 0x3 + + + DFT_RSSI_MAG_OUT_SEL_4 + NB-RSSI mag avg + 0x4 + + + DFT_RSSI_MAG_OUT_SEL_5 + NB-RSSI noise mag IIR + 0x5 + + + DFT_RSSI_MAG_OUT_SEL_6 + NB-RSSI noise mag avg + 0x6 + + + DFT_RSSI_MAG_OUT_SEL_7 + DFT_RX_IQ_OUT mag + 0x7 + + + + + DFT_RSSI_OUT_SEL + DFT RSSI Result Output Selection + 16 + 3 + read-write + + + DFT_RSSI_OUT_SEL_0 + Disable RSSI output + 0 + + + DFT_RSSI_OUT_SEL_1 + Wide-band RSSI_RAW output + 0x1 + + + DFT_RSSI_OUT_SEL_2 + Wide-band RSSI output + 0x2 + + + DFT_RSSI_OUT_SEL_3 + Narrow-band RSSI_RAW output + 0x3 + + + DFT_RSSI_OUT_SEL_4 + Narrow-band RSSI output + 0x4 + + + DFT_RSSI_OUT_SEL_5 + Narrow-band NOISE_RAW output + 0x5 + + + DFT_RSSI_OUT_SEL_6 + Narrow-band SNR output + 0x6 + + + DFT_RSSI_OUT_SEL_7 + Narrow-band LQI output + 0x7 + + + + + CGM_OVRD + CGM Override + 20 + 12 + read-write + + + CGM_OVRD_1 + RCCAL + 0x1 + + + CGM_OVRD_2 + DCOC + 0x2 + + + CGM_OVRD_4 + IF_MIXER + 0x4 + + + CGM_OVRD_8 + CIC + 0x8 + + + CGM_OVRD_16 + ACQ_CHF + 0x10 + + + CGM_OVRD_32 + SRC + 0x20 + + + CGM_OVRD_64 + SAMPLE_BUF and CFO_MIXER + 0x40 + + + CGM_OVRD_128 + DEMOD_CHF and FRAC_CORR + 0x80 + + + CGM_OVRD_256 + NB_NORM and HIGH_RES_NORM + 0x100 + + + CGM_OVRD_512 + AGC + 0x200 + + + CGM_OVRD_1024 + IQ_MISMATCH + 0x400 + + + CGM_OVRD_2048 + DIG_GAIN + 0x800 + + + + + + + RCCAL_CTRL0 + RCCAL Control 0 + 0x10 + 32 + read-write + 0x2A + 0xFFFFFFFF + + + CBPF_BW_CODE + CBPF BW_CODE + 0 + 3 + read-write + + + CBPF_SC_CODE + See detail in CBPF_BW_CODE description + 3 + 1 + read-write + + + CBPF_BW_CODE_DRS + When datarate_config_sel=1, will choose this value instead of CBPF_BW_CODE + 4 + 3 + read-write + + + CBPF_SC_CODE_DRS + When datarate_config_sel=1, will choose this value instead of CBPF_SC_CODE + 7 + 1 + read-write + + + CBPF_CCODE_OFFSET + CBPF_CCODE Offset + 8 + 5 + read-write + + + RCCAL_CODE_OFFSET + RCCAL_CODE Offset + 16 + 4 + read-write + + + RCCAL_SMPL_DLY + RCCAL Sample Delay + 20 + 2 + read-write + + + RCCAL_SMPL_DLY_0 + 2 cycles (default) + 0 + + + RCCAL_SMPL_DLY_1 + 1 cycle + 0x1 + + + RCCAL_SMPL_DLY_2 + 2 cycles + 0x2 + + + RCCAL_SMPL_DLY_3 + 3 cycles + 0x3 + + + + + RCCAL_CMPOUT_INV + RCCAL Comparator Output Invert + 22 + 1 + read-write + + + + + RCCAL_CTRL1 + RCCAL Control 1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CBPF_CCODE_OVRD + CBPF_CCODE Override Value + 0 + 7 + read-write + + + CBPF_CCODE_OVRD_EN + CBPF_CCODE Override Enable + 7 + 1 + read-write + + + RCCAL_CODE_OVRD + RCCAL_CODE Override Value + 8 + 5 + read-write + + + RCCAL_CODE_OVRD_EN + RCCAL_CODE Override Enable + 13 + 1 + read-write + + + RCCAL_SAMPLE_OVRD + RCCAL_SAMPLE Override Value + 16 + 1 + read-write + + + RCCAL_CHARGE_OVRD + RCCAL_CHARGE Override Value + 17 + 1 + read-write + + + RCCAL_DISCHARGE_OVRD + RCCAL_DISCHARGE Override Value + 18 + 1 + read-write + + + RCCAL_CTRL_OVRD_EN + RCCAL Control Signals Override Enable + 19 + 1 + read-write + + + + + RCCAL_RES + RCCAL Result + 0x18 + 32 + read-only + 0x4E10 + 0xFFFFFFFF + + + RCCAL_CODE + RCCAL_CODE + 0 + 5 + read-only + + + CBPF_CCODE + CBPF_CCODE + 8 + 7 + read-only + + + RCCAL_CMPOUT + RCCAL CMPOUT + 16 + 1 + read-only + + + + + DCOC_CTRL0 + DCOC Control 0 + 0x1C + 32 + read-write + 0x332F56 + 0xFFFFFFFF + + + DCOC_SFII + DCOC_SFII + 0 + 4 + read-write + + + DCOC_SFQQ + DCOC_SFQQ + 4 + 4 + read-write + + + DCOC_SFIIP + DCOC_SFIIP + 8 + 1 + read-write + + + DCOC_SFQQP + DCOC_SFQQP + 9 + 1 + read-write + + + DCOC_SFIQ + DCOC_SFIQ + 10 + 1 + read-write + + + DCOC_SFQI + DCOC_SFQI + 11 + 1 + read-write + + + DCOC_I_CAL_POL + DCOC_I_CAL_POL + 12 + 1 + read-write + + + DCOC_Q_CAL_POL + DCOC_Q_CAL_POL + 13 + 1 + read-write + + + DCOC_DAC_ORDER + DCOC_DAC_ORDER + 14 + 1 + read-write + + + DCOC_DAC_ORDER_0 + DCOC I DAC is calibrated first + 0 + + + DCOC_DAC_ORDER_1 + DCOC Q DAC is calibrated first + 0x1 + + + + + DCOC_PULSE_CAPCODE + no description available + 15 + 1 + read-write + + + DCOC_CBPF_STL_TIME + DCOC CBPF Settle Time + 16 + 4 + read-write + + + DCOC_SAR_STL_TIME + DCOC CBPF Settle Time + 20 + 4 + read-write + + + DCOC_CAL_USE_OFFSET + Apply dcoc_i/qcbpf_offset during DCOC calibration. + 24 + 1 + read-write + + + DCOC_CAL_USE_OFFSET_0 + Do not apply dcoc_i/qcbpf_offset during DCOC calibration + 0 + + + DCOC_CAL_USE_OFFSET_1 + Apply dcoc_i/qcbpf_offset during DCOC calibration + 0x1 + + + + + DCOC_AVG_WIN + DCOC Average Window Select + 25 + 1 + read-write + + + DCOC_AVG_WIN_0 + 4-sample + 0 + + + DCOC_AVG_WIN_1 + 8-sample + 0x1 + + + + + DCOC_DIG_CORR_EN + DCOC Digital Correction Enable + 26 + 1 + read-write + + + DCOC_DAC_OVRD_EN + DCOC_DAC_OVRD_EN + 27 + 1 + read-write + + + DCOC_ADC_OFFSET_OVRD_EN + DCOC_ADC_OFFSET_OVRD_EN + 28 + 1 + read-write + + + DCOC_CBPF_SHORT_OVRD + DCOC CBPF_SHORT Override Value + 29 + 1 + read-write + + + DCOC_CBPF_HIZ_OVRD + DCOC CBPF_HIZ Override Value + 30 + 1 + read-write + + + DCOC_CBPF_HIZ_SHORT_OVRD_EN + DCOC CBPF HIZ SHORT Override Enable + 31 + 1 + read-write + + + + + DCOC_CTRL0_DRS + DCOC Control 0 DRS + 0x20 + 32 + read-write + 0x356 + 0xFFFFFFFF + + + DCOC_SFII + DCOC_SFII + 0 + 4 + read-write + + + DCOC_SFQQ + DCOC_SFQQ + 4 + 4 + read-write + + + DCOC_SFIIP + DCOC_SFIIP + 8 + 1 + read-write + + + DCOC_SFQQP + DCOC_SFQQP + 9 + 1 + read-write + + + + + DCOC_CTRL1 + DCOC CONTROL 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_ILNA_OFFSET + DCOC_ILNA_OFFSET + 0 + 6 + read-write + + + DCOC_QLNA_OFFSET + DCOC_QLNA_OFFSET + 8 + 6 + read-write + + + DCOC_ICBPF_OFFSET + DCOC_ICBPF_OFFSET + 16 + 6 + read-write + + + DCOC_QCBPF_OFFSET + DCOC_QCBPF_OFFSET + 24 + 6 + read-write + + + + + DCOC_CTRL2 + DCOC CONTROL 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_DAC_OVRD_I + DCOC_DAC_OVRD_I + 0 + 6 + read-write + + + DCOC_DAC_OVRD_Q + DCOC_DAC_OVRD_Q + 8 + 6 + read-write + + + DCOC_ADC_OFFSET_OVRD_I + DCOC_ADC_OFFSET_OVRD_I + 16 + 7 + read-write + + + DCOC_ADC_OFFSET_OVRD_Q + DCOC_ADC_OFFSET_OVRD_Q + 24 + 7 + read-write + + + + + DCOC_STAT + DCOC Status + 0x2C + 32 + read-only + 0x2020 + 0xFFFFFFFF + + + CBPF_CODE_DCOC_I + CBPF_CODE_DCOC_I + 0 + 6 + read-only + + + CBPF_CODE_DCOC_Q + CBPF_CODE_DCOC_Q + 8 + 6 + read-only + + + DCOC_ADC_OFFSET_I + DCOC_ADC_OFFSET_I + 16 + 7 + read-only + + + DCOC_ADC_OFFSET_Q + DCOC_ADC_OFFSET_Q + 24 + 7 + read-only + + + + + IQMC_CTRL0 + IQ Mismatch Control 0 + 0x30 + 32 + read-write + 0x4008000 + 0xFFFFFFFF + + + IQMC_CAL_EN + IQ Mismatch Cal Enable + 0 + 1 + read-write + + + IQMC_CAL_FREQ_SEL + IQMC_CAL_FREQ_SEL + 1 + 1 + read-write + + + IQMC_CAL_FREQ_SEL_0 + Reference clk divided by 2 + 0 + + + IQMC_CAL_FREQ_SEL_1 + Reference clk divided by 4 + 0x1 + + + + + IQMC_NUM_ITER + IQ Mismatch Cal Num Iter + 8 + 8 + read-write + + + IQMC_DC_GAIN_ADJ + Not currently used. + 16 + 11 + read-write + + + + + IQMC_CTRL1 + IQ Mismatch Control 1 + 0x34 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + IQMC_GAIN_ADJ + IQ Mismatch Correction Gain Coeff + 0 + 11 + read-write + + + IQMC_PHASE_ADJ + IQ Mismatch Correction Phase Coeff + 16 + 12 + read-write + + + + + ACQ_FILT_0_3 + Acquisition Filter Coeffs 0~3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + H0 + Acquisition Filter Coefficient 0 + 0 + 6 + read-write + + + H1 + Acquisition Filter Coefficient 1 + 8 + 6 + read-write + + + H2 + Acquisition Filter Coefficient 2 + 16 + 7 + read-write + + + H3 + Acquisition Filter Coefficient 3 + 24 + 7 + read-write + + + + + ACQ_FILT_4_7 + Acquisition Filter Coeffs 4~7 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + H4 + Acquisition Filter Coefficient 4 + 0 + 7 + read-write + + + H5 + Acquisition Filter Coefficient 5 + 8 + 7 + read-write + + + H6 + Acquisition Filter Coefficient 6 + 16 + 8 + read-write + + + H7 + Acquisition Filter Coefficient 7 + 24 + 8 + read-write + + + + + ACQ_FILT_8_9 + Acquisition Filter Coeffs 8~9 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + H8 + Acquisition Filter Coefficient 8 + 0 + 9 + read-write + + + H9 + Acquisition Filter Coefficient 9 + 16 + 9 + read-write + + + + + ACQ_FILT_10_11 + Acquisition Filter Coeffs 10~11 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + Acquisition Filter Coefficient 10 + 0 + 10 + read-write + + + H11 + Acquisition Filter Coefficient 11 + 16 + 10 + read-write + + + + + DEMOD_FILT_0_1 + Demod Filter Coeffs 0~1 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + H0 + Demod Channel Filter Coefficient 0 + 0 + 9 + read-write + + + H1 + Demod Channel Filter Coefficient 1 + 16 + 9 + read-write + + + + + DEMOD_FILT_2_4 + Demod Filter Coeffs 2~4 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + H2 + Demod Channel Filter Coefficient 2 + 0 + 10 + read-write + + + H3 + Demod Channel Filter Coefficient 3 + 10 + 10 + read-write + + + H4 + Demod Channel Filter Coefficient 4 + 20 + 10 + read-write + + + + + ACQ_FILT_0_3_DRS + Acquisition Filter Coeffs 0~3 DRS + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + H0 + Acquisition Filter Coefficient 0 + 0 + 6 + read-write + + + H1 + Acquisition Filter Coefficient 1 + 8 + 6 + read-write + + + H2 + Acquisition Filter Coefficient 2 + 16 + 7 + read-write + + + H3 + Acquisition Filter Coefficient 3 + 24 + 7 + read-write + + + + + ACQ_FILT_4_7_DRS + Acquisition Filter Coeffs 4~7 DRS + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + H4 + Acquisition Filter Coefficient 4 + 0 + 7 + read-write + + + H5 + Acquisition Filter Coefficient 5 + 8 + 7 + read-write + + + H6 + Acquisition Filter Coefficient 6 + 16 + 8 + read-write + + + H7 + Acquisition Filter Coefficient 7 + 24 + 8 + read-write + + + + + ACQ_FILT_8_9_DRS + Acquisition Filter Coeffs 8~9 DRS + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + H8 + Acquisition Filter Coefficient 8 + 0 + 9 + read-write + + + H9 + Acquisition Filter Coefficient 9 + 16 + 9 + read-write + + + + + ACQ_FILT_10_11_DRS + Acquisition Filter Coeffs 10~11 DRS + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + H10 + Acquisition Filter Coefficient 10 + 0 + 10 + read-write + + + H11 + Acquisition Filter Coefficient 11 + 16 + 10 + read-write + + + + + DEMOD_FILT_0_1_DRS + Demod Filter Coeffs 0~1 DRS + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + H0 + Demod Channel Filter Coefficient 0 + 0 + 9 + read-write + + + H1 + Demod Channel Filter Coefficient 1 + 16 + 9 + read-write + + + + + DEMOD_FILT_2_4_DRS + Demod Filter Coeffs 2~4 DRS + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + H2 + Demod Channel Filter Coefficient 2 + 0 + 10 + read-write + + + H3 + Demod Channel Filter Coefficient 3 + 10 + 10 + read-write + + + H4 + Demod Channel Filter Coefficient 4 + 20 + 10 + read-write + + + + + RSSI_GLOBAL_CTRL + RSSI Global Control + 0x68 + 32 + read-write + 0x310 + 0xFFFFFFFF + + + NB_RSSI_INPUT_SEL + NB RSSI Input Select + 0 + 2 + read-write + + + NB_RSSI_INPUT_SEL_0 + ACQ_CHF output I/Q + 0 + + + NB_RSSI_INPUT_SEL_1 + SRC output I/Q + 0x1 + + + NB_RSSI_INPUT_SEL_2 + DEMOD_CHF output I/Q + 0x2 + + + + + NB_RSSI_AA_MATCH_OVRD + NB RSSI PHY Trigger Override + 2 + 1 + read-write + + + NB_RSSI_AA_MATCH_OVRD_EN + NB RSSI PHY Trigger Override Enable + 3 + 1 + read-write + + + NB_RSSI_PA_AA_MATCH_SEL + NB RSSI PHY Trigger Select + 4 + 1 + read-write + + + NB_RSSI_PA_AA_MATCH_SEL_0 + NB-RSSI starts work when PHY_PD_FOUND asserted + 0 + + + NB_RSSI_PA_AA_MATCH_SEL_1 + NB-RSSI starts work when PHY_AA_MATCH asserted + 0x1 + + + + + NB_CCA1_ED_EN + NB RSSI CCA1 ED Enable + 5 + 1 + read-write + + + NB_CCA1_ED_EN_0 + NB-RSSI CCA1/ED is disabled + 0 + + + NB_CCA1_ED_EN_1 + NB-RSSI CCA1/ED is enabled + 0x1 + + + + + NB_CONT_MEAS_OVRD + NB RSSI Onetime Measure Override + 6 + 1 + read-write + + + NB_CONT_MEAS_OVRD_EN + NB RSSI One-time Measure Override Enable + 7 + 1 + read-write + + + NB_SNR_LQI_ENABLE + NB RSSI SNR LQI Enable + 8 + 1 + read-write + + + NB_SNR_LQI_ENABLE_0 + NB-RSSI SNR/LQI calculation is disabled + 0 + + + NB_SNR_LQI_ENABLE_1 + NB-RSSI SNR/LQI calculation is enabled + 0x1 + + + + + CCA1_ED_FROM_NB + CCA1/ED Result Selection + 9 + 1 + read-write + + + CCA1_ED_FROM_NB_0 + WB-RSSI's CCA1/ED result is selected + 0 + + + CCA1_ED_FROM_NB_1 + NB-RSSI's CCA1/ED result is selected + 0x1 + + + + + NB_RSSI_EN + NB RSSI Enable + 15 + 1 + read-write + + + NB_RSSI_EN_0 + NB-RSSI is disabled + 0 + + + NB_RSSI_EN_1 + NB-RSSI is enabled + 0x1 + + + + + WB_RSSI_INPUT_SEL + WB RSSI Input Select + 16 + 1 + read-write + + + WB_RSSI_INPUT_SEL_0 + DCOC output I/Q + 0 + + + WB_RSSI_INPUT_SEL_1 + CIC output I/Q + 0x1 + + + + + WB_CCA1_ED_EN + WB RSSI CCA1 ED Enable + 20 + 1 + read-write + + + WB_CCA1_ED_EN_0 + WB-RSSI CCA1/ED disabled + 0 + + + WB_CCA1_ED_EN_1 + WB-RSSI CCA1/ED enabled + 0x1 + + + + + WB_CONT_MEAS_OVRD + WB RSSI Continuous Measurment Override Value + 21 + 1 + read-write + + + WB_CONT_MEAS_OVRD_EN + WB RSSI Continuous Measurment Override Enable + 22 + 1 + read-write + + + WB_RSSI_EN + WB RSSI Enable + 31 + 1 + read-write + + + WB_RSSI_EN_0 + WB-RSSI is disabled + 0 + + + WB_RSSI_EN_1 + WB-RSSI is enabled + 0x1 + + + + + + + WB_RSSI_CTRL + Wide-Band RSSI Control + 0x6C + 32 + read-write + 0x223222 + 0xFFFFFFFF + + + RSSI_N_WINDOW_WB + WB RSSI N Window Averager Factor + 0 + 3 + read-write + + + RSSI_M_WINDOW_WB + WB RSSI M Window Averager Factor + 4 + 3 + read-write + + + RSSI_F_WINDOW_WB + WB RSSI F Window Averager Factor + 8 + 3 + read-write + + + RSSI_DB_EN_WB + WB RSSI dB Calculate Enable + 12 + 1 + read-write + + + KEEP_RSSI_RESULT_WB + When enabled, the WB-RSSI results will keep until next update/refresh, or the WB-RSSI results will be cleared when rssi_init asserts + 13 + 1 + read-write + + + RSSI_N_WINDOW_WB_DRS + no description available + 16 + 3 + read-write + + + RSSI_F_WINDOW_WB_DRS + no description available + 20 + 3 + read-write + + + RSSI_ADJ_WB + WB RSSI Adjust Value + 24 + 8 + read-write + + + + + WB_RSSI_RES0 + Wide-Band RSSI Result 0 + 0x70 + 32 + read-write + 0x800100 + 0xFFFFFFFF + + + RSSI_WB + WB RSSI Result + 0 + 9 + read-only + + + RSSI_RDY_WB + This bit set when RSSI_WB value ready to read(or updated) and cleared by rx_init or write "1" to this field(W1C) + 15 + 1 + read-write + + + RSSI_RAW_WB + WB Raw RSSI Result + 16 + 8 + read-only + + + + + WB_RSSI_RES1 + Wide-Band RSSI Result 1 + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + ED_WB + WB RSSI ED Result + 0 + 8 + read-only + + + CCA1_STATE_WB + WB RSSI CCA1 State + 30 + 1 + read-only + + + MEAS_COMPLETE_WB + WB RSSI Measure Complete + 31 + 1 + read-only + + + + + WB_RSSI_DFT + Wide-Band RSSI DFT Result + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLOW_MAG + WB RSSI Slow Magnitude Value + 0 + 10 + read-only + + + FAST_MAG + WB RSSI Fast Magnitude Value + 10 + 10 + read-only + + + + + NB_RSSI_CTRL0 + Narrow-Band RSSI Control 0 + 0x7C + 32 + read-write + 0x400022 + 0xFFFFFFFF + + + RSSI_N_WINDOW_NB + NB RSSI N Window Averager Factor + 0 + 4 + read-write + + + RSSI_M_WINDOW_NB + NB RSSI M Window Averager Factor + 4 + 4 + read-write + + + RSSI_IIR_WAIT_NB + NB RSSI IIR Filter Initial Wait Time + 8 + 3 + read-write + + + RSSI_IIR_WT_NB + NB RSSI IIR Filter Factor + 12 + 3 + read-write + + + SNR_ADJ_NB + NB RSSI SNR Adjust Value + 16 + 6 + read-write + + + KEEP_RSSI_RESULT_NB + When enabled, the NB-RSSI results will keep until next update/refresh, or the NB-RSSI results will be cleared when rx_init or rssi_init asserts + 22 + 1 + read-write + + + RSSI_ADJ_NB + NB RSSI Adjust Value + 24 + 8 + read-write + + + + + NB_RSSI_CTRL1 + Narrow-Band RSSI Control 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + LQI_RSSI_WEIGHT + RSSI Weight For LQI Calulation + 16 + 3 + read-write + + + LQI_SNR_WEIGHT + SNR Weight For LQI Calulation + 20 + 4 + read-write + + + LQI_RSSI_SENS_ADJ + LQI Sensitivity Adjust Value + 24 + 4 + read-write + + + LQI_BIAS + LQI Bias Value + 28 + 4 + read-write + + + + + NB_RSSI_RES0 + Narrow-Band RSSI Result 0 + 0x84 + 32 + read-write + 0x80800100 + 0xFFFFFFFF + + + RSSI_NB + NB RSSI Result + 0 + 9 + read-only + + + RSSI_RDY_NB + This bit set when RSSI_NB/SNR_NB/LQI_NB/ED_NB value ready to read(or updated) and cleared by rx_init or write "1" to this field(W1C) + 15 + 1 + read-write + + + RSSI_RAW_NB + Raw NB RSSI Result + 16 + 8 + read-only + + + NOISE_RSSI_RAW_NB + Raw Noise Result + 24 + 8 + read-only + + + + + NB_RSSI_RES1 + Narrow-Band RSSI Result 1 + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + ED_NB + NB RSSI ED Result + 0 + 8 + read-only + + + LQI_NB + NB RSSI LQI Result + 8 + 8 + read-only + + + SNR_NB + NB RSSI SNR Result + 16 + 6 + read-only + + + CCA1_STATE_NB + NB RSSI CCA1 State + 30 + 1 + read-only + + + MEAS_COMPLETE_NB + NB RSSI Measure Complete + 31 + 1 + read-only + + + + + NB_RSSI_DFT + Narrow-Band RSSI DFT Result + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + AVG_NOISE_MAG_NB + NB RSSI Averaged Noise Magnitude Value + 0 + 12 + read-only + + + AVG_MAG_NB + NB RSSI Averaged Magnitude Value + 16 + 12 + read-only + + + + + AGC_CTRL + AGC Control + 0x90 + 32 + read-write + 0x805CCD10 + 0xFFFFFFFF + + + AGC_UNHOLD_FEAT_EN + AGC Unhold Enalbe + 0 + 2 + read-write + + + AGC_HOLD_EN + AGC Hold Mode Enable + 2 + 2 + read-write + + + AGC_HOLD_EN_0 + Disable AGC hold mode + 0 + + + AGC_HOLD_EN_1 + AGC hold when preamble found + 0x1 + + + AGC_HOLD_EN_2 + AGC hold when AGC hold timeout matched + 0x2 + + + AGC_HOLD_EN_3 + AGC hold when preamble found or hold timeout matched + 0x3 + + + + + AGC_DELTA_SLOW_STEP + AGC Delta Slow Mode Gain Step Up Value + 4 + 3 + read-write + + + AGC_DELTA_SLOW_EN + AGC Delta Slow Magitude Mode Enable + 7 + 1 + read-write + + + AGC_DELTA_SLOW_EN_0 + Disable AGC delta slow magnitude mode + 0 + + + AGC_DELTA_SLOW_EN_1 + Enable AGC delta slow magnitude mode + 0x1 + + + + + AGC_SLOW_EN + AGC Slow Magitude Mode Enable + 8 + 1 + read-write + + + AGC_SLOW_EN_0 + Disable AGC slow magnitude mode + 0 + + + AGC_SLOW_EN_1 + Enable AGC slow magnitude mode + 0x1 + + + + + AGC_FAST_STEP_UP_EN + AGC Fast Magitude Mode Step Up Enable + 9 + 1 + read-write + + + AGC_FAST_STEP_UP_EN_0 + Fast magnitude mode can only make AGC gain index step down + 0 + + + AGC_FAST_STEP_UP_EN_1 + Fast magnitude mode can make AGC gain index step down or step up + 0x1 + + + + + AGC_FAST_EN + AGC Fast Magitude Mode Enable + 10 + 1 + read-write + + + AGC_FAST_EN_0 + Disable fast magnitude mode + 0 + + + AGC_FAST_EN_1 + Enable fast magnitude mode + 0x1 + + + + + AGC_WBD_STEP2_SZ + AGC WBD Step2 Gain Decreas Value + 11 + 3 + read-write + + + AGC_WBD_STEP1_SZ + AGC WBD Step1 Gain Decreas Value + 14 + 3 + read-write + + + AGC_WBD_THR2 + AGC WBD Step2 threshold + 17 + 4 + read-write + + + AGC_WBD_THR1 + AGC WBD Step1 threshold + 21 + 4 + read-write + + + AGC_WBD_THR1_0 + 49.31 + 0 + + + AGC_WBD_THR1_1 + 67.56 + 0x1 + + + AGC_WBD_THR1_2 + 90.98 + 0x2 + + + AGC_WBD_THR1_3 + 117.42 + 0x3 + + + AGC_WBD_THR1_4 + 150.66 + 0x4 + + + AGC_WBD_THR1_5 + 180.98 + 0x5 + + + AGC_WBD_THR1_6 + 211.87 + 0x6 + + + AGC_WBD_THR1_7 + 245.2 + 0x7 + + + AGC_WBD_THR1_8 + 288.31 + 0x8 + + + AGC_WBD_THR1_9 + 336.02 + 0x9 + + + AGC_WBD_THR1_10 + 394.34 + 0xA + + + AGC_WBD_THR1_11 + 462.71 + 0xB + + + AGC_WBD_THR1_12 + 548.04 + 0xC + + + AGC_WBD_THR1_13 + 650.13 + 0xD + + + AGC_WBD_THR1_14 + 771.65 + 0xE + + + AGC_WBD_THR1_15 + 918.12 + 0xF + + + + + AGC_WBD_STEP2_DUAL_CLIP_EN + AGC WBD Step2 Dual Clip Enable + 25 + 1 + read-write + + + AGC_WBD_STEP1_DUAL_CLIP_EN + AGC WBD Step1 Dual Clip Enable + 26 + 1 + read-write + + + AGC_WBD_GAIN_LIMIT_EN + AGC WBD Gain Limit + 27 + 1 + read-write + + + AGC_WBD_AUTO_DIS_CFG + AGC WBD Auto Disable + 28 + 2 + read-write + + + AGC_WBD_EN + AGC WBD Enable + 30 + 2 + read-write + + + AGC_WBD_EN_0 + AGC WBD is disabled + 0 + + + AGC_WBD_EN_1 + AGC WBD step1 is enabled + 0x1 + + + AGC_WBD_EN_2 + AGC WBD step1 and step2 is enabled + 0x2 + + + + + + + AGC_CTRL_STAT + AGC Control Status + 0x94 + 32 + read-write + 0x17E802C + 0xFFFFFFFF + + + AGC_MAX_IDX + AGC Max Gain Index + 0 + 2 + read-write + + + AGC_INIT_IDX + AGC Initial Gain Index + 2 + 4 + read-write + + + AGC_PHY_HOLD_TRIG_SEL + AGC PHY Hold Trigger Select + 6 + 1 + read-write + + + AGC_PHY_HOLD_TRIG_SEL_0 + PHY_AGC_HOLD_TRIG is select as AGC hold trig. + 0 + + + AGC_PHY_HOLD_TRIG_SEL_1 + PHY_AGC_FREEZE_TRIG is select as AGC hold trig. + 0x1 + + + + + AGC_PHY_FREEZE_TRIG_SEL + AGC PHY Freeze Trigger Select + 7 + 1 + read-write + + + AGC_PHY_FREEZE_TRIG_SEL_0 + PHY_AGC_FREEZE_TRIG is select as AGC freeze trig. + 0 + + + AGC_PHY_FREEZE_TRIG_SEL_1 + PHY_AGC_HOLD_TRIG is select as AGC freeze trig. + 0x1 + + + + + AGC_CALC_MAG_IN_FRZ + AGC Calucate Magnitude In Freeze Mode + 8 + 1 + read-write + + + AGC_UNFREEZE_FEAT_EN + AGC Unfreeze Feature Enable + 9 + 1 + read-write + + + AGC_UNFREEZE_FEAT_EN_0 + AGC unfreeze function is disabled + 0 + + + AGC_UNFREEZE_FEAT_EN_1 + AGC will exit FREEZE mode when AGC_UNFREEZE_TMEOUT matched and aa_found not be asserted + 0x1 + + + + + AGC_FREEZE_EN + AGC Freeze Mode Enable + 10 + 2 + read-write + + + AGC_FREEZE_EN_0 + Disable AGC freeze mode + 0 + + + AGC_FREEZE_EN_1 + AGC freeze when AA/SFD matched + 0x1 + + + AGC_FREEZE_EN_2 + AGC freeze when AGC freeze timeout matched + 0x2 + + + AGC_FREEZE_EN_3 + AGC freeze when AA/SFD matched or freeze timeout matched + 0x3 + + + + + AGC_GAIN_IDX_STORE + Enable and config AGC gain index stroe function + 12 + 2 + read-write + + + AGC_GAIN_IDX_STORE_0 + AGC gain index stroe function is disabled + 0 + + + AGC_GAIN_IDX_STORE_1 + Store AGC gain index when AGC enter into HOLD mode + 0x1 + + + AGC_GAIN_IDX_STORE_2 + Store AGC gain index when AGC enter into FREEZE mode + 0x2 + + + AGC_GAIN_IDX_STORE_3 + Store AGC gain index when AA matched + 0x3 + + + + + AGC_SOFT_RST_GAIN_SEL + PHY AGC Soft Reset Gain Sel + 14 + 1 + read-write + + + AGC_SOFT_RST_GAIN_SEL_0 + AGC keep current gain index when PHY AGC soft reset trigged, + 0 + + + AGC_SOFT_RST_GAIN_SEL_1 + AGC return to AGC_INIT_IDX when PHY AGC soft reset trigged, + 0x1 + + + + + AGC_SOFT_RST_SRC_SEL + PHY AGC Soft Reset Sel + 15 + 2 + read-write + + + AGC_SOFT_RST_SRC_SEL_0 + Disable PHY AGC soft reset function + 0 + + + AGC_SOFT_RST_SRC_SEL_1 + Use posedge phy_soft_rst to reset AGC + 0x1 + + + AGC_SOFT_RST_SRC_SEL_2 + Use negedge phy_soft_rst to reset AGC + 0x2 + + + AGC_SOFT_RST_SRC_SEL_3 + Use negedge phy_agc_freeze_trig to reset AGC + 0x3 + + + + + AGC_PREV_GAIN_IDX + AGC Previous Gain Index + 17 + 4 + read-only + + + AGC_GAIN_IDX + AGC Gain Index + 21 + 4 + read-only + + + AGC_GAIN_CHANGE + AGC Gain Change + 25 + 1 + read-only + + + AGC_GAIN_CHANGE_STATUS + AGC Gain Change Status + 26 + 3 + read-only + + + AGC_GAIN_CHANGE_STATUS_0 + No gain change + 0 + + + AGC_GAIN_CHANGE_STATUS_1 + Gain decreased by WBD step1 + 0x1 + + + AGC_GAIN_CHANGE_STATUS_2 + Gain decreased by WBD step2 + 0x2 + + + AGC_GAIN_CHANGE_STATUS_3 + Gain decreased by fast mode + 0x3 + + + AGC_GAIN_CHANGE_STATUS_4 + Gain increased by fast mode + 0x4 + + + AGC_GAIN_CHANGE_STATUS_5 + Gain decreased by slow mode + 0x5 + + + AGC_GAIN_CHANGE_STATUS_6 + Gain increased by slow mode + 0x6 + + + AGC_GAIN_CHANGE_STATUS_7 + Gain increased by delta slow mode + 0x7 + + + + + AGC_STATUS + AGC FSM Status + 29 + 3 + read-only + + + AGC_STATUS_0 + AGC_IDLE + 0 + + + AGC_STATUS_1 + AGC_WB_ONLY + 0x1 + + + AGC_STATUS_2 + AGC_WB_MAG + 0x2 + + + AGC_STATUS_3 + AGC_WB_DEBOUNCE + 0x3 + + + AGC_STATUS_4 + AGC_MAG_ONLY + 0x4 + + + AGC_STATUS_5 + AGC_HOLD + 0x5 + + + AGC_STATUS_6 + AGC_FREEZE + 0x6 + + + AGC_STATUS_7 + AGC_WAIT_GAIN_SETTLE + 0x7 + + + + + + + AGC_TIMING0 + AGC Timing Control 0 + 0x98 + 32 + read-write + 0x8104398 + 0xFFFFFFFF + + + AGC_DELTA_SLOW_WAIT + AGC Delta Slow Mode Timing + 0 + 2 + read-write + + + AGC_WBD_STEP2_TIMEOUT + AGC WBD Step2 Timeout + 2 + 5 + read-write + + + AGC_WBD_STEP1_TIMEOUT + AGC WBD Timeout + 7 + 3 + read-write + + + AGC_GAIN_STEP_WAIT + AGC Gain Change Wait Time + 10 + 6 + read-write + + + AGC_MAG_INIT_WAIT + AGC Magnitude Mode Initial Wait Time + 16 + 7 + read-write + + + AGC_WBD_INIT_WAIT + AGC WBD Mode Initial Wait Time + 24 + 7 + read-write + + + + + AGC_TIMING1 + AGC Timing Control 1 + 0x9C + 32 + read-write + 0x1902440A + 0xFFFFFFFF + + + AGC_FREEZE_TIMEOUT + AGC FREEZE Mode Wait Time + 0 + 7 + read-write + + + AGC_HOLD_TIMEOUT + AGC HOLD Mode Wait Time + 7 + 7 + read-write + + + AGC_WBD_STEP2_DUAL_CLIP_WAIT + AGC WBD step2 Debounce Wait Time + 14 + 3 + read-write + + + AGC_WBD_STEP1_DUAL_CLIP_WAIT + AGC WBD step1 Debounce Wait Time + 17 + 3 + read-write + + + AGC_WBD_STEP2_WAIT + AGC Gain Change Wait For WBD step2 + 20 + 6 + read-write + + + AGC_WBD_DUAL_CLIP_TIMEOUT + Indicate the max duration, count by reference clk, for WBD debounce + 26 + 4 + read-write + + + + + AGC_TIMING2 + AGC Timing Control 2 + 0xA0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + AGC_UNFREEZE_FEAT_TIMEOUT + AGC Unfreeze Feature Timeout + 0 + 11 + read-write + + + AGC_UNHOLD_FEAT_TIMEOUT + AGC Unhold Feature Timeout + 11 + 10 + read-write + + + AGC_UNHOLD_GAIN_CHG + AGC Gain Index Change When UNHOLD + 29 + 1 + read-write + + + AGC_UNHOLD_MAG_CNT + AGC Unhold Magnitude Count Selection + 30 + 1 + read-write + + + AGC_UNHOLD_MAG_SRC + AGC Magnitude Unhold Feature Source Selection + 31 + 1 + read-write + + + AGC_UNHOLD_MAG_SRC_0 + fast_mag + 0 + + + AGC_UNHOLD_MAG_SRC_1 + slow_mag + 0x1 + + + + + + + AGC_TIMING0_DRS + AGC Timing Control 0 DRS + 0xA4 + 32 + read-write + 0x4000 + 0xFFFFFFFF + + + AGC_GAIN_STEP_WAIT + AGC Gain Change Wait Time + 10 + 6 + read-write + + + AGC_WBD_EN_DRS + DRS version of AGC_CTRL[AGC_WBD_EN] + 30 + 2 + read-write + + + + + AGC_TIMING1_DRS + AGC Timing Control 1 DRS + 0xA8 + 32 + read-write + 0x40A + 0xFFFFFFFF + + + AGC_FREEZE_TIMEOUT + AGC FREEZE Mode Wait Time + 0 + 7 + read-write + + + AGC_HOLD_TIMEOUT + AGC HOLD Mode Wait Time + 7 + 7 + read-write + + + + + AGC_TIMING2_DRS + AGC Timing Control 2 DRS + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + AGC_UNFREEZE_FEAT_TIMEOUT + AGC Unfreeze Feature Timeout + 0 + 11 + read-write + + + AGC_UNHOLD_FEAT_TIMEOUT + AGC Unhold Feature Timeout + 11 + 10 + read-write + + + + + AGC_IDX11_GAIN_CFG + AGC IDX11 Gain Config + 0xB0 + 32 + read-write + 0x7E07 + 0xFFFFFFFF + + + CBPF_GAIN_11 + CBPF_GAIN_11 + 0 + 1 + read-write + + + CBPF_GAIN_11_0 + -6 dB + 0 + + + CBPF_GAIN_11_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_11 + LNA_RTRIM_11 + 1 + 3 + read-write + + + LNA_ATTN_11 + LNA_ATTN_11 + 4 + 2 + read-write + + + LNA_HATTN_11 + LNA_HATTN_11 + 6 + 1 + read-write + + + LNA_LGAIN_11 + LNA_LGAIN_11 + 7 + 2 + read-write + + + LNA_HGAIN_11 + LNA_HGAIN_11 + 9 + 6 + read-write + + + ANT_EN_RLOAD_11 + ANT_EN_RLOAD_11 + 15 + 1 + read-write + + + MAG_THR_HI_11_DRS_OFS + Mag Thresh High DRS for AGC Gain Index 11 + 16 + 8 + read-write + + + MAG_THR_11_DRS_OFS + Mag Thresh High DRS for AGC Gain Index 11 + 24 + 8 + read-write + + + + + AGC_IDX10_GAIN_CFG + AGC IDX10 Gain Config + 0xB4 + 32 + read-write + 0x2E07 + 0xFFFFFFFF + + + CBPF_GAIN_10 + CBPF_GAIN_10 + 0 + 1 + read-write + + + CBPF_GAIN_10_0 + -6 dB + 0 + + + CBPF_GAIN_10_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_10 + LNA_RTRIM_10 + 1 + 3 + read-write + + + LNA_ATTN_10 + LNA_ATTN_10 + 4 + 2 + read-write + + + LNA_HATTN_10 + LNA_HATTN_10 + 6 + 1 + read-write + + + LNA_LGAIN_10 + LNA_LGAIN_10 + 7 + 2 + read-write + + + LNA_HGAIN_10 + LNA_HGAIN_10 + 9 + 6 + read-write + + + ANT_EN_RLOAD_10 + ANT_EN_RLOAD_10 + 15 + 1 + read-write + + + MAG_THR_HI_10_DRS_OFS + Magnitude threshold high offset for AGC gain index 10 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_10_DRS_OFS + Magnitude threshold offset for AGC gain index 10 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX9_GAIN_CFG + AGC IDX9 Gain Config + 0xB8 + 32 + read-write + 0x1207 + 0xFFFFFFFF + + + CBPF_GAIN_9 + CBPF_GAIN_9 + 0 + 1 + read-write + + + CBPF_GAIN_9_0 + -6 dB + 0 + + + CBPF_GAIN_9_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_9 + LNA_RTRIM_9 + 1 + 3 + read-write + + + LNA_ATTN_9 + LNA_ATTN_9 + 4 + 2 + read-write + + + LNA_HATTN_9 + LNA_HATTN_9 + 6 + 1 + read-write + + + LNA_LGAIN_9 + LNA_LGAIN_9 + 7 + 2 + read-write + + + LNA_HGAIN_9 + LNA_HGAIN_9 + 9 + 6 + read-write + + + ANT_EN_RLOAD_9 + ANT_EN_RLOAD_9 + 15 + 1 + read-write + + + MAG_THR_HI_9_DRS_OFS + Magnitude threshold high offset for AGC gain index 9 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_9_DRS_OFS + Magnitude threshold offset for AGC gain index 9 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX8_GAIN_CFG + AGC IDX8 Gain Config + 0xBC + 32 + read-write + 0x607 + 0xFFFFFFFF + + + CBPF_GAIN_8 + CBPF_GAIN_8 + 0 + 1 + read-write + + + CBPF_GAIN_8_0 + -6 dB + 0 + + + CBPF_GAIN_8_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_8 + LNA_RTRIM_8 + 1 + 3 + read-write + + + LNA_ATTN_8 + LNA_ATTN_8 + 4 + 2 + read-write + + + LNA_HATTN_8 + LNA_HATTN_8 + 6 + 1 + read-write + + + LNA_LGAIN_8 + LNA_LGAIN_8 + 7 + 2 + read-write + + + LNA_HGAIN_8 + LNA_HGAIN_8 + 9 + 6 + read-write + + + ANT_EN_RLOAD_8 + ANT_EN_RLOAD_8 + 15 + 1 + read-write + + + MAG_THR_HI_8_DRS_OFS + Magnitude threshold high offset for AGC gain index 8 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_8_DRS_OFS + Magnitude threshold offset for AGC gain index 8 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX7_GAIN_CFG + AGC IDX7 Gain Config + 0xC0 + 32 + read-write + 0x207 + 0xFFFFFFFF + + + CBPF_GAIN_7 + CBPF_GAIN_7 + 0 + 1 + read-write + + + CBPF_GAIN_7_0 + -6 dB + 0 + + + CBPF_GAIN_7_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_7 + LNA_RTRIM_7 + 1 + 3 + read-write + + + LNA_ATTN_7 + LNA_ATTN_7 + 4 + 2 + read-write + + + LNA_HATTN_7 + LNA_HATTN_7 + 6 + 1 + read-write + + + LNA_LGAIN_7 + LNA_LGAIN_7 + 7 + 2 + read-write + + + LNA_HGAIN_7 + LNA_HGAIN_7 + 9 + 6 + read-write + + + ANT_EN_RLOAD_7 + ANT_EN_RLOAD_7 + 15 + 1 + read-write + + + MAG_THR_HI_7_DRS_OFS + Magnitude threshold high offset for AGC gain index 7 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_7_DRS_OFS + Magnitude threshold offset for AGC gain index 7 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX6_GAIN_CFG + AGC IDX6 Gain Config + 0xC4 + 32 + read-write + 0x187 + 0xFFFFFFFF + + + CBPF_GAIN_6 + CBPF_GAIN_6 + 0 + 1 + read-write + + + CBPF_GAIN_6_0 + -6 dB + 0 + + + CBPF_GAIN_6_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_6 + LNA_RTRIM_6 + 1 + 3 + read-write + + + LNA_ATTN_6 + LNA_ATTN_6 + 4 + 2 + read-write + + + LNA_HATTN_6 + LNA_HATTN_6 + 6 + 1 + read-write + + + LNA_LGAIN_6 + LNA_LGAIN_6 + 7 + 2 + read-write + + + LNA_HGAIN_6 + LNA_HGAIN_6 + 9 + 6 + read-write + + + ANT_EN_RLOAD_6 + ANT_EN_RLOAD_6 + 15 + 1 + read-write + + + MAG_THR_HI_6_DRS_OFS + Magnitude threshold high offset for AGC gain index 6 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_6_DRS_OFS + Magnitude threshold offset for AGC gain index 6 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX5_GAIN_CFG + AGC IDX5 Gain Config + 0xC8 + 32 + read-write + 0x107 + 0xFFFFFFFF + + + CBPF_GAIN_5 + CBPF_GAIN_5 + 0 + 1 + read-write + + + CBPF_GAIN_5_0 + -6 dB + 0 + + + CBPF_GAIN_5_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_5 + LNA_RTRIM_5 + 1 + 3 + read-write + + + LNA_ATTN_5 + LNA_ATTN_5 + 4 + 2 + read-write + + + LNA_HATTN_5 + LNA_HATTN_5 + 6 + 1 + read-write + + + LNA_LGAIN_5 + LNA_LGAIN_5 + 7 + 2 + read-write + + + LNA_HGAIN_5 + LNA_HGAIN_5 + 9 + 6 + read-write + + + ANT_EN_RLOAD_5 + ANT_EN_RLOAD_5 + 15 + 1 + read-write + + + MAG_THR_HI_5_DRS_OFS + Magnitude threshold high offset for AGC gain index 5 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_5_DRS_OFS + Magnitude threshold offset for AGC gain index 5 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX4_GAIN_CFG + AGC IDX4 Gain Config + 0xCC + 32 + read-write + 0x1A7 + 0xFFFFFFFF + + + CBPF_GAIN_4 + CBPF_GAIN_4 + 0 + 1 + read-write + + + CBPF_GAIN_4_0 + -6 dB + 0 + + + CBPF_GAIN_4_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_4 + LNA_RTRIM_4 + 1 + 3 + read-write + + + LNA_ATTN_4 + LNA_ATTN_4 + 4 + 2 + read-write + + + LNA_HATTN_4 + LNA_HATTN_4 + 6 + 1 + read-write + + + LNA_LGAIN_4 + LNA_LGAIN_4 + 7 + 2 + read-write + + + LNA_HGAIN_4 + LNA_HGAIN_4 + 9 + 6 + read-write + + + ANT_EN_RLOAD_4 + ANT_EN_RLOAD_4 + 15 + 1 + read-write + + + MAG_THR_HI_4_DRS_OFS + Magnitude threshold high offset for AGC gain index 4 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_4_DRS_OFS + Magnitude threshold offset for AGC gain index 4 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX3_GAIN_CFG + AGC IDX3 Gain Config + 0xD0 + 32 + read-write + 0x127 + 0xFFFFFFFF + + + CBPF_GAIN_3 + CBPF_GAIN_3 + 0 + 1 + read-write + + + CBPF_GAIN_3_0 + -6 dB + 0 + + + CBPF_GAIN_3_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_3 + LNA_RTRIM_3 + 1 + 3 + read-write + + + LNA_ATTN_3 + LNA_ATTN_3 + 4 + 2 + read-write + + + LNA_HATTN_3 + LNA_HATTN_3 + 6 + 1 + read-write + + + LNA_LGAIN_3 + LNA_LGAIN_3 + 7 + 2 + read-write + + + LNA_HGAIN_3 + LNA_HGAIN_3 + 9 + 6 + read-write + + + ANT_EN_RLOAD_3 + ANT_EN_RLOAD_3 + 15 + 1 + read-write + + + MAG_THR_HI_3_DRS_OFS + Magnitude threshold high offset for AGC gain index 3 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_3_DRS_OFS + Magnitude threshold offset for AGC gain index 3 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX2_GAIN_CFG + AGC IDX2 Gain Config + 0xD4 + 32 + read-write + 0xB7 + 0xFFFFFFFF + + + CBPF_GAIN_2 + CBPF_GAIN_2 + 0 + 1 + read-write + + + CBPF_GAIN_2_0 + -6 dB + 0 + + + CBPF_GAIN_2_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_2 + LNA_RTRIM_2 + 1 + 3 + read-write + + + LNA_ATTN_2 + LNA_ATTN_2 + 4 + 2 + read-write + + + LNA_HATTN_2 + LNA_HATTN_2 + 6 + 1 + read-write + + + LNA_LGAIN_2 + LNA_LGAIN_2 + 7 + 2 + read-write + + + LNA_HGAIN_2 + LNA_HGAIN_2 + 9 + 6 + read-write + + + ANT_EN_RLOAD_2 + ANT_EN_RLOAD_2 + 15 + 1 + read-write + + + MAG_THR_HI_2_DRS_OFS + Magnitude threshold high offset for AGC gain index 2 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_2_DRS_OFS + Magnitude threshold offset for AGC gain index 2 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX1_GAIN_CFG + AGC IDX1 Gain Config + 0xD8 + 32 + read-write + 0xB6 + 0xFFFFFFFF + + + CBPF_GAIN_1 + CBPF_GAIN_1 + 0 + 1 + read-write + + + CBPF_GAIN_1_0 + -6 dB + 0 + + + CBPF_GAIN_1_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_1 + LNA_RTRIM_1 + 1 + 3 + read-write + + + LNA_ATTN_1 + LNA_ATTN_1 + 4 + 2 + read-write + + + LNA_HATTN_1 + LNA_HATTN_1 + 6 + 1 + read-write + + + LNA_LGAIN_1 + LNA_LGAIN_1 + 7 + 2 + read-write + + + LNA_HGAIN_1 + LNA_HGAIN_1 + 9 + 6 + read-write + + + ANT_EN_RLOAD_1 + ANT_EN_RLOAD_1 + 15 + 1 + read-write + + + MAG_THR_HI_1_DRS_OFS + Magnitude threshold high offset for AGC gain index 1 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_1_DRS_OFS + Magnitude threshold offset for AGC gain index 1 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_IDX0_GAIN_CFG + AGC IDX0 Gain Config + 0xDC + 32 + read-write + 0x80F6 + 0xFFFFFFFF + + + CBPF_GAIN_0 + CBPF_GAIN_0 + 0 + 1 + read-write + + + CBPF_GAIN_0_0 + -6 dB + 0 + + + CBPF_GAIN_0_1 + 0 dB + 0x1 + + + + + LNA_RTRIM_0 + LNA_RTRIM_0 + 1 + 3 + read-write + + + LNA_ATTN_0 + LNA_ATTN_0 + 4 + 2 + read-write + + + LNA_HATTN_0 + LNA_HATTN_0 + 6 + 1 + read-write + + + LNA_LGAIN_0 + LNA_LGAIN_0 + 7 + 2 + read-write + + + LNA_HGAIN_0 + LNA_HGAIN_0 + 9 + 6 + read-write + + + ANT_EN_RLOAD_0 + ANT_EN_RLOAD_0 + 15 + 1 + read-write + + + MAG_THR_HI_0_DRS_OFS + Magnitude threshold high offset for AGC gain index 0 when datarate_config_sel = 1 + 16 + 8 + read-write + + + MAG_THR_0_DRS_OFS + Magnitude threshold offset for AGC gain index 0 when datarate_config_sel = 1 + 24 + 8 + read-write + + + + + AGC_MIS_GAIN_CFG + AGC Miscellaneous Gain Config + 0xE0 + 32 + read-write + 0x43 + 0xFFFFFFFF + + + LNA_RTRIM_IN_DCOC_CAL + LNA RTFE matching resistor adjustment value during DCOC calibration phase. + 0 + 3 + read-write + + + LNA_RTRIM_IN_TX_MODE + LNA RTFE matching resistor adjustment value in TX mode + 3 + 3 + read-write + + + LNA_HATTN_IN_TX_MODE + LNA high gain capacitor attenuation value in TX mode + 6 + 1 + read-write + + + + + AGC_IDX11_GAIN_VAL + AGC IDX11 Gain Value + 0xE4 + 32 + read-write + 0x10B + 0xFFFFFFFF + + + LOG_GAIN_11 + LOG_GAIN_11 + 0 + 10 + read-write + + + MAG_THR_HI_11 + Magnitude threshold high for AGC gain index 11 + 10 + 11 + read-write + + + MAG_THR_11 + Magnitude threshold for AGC gain index 11 + 21 + 11 + read-write + + + + + AGC_IDX10_GAIN_VAL + AGC_IDX10_GAIN_VAL + 0xE8 + 32 + read-write + 0xEB + 0xFFFFFFFF + + + LOG_GAIN_10 + LOG_GAIN_10 + 0 + 10 + read-write + + + MAG_THR_HI_10 + Magnitude threshold high for AGC gain index 10 + 10 + 11 + read-write + + + MAG_THR_10 + Magnitude threshold for AGC gain index 10 + 21 + 11 + read-write + + + + + AGC_IDX9_GAIN_VAL + AGC_IDX9_GAIN_VAL + 0xEC + 32 + read-write + 0xCD + 0xFFFFFFFF + + + LOG_GAIN_9 + LOG_GAIN_9 + 0 + 10 + read-write + + + MAG_THR_HI_9 + Magnitude threshold high for AGC gain index 9 + 10 + 11 + read-write + + + MAG_THR_9 + Magnitude threshold for AGC gain index 9 + 21 + 11 + read-write + + + + + AGC_IDX8_GAIN_VAL + AGC_IDX8_GAIN_VAL + 0xF0 + 32 + read-write + 0xAE + 0xFFFFFFFF + + + LOG_GAIN_8 + LOG_GAIN_8 + 0 + 10 + read-write + + + MAG_THR_HI_8 + Magnitude threshold high for AGC gain index 8 + 10 + 11 + read-write + + + MAG_THR_8 + Magnitude threshold for AGC gain index 8 + 21 + 11 + read-write + + + + + AGC_IDX7_GAIN_VAL + AGC_IDX7_GAIN_VAL + 0xF4 + 32 + read-write + 0x96 + 0xFFFFFFFF + + + LOG_GAIN_7 + LOG_GAIN_7 + 0 + 10 + read-write + + + MAG_THR_HI_7 + Magnitude threshold high for AGC gain index 7 + 10 + 11 + read-write + + + MAG_THR_7 + Magnitude threshold for AGC gain index 7 + 21 + 11 + read-write + + + + + AGC_IDX6_GAIN_VAL + AGC_IDX6_GAIN_VAL + 0xF8 + 32 + read-write + 0x77 + 0xFFFFFFFF + + + LOG_GAIN_6 + LOG_GAIN_6 + 0 + 10 + read-write + + + MAG_THR_HI_6 + Magnitude threshold highfor AGC gain index 6 + 10 + 11 + read-write + + + MAG_THR_6 + Magnitude threshold for AGC gain index 6 + 21 + 11 + read-write + + + + + AGC_IDX5_GAIN_VAL + AGC_IDX5_GAIN_VAL + 0xFC + 32 + read-write + 0x5F + 0xFFFFFFFF + + + LOG_GAIN_5 + LOG_GAIN_5 + 0 + 10 + read-write + + + MAG_THR_HI_5 + Magnitude threshold high for AGC gain index 5 + 10 + 11 + read-write + + + MAG_THR_5 + Magnitude threshold for AGC gain index 5 + 21 + 11 + read-write + + + + + AGC_IDX4_GAIN_VAL + AGC_IDX4_GAIN_VAL + 0x100 + 32 + read-write + 0x49 + 0xFFFFFFFF + + + LOG_GAIN_4 + LOG_GAIN_4 + 0 + 10 + read-write + + + MAG_THR_HI_4 + Magnitude threshold high for AGC gain index 4 + 10 + 11 + read-write + + + MAG_THR_4 + Magnitude threshold for AGC gain index 4 + 21 + 11 + read-write + + + + + AGC_IDX3_GAIN_VAL + AGC_IDX3_GAIN_VAL + 0x104 + 32 + read-write + 0x31 + 0xFFFFFFFF + + + LOG_GAIN_3 + LOG_GAIN_3 + 0 + 10 + read-write + + + MAG_THR_HI_3 + Magnitude threshold high for AGC gain index 3 + 10 + 11 + read-write + + + MAG_THR_3 + Magnitude threshold for AGC gain index 3 + 21 + 11 + read-write + + + + + AGC_IDX2_GAIN_VAL + AGC_IDX2_GAIN_VAL + 0x108 + 32 + read-write + 0x1A + 0xFFFFFFFF + + + LOG_GAIN_2 + LOG_GAIN_2 + 0 + 10 + read-write + + + MAG_THR_HI_2 + Magnitude threshold high for AGC gain index 2 + 10 + 11 + read-write + + + MAG_THR_2 + Magnitude threshold for AGC gain index 2 + 21 + 11 + read-write + + + + + AGC_IDX1_GAIN_VAL + AGC_IDX1_GAIN_VAL + 0x10C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOG_GAIN_1 + LOG_GAIN_1 + 0 + 10 + read-write + + + MAG_THR_HI_1 + Magnitude threshold high for AGC gain index 1 + 10 + 11 + read-write + + + MAG_THR_1 + Magnitude threshold for AGC gain index 1 + 21 + 11 + read-write + + + + + AGC_IDX0_GAIN_VAL + AGC_IDX0_GAIN_VAL + 0x110 + 32 + read-write + 0x3E4 + 0xFFFFFFFF + + + LOG_GAIN_0 + LOG_GAIN_0 + 0 + 10 + read-write + + + MAG_THR_HI_0 + Magnitude threshold high for AGC gain index 0 + 10 + 11 + read-write + + + MAG_THR_0 + Magnitude threshold for AGC gain index 0 + 21 + 11 + read-write + + + + + AGC_THR_FAST + AGC Fast Mode Threshold + 0x114 + 32 + read-write + 0x1C2001E + 0xFFFFFFFF + + + STEP_UP_THR_FAST + STEP_UP_THR_FAST + 0 + 9 + read-write + + + STEP_DOWN_THR_FAST + STEP_DOWN_THR_FAST + 16 + 9 + read-write + + + + + AGC_THR_FAST_DRS + AGC Fast Mode Threshold DRS + 0x118 + 32 + read-write + 0x1C2001E + 0xFFFFFFFF + + + STEP_UP_THR_FAST + STEP_UP_THR_FAST + 0 + 9 + read-write + + + STEP_DOWN_THR_FAST + STEP_DOWN_THR_FAST + 16 + 9 + read-write + + + + + AGC_IDX11_THR + AGC IDX11 Slow Mode Threshold + 0x11C + 32 + read-write + 0x1900000 + 0xFFFFFFFF + + + STEP_DOWN_THR_11 + STEP_DOWN_THR_11 + 16 + 9 + read-write + + + STEP_DOWN_THR_11_DRS_OFS + STEP_DOWN_THR_11 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX10_THR + AGC IDX10 Slow Mode Threshold + 0x120 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_10 + STEP_UP_THR_10 + 0 + 9 + read-write + + + STEP_DOWN_THR_10 + STEP_DOWN_THR_10 + 16 + 9 + read-write + + + STEP_DOWN_THR_10_DRS_OFS + STEP_DOWN_THR_10 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX9_THR + AGC IDX9 Slow Mode Threshold + 0x124 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_9 + STEP_UP_THR_9 + 0 + 9 + read-write + + + STEP_DOWN_THR_9 + STEP_DOWN_THR_9 + 16 + 9 + read-write + + + STEP_DOWN_THR_9_DRS_OFS + STEP_DOWN_THR_9 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX8_THR + AGC IDX8 Slow Mode Threshold + 0x128 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_8 + STEP_UP_THR_8 + 0 + 9 + read-write + + + STEP_DOWN_THR_8 + STEP_DOWN_THR_8 + 16 + 9 + read-write + + + STEP_DOWN_THR_8_DRS_OFS + STEP_DOWN_THR_8 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX7_THR + AGC IDX7 Slow Mode Threshold + 0x12C + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_7 + STEP_UP_THR_7 + 0 + 9 + read-write + + + STEP_DOWN_THR_7 + STEP_DOWN_THR_7 + 16 + 9 + read-write + + + STEP_DOWN_THR_7_DRS_OFS + STEP_DOWN_THR_7 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX6_THR + AGC IDX6 Slow Mode Threshold + 0x130 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_6 + STEP_UP_THR_6 + 0 + 9 + read-write + + + STEP_DOWN_THR_6 + STEP_DOWN_THR_6 + 16 + 9 + read-write + + + STEP_DOWN_THR_6_DRS_OFS + STEP_DOWN_THR_6 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX5_THR + AGC IDX5 Slow Mode Threshold + 0x134 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_5 + STEP_UP_THR_5 + 0 + 9 + read-write + + + STEP_DOWN_THR_5 + STEP_DOWN_THR_5 + 16 + 9 + read-write + + + STEP_DOWN_THR_5_DRS_OFS + STEP_DOWN_THR_5 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX4_THR + AGC IDX4 Slow Mode Threshold + 0x138 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_4 + STEP_UP_THR_4 + 0 + 9 + read-write + + + STEP_DOWN_THR_4 + STEP_DOWN_THR_4 + 16 + 9 + read-write + + + STEP_DOWN_THR_4_DRS_OFS + STEP_DOWN_THR_4 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX3_THR + AGC IDX3 Slow Mode Threshold + 0x13C + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_3 + STEP_UP_THR_3 + 0 + 9 + read-write + + + STEP_DOWN_THR_3 + STEP_DOWN_THR_3 + 16 + 9 + read-write + + + STEP_DOWN_THR_3_DRS_OFS + STEP_DOWN_THR_3 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX2_THR + AGC IDX2 Slow Mode Threshold + 0x140 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_2 + STEP_UP_THR_2 + 0 + 9 + read-write + + + STEP_DOWN_THR_2 + STEP_DOWN_THR_2 + 16 + 9 + read-write + + + STEP_DOWN_THR_2_DRS_OFS + STEP_DOWN_THR_2 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX1_THR + AGC IDX1 Slow Mode Threshold + 0x144 + 32 + read-write + 0x1900032 + 0xFFFFFFFF + + + STEP_UP_THR_1 + STEP_UP_THR_1 + 0 + 9 + read-write + + + STEP_DOWN_THR_1 + STEP_DOWN_THR_1 + 16 + 9 + read-write + + + STEP_DOWN_THR_1_DRS_OFS + STEP_DOWN_THR_1 DRS Offset + 25 + 7 + read-write + + + + + AGC_IDX0_THR + AGC IDX0 Slow Mode Threshold + 0x148 + 32 + read-write + 0x32 + 0xFFFFFFFF + + + STEP_UP_THR_0 + STEP_UP_THR_0 + 0 + 9 + read-write + + + + + AGC_THR_MIS + AGC Miscellaneous Thresholds + 0x14C + 32 + read-write + 0x140028 + 0xFFFFFFFF + + + DELTA_SLOW_THR + STEP_UP_THR_VLG2 + 0 + 9 + read-write + + + HOLD_MARGIN_THR + STEP_UP_THR_VLG2large + 16 + 9 + read-write + + + + + AGC_OVRD + AGC Override Control + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + AGC_GAIN_OVRD + AGC gain config override values + 0 + 16 + read-write + + + AGC_GAIN_OVRD_EN + AGC gain config override enable + 16 + 1 + read-write + + + AGC_GAIN_IDX_OVRD + AGC gain index override value. + 17 + 4 + read-write + + + AGC_GAIN_IDX_OVRD_EN + AGC gain index override enable. + 21 + 1 + read-write + + + AGC_PHY_HOLD_OVRD + PHY_HOLD_TRIG signal override value + 22 + 1 + read-write + + + AGC_PHY_HOLD_OVRD_EN + PHY_HOLD_TRIG signal override enable + 23 + 1 + read-write + + + AGC_PHY_FREEZE_OVRD + PHY_FREEZE_TRIG signal override value + 24 + 1 + read-write + + + AGC_PHY_FREEZE_OVRD_EN + PHY_FREEZE_TRIG signal override enable + 25 + 1 + read-write + + + + + DC_RESID_CTRL + DC Residual Control + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DC_RESID_NWIN + DC Residual NWIN + 0 + 7 + read-write + + + DC_RESID_ITER_FREEZE + DC Residual Iteration Freeze + 8 + 4 + read-write + + + DC_RESID_ALPHA + DC Residual Alpha + 12 + 3 + read-write + + + DC_RESID_ALPHA_0 + Update factor is 1 + 0 + + + DC_RESID_ALPHA_1 + Update factor is 1/2 + 0x1 + + + DC_RESID_ALPHA_2 + Update factor is 1/4 + 1/8 + 0x2 + + + DC_RESID_ALPHA_3 + Update factor is 1/4 + 0x3 + + + DC_RESID_ALPHA_4 + Update factor is 1/8 + 16 + 0x4 + + + DC_RESID_ALPHA_5 + Update factor is 1/8 + 0x5 + + + DC_RESID_ALPHA_6 + Update factor is 1/16 + 1/32 + 0x6 + + + DC_RESID_ALPHA_7 + Update factor is 1/16 + 0x7 + + + + + DC_RESID_GS_EN + DC Residual Gearshift Enable + 15 + 1 + read-write + + + DC_RESID_GS_EN_0 + Gearshifting disabled + 0 + + + DC_RESID_GS_EN_1 + Gearshifting enabled + 0x1 + + + + + DC_RESID_DLY + DC Residual Delay + 16 + 3 + read-write + + + DC_RESID_SECOND_RUN_EN + DC Residual Second Run Enable + 19 + 1 + read-write + + + DC_RESID_SECOND_RUN_EN_0 + Second Run disabled + 0 + + + DC_RESID_SECOND_RUN_EN_1 + Second Run enabled + 0x1 + + + + + DC_RESID_EXT_DC_EN + DC Residual External DC Enable + 20 + 1 + read-write + + + DC_RESID_EXT_DC_EN_0 + External DC disable. The DC Residual activates at a delay specified by DC_RESID_DLY after an AGC gain change pulse. The DC Residual is initialized with a DC offset of 0. + 0 + + + DC_RESID_EXT_DC_EN_1 + External DC enable. The DC residual activates after the DCOC's tracking hold timer expires. The DC Residual is initialized with the DC estimate from the DCOC tracking estimator. + 0x1 + + + + + DC_RESID_MIN_AGC_IDX + DC Residual Minimum AGC Table Index + 24 + 5 + read-write + + + DC_RESID_GEARSHIFT + DC Residual Gearshift + 29 + 3 + read-write + + + + + DC_RESID_CTRL2 + DC Residual Control2 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DC_RESID_NWIN2 + DC Residual NWIN, for Second Run + 0 + 9 + read-write + + + DC_RESID_PHY_STOP_EN + DC Residual PHY Stop Enable + 9 + 1 + read-write + + + DC_RESID_CC_EN + DC Residual Continuous Correction Enable + 10 + 1 + read-write + + + DC_RESID_SR2_EN + DC Residual Slewrate Enable, for Second Run + 11 + 1 + read-write + + + DC_RESID_ALPHA2 + DC Residual Alpha, for Second Run + 12 + 3 + read-write + + + DC_RESID_ALPHA2_0 + Update factor is 1 + 0 + + + DC_RESID_ALPHA2_1 + Update factor is 1/2 + 0x1 + + + DC_RESID_ALPHA2_2 + Update factor is 1/4 + 1/8 + 0x2 + + + DC_RESID_ALPHA2_3 + Update factor is 1/4 + 0x3 + + + DC_RESID_ALPHA2_4 + Update factor is 1/8 + 16 + 0x4 + + + DC_RESID_ALPHA2_5 + Update factor is 1/8 + 0x5 + + + DC_RESID_ALPHA2_6 + Update factor is 1/16 + 1/32 + 0x6 + + + DC_RESID_ALPHA2_7 + Update factor is 1/16 + 0x7 + + + + + DC_RESID_GS2_EN + DC Residual Gearshift Enable, for Second Run + 15 + 1 + read-write + + + DC_RESID_GS2_EN_0 + Gearshifting disabled for Second Run + 0 + + + DC_RESID_GS2_EN_1 + Gearshifting enabled for Second Run + 0x1 + + + + + DC_RESID_ITER_FREEZE2 + DC Residual Iteration Freeze, for Second Run + 16 + 5 + read-write + + + DC_RESID_SLEWRATE2 + DC Residual Slewrate, for Second Run + 21 + 3 + read-write + + + DC_RESID_MIN_AGC_IDX2 + DC Residual Minimum AGC Table Index, for Second Run + 24 + 5 + read-write + + + DC_RESID_GEARSHIFT2 + DC Residual Gearshift, for Second Run + 29 + 3 + read-write + + + + + DC_RESID_CTRL_DRS + DC Residual Control DataRate1 + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DC_RESID_NWIN + DC Residual NWIN + 0 + 7 + read-write + + + DC_RESID_DLY + DC Residual Delay + 16 + 3 + read-write + + + DC_RESID_NWIN2 + DC Residual NWIN, for Second Run + 20 + 9 + read-write + + + + + DC_RESID_EST + DC Residual Estimate + 0x160 + 32 + read-only + 0 + 0xFFFFFFFF + + + DC_RESID_OFFSET_I + DC Residual Offset I + 0 + 13 + read-only + + + DC_RESID_OFFSET_Q + DC Residual Offset Q + 16 + 13 + read-only + + + + + DFT_TONE_ANALYZER0 + DfT tone analyzer + 0x164 + 32 + read-write + 0xA000 + 0xFFFFFFFF + + + ipr_dft_ana_start_offset_q + Q Initial Phase + 0 + 9 + read-write + + + ipr_dft_ana_start_offset_i + I Initial Phase + 9 + 9 + read-write + + + ipr_dft_ana_attenuation_q + Tone Attenuation For Q Path + 18 + 3 + read-write + + + ipr_dft_ana_attenuation_i + Check description of ipr_dft_ana_attenuation_q + 21 + 3 + read-write + + + ipr_dft_ana_en + Enable for DfT tone analyzer + 24 + 1 + read-write + + + + + DFT_TONE_ANALYZER1 + DfT tone analyzer + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + rx_tone_ana_accu_ovf + Indicate the accumulator has overflow during measurement. + 0 + 1 + read-only + + + rx_tone_ana_bitshift_ovf + Indicate the accumulator input has overflow during measurement. + 1 + 1 + read-only + + + ipr_dft_ana_bitshift + Accumulaotr input valude scale down factor. + 2 + 4 + read-write + + + rx_tone_ana_done + Read only status bit. Indicating the tone analyze finished. + 6 + 1 + read-only + + + ipr_dft_ana_start + Set 1 to trig the DFT Tone Analyzer + 7 + 1 + read-write + + + ipr_dft_ana_input_sel_2 + Should always set 2 for this field + 8 + 2 + read-write + + + ipr_dft_ana_input_sel_1 + Should always set 0 for this field + 10 + 2 + read-write + + + ipr_dft_ana_increment + ipr_dft_ana_increment and ipr_dft_ana_clk_div determines the tone frequence + 12 + 7 + read-write + + + ipr_dft_ana_clk_div + Clock divider factor for tone generator. Check ipr_dft_ana_increment for more information. + 19 + 3 + read-write + + + ipr_dft_ana_clk_div_0 + ref_clk + 0 + + + ipr_dft_ana_clk_div_1 + ref_clk div 2 + 0x1 + + + ipr_dft_ana_clk_div_2 + ref_clk div 4 + 0x2 + + + ipr_dft_ana_clk_div_3 + ref_clk div 8 + 0x3 + + + ipr_dft_ana_clk_div_4 + ref_clk div 16 + 0x4 + + + + + + + DFT_TONE_ANALYZER2 + DfT tone analyzer + 0x16C + 32 + read-only + 0 + 0xFFFFFFFF + + + rx_tone_ana_out_q + Accumulator Q-path result + 0 + 16 + read-only + + + rx_tone_ana_out_i + Accumulator I-path result + 16 + 16 + read-only + + + + + DFT_TONE_ANALYZER3 + DfT tone analyzer + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ipr_dft_ana_accumulation_length + Accumulation length + 0 + 15 + read-write + + + rx_tone_ana_out_abs + Tone Analyzer Result + 15 + 16 + read-only + + + + + DCOC_DIG_CORR_RESULT + DCOC Digital Correction Result + 0x174 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_DIG_CORR_Q + DCOC I-Channel Residual After Calibration + 0 + 8 + read-only + + + DCOC_DIG_CORR_I + DCOC Q-Channel Residual After Calibration + 8 + 8 + read-only + + + + + + + XCVR_TX_DIG + XCVR_TX_DIG + XCVR_TX_DIG + 0x48A07200 + + 0 + 0x1000 + registers + + + + TXDIG_CTRL + TXDIG_CTRL + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MODULATOR_SEL + MODULATOR_SEL + 0 + 1 + read-write + + + PFC_EN + PFC_EN + 1 + 1 + read-write + + + DATA_STREAM_SEL + DATA_STREAM_SEL + 2 + 1 + read-write + + + INV_DATA_OUT + INV_DATA_OUT + 4 + 1 + read-write + + + + + DATA_PADDING_CTRL + DATA_PADDING_CTRL + 0x4 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + DATA_PADDING_SEL + DATA_PADDING_SEL + 0 + 2 + read-write + + + TX_CAPTURE_POL + TX_CAPTURE_POL + 2 + 1 + read-write + + + CTE_DATA + CTE_DATA + 4 + 1 + read-write + + + PAD_DLY + PAD_DLY + 8 + 4 + read-write + + + PAD_DLY_EN + PAD_DLY_EN + 12 + 1 + read-write + + + RAMP_DN_PAD_EN + RAMP_DN_PAD_EN + 16 + 1 + read-write + + + + + DATA_PADDING_CTRL_1 + DATA_PADDING_CTRL_1 + 0x8 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RAMP_UP_DLY + RAMP_UP_DLY + 0 + 5 + read-write + + + TX_DATA_FLUSH_DLY + TX_DATA_FLUSH_DLY + 8 + 3 + read-write + + + PA_PUP_ADJ + PA_PUP_ADJ + 12 + 4 + read-write + + + + + DATA_PADDING_CTRL_2 + DATA_PADDING_CTRL_2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_PAD_MFDEV + DATA_PAD_MFDEV + 0 + 13 + read-write + + + DATA_PAD_PFDEV + DATA_PAD_PFDEV + 16 + 13 + read-write + + + + + FSK_CTRL + FSK_CTRL + 0x10 + 32 + read-write + 0x8001800 + 0xFFFFFFFF + + + FSK_FDEV_0 + FSK_FDEV_0 + 0 + 13 + read-write + + + FSK_FDEV_1 + FSK_FDEV_1 + 16 + 13 + read-write + + + + + GFSK_CTRL + GFSK_CTRL + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_FDEV + GFSK_FDEV + 0 + 12 + read-write + + + GFSK_COEFF_MAN + GFSK_COEFF_MAN + 12 + 1 + read-write + + + BT_EQ_OR_GTR_ONE + BT_EQ_OR_GTR_ONE + 16 + 1 + read-write + + + + + GFSK_COEFF_0_1 + GFSK_COEFF_0_1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_0 + GFSK_COEFF_0 + 0 + 9 + read-write + + + GFSK_COEFF_1 + GFSK_COEFF_1 + 16 + 9 + read-write + + + + + GFSK_COEFF_2_3 + GFSK_COEFF_2_3 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_2 + GFSK_COEFF_2 + 0 + 9 + read-write + + + GFSK_COEFF_3 + GFSK_COEFF_3 + 16 + 9 + read-write + + + + + GFSK_COEFF_4_5 + GFSK_COEFF_4_5 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_4 + GFSK_COEFF_4 + 0 + 9 + read-write + + + GFSK_COEFF_5 + GFSK_COEFF_5 + 16 + 9 + read-write + + + + + GFSK_COEFF_6_7 + GFSK_COEFF_6_7 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_6 + GFSK_COEFF_6 + 0 + 9 + read-write + + + GFSK_COEFF_7 + GFSK_COEFF_7 + 16 + 9 + read-write + + + + + IMAGE_FILTER_CTRL + IMAGE_FILTER_CTRL + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMAGE_FIR_FILTER_SEL + IMAGE_FIR_FILTER_SEL + 0 + 2 + read-write + + + IMAGE_FILTER_OVRD_EN + IMAGE_FILTER_OVRD_EN + 2 + 1 + read-write + + + IMAGE_FIR_FILTER_OVRD + IMAGE_FIR_FILTER_OVRD + 3 + 1 + read-write + + + IMAGE_SYNC1_FILTER_OVRD + IMAGE_SYNC1_FILTER_OVRD + 4 + 1 + read-write + + + IMAGE_SYNC0_FILTER_OVRD + IMAGE_SYNC0_FILTER_OVRD + 5 + 1 + read-write + + + FREQ_WORD_ADJ + FREQ_WORD_ADJ + 16 + 10 + read-write + + + + + PA_CTRL + PA_CTRL + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PA_TGT_POWER + PA_TGT_POWER + 0 + 6 + read-write + + + TGT_PWR_SRC + TGT_PWR_SRC + 8 + 1 + read-write + + + EARLY_WU_COMPLETE + EARLY_WU_COMPLETE + 12 + 1 + read-write + + + RAMP_CS + RAMP_CS + 13 + 3 + read-only + + + PA_RAMP_SEL + PA_RAMP_SEL + 16 + 2 + read-write + + + TX_PA_PUP_OVRD + TX_PA_PUP_OVRD + 30 + 1 + read-write + + + TX_PA_PUP_OVRD_EN + TX_PA_PUP_OVRD_EN + 31 + 1 + read-write + + + + + PA_RAMP_TBL0 + PA_RAMP_TBL0 + 0x30 + 32 + read-write + 0x6040201 + 0xFFFFFFFF + + + PA_RAMP0 + PA_RAMP0 + 0 + 6 + read-write + + + PA_RAMP1 + PA_RAMP1 + 8 + 6 + read-write + + + PA_RAMP2 + PA_RAMP2 + 16 + 6 + read-write + + + PA_RAMP3 + PA_RAMP3 + 24 + 6 + read-write + + + + + PA_RAMP_TBL1 + PA_RAMP_TBL1 + 0x34 + 32 + read-write + 0x14100C09 + 0xFFFFFFFF + + + PA_RAMP4 + PA_RAMP4 + 0 + 6 + read-write + + + PA_RAMP5 + PA_RAMP5 + 8 + 6 + read-write + + + PA_RAMP6 + PA_RAMP6 + 16 + 6 + read-write + + + PA_RAMP7 + PA_RAMP7 + 24 + 6 + read-write + + + + + PA_RAMP_TBL2 + PA_RAMP_TBL2 + 0x38 + 32 + read-write + 0x26211C18 + 0xFFFFFFFF + + + PA_RAMP8 + PA_RAMP8 + 0 + 6 + read-write + + + PA_RAMP9 + PA_RAMP9 + 8 + 6 + read-write + + + PA_RAMP10 + PA_RAMP10 + 16 + 6 + read-write + + + PA_RAMP11 + PA_RAMP11 + 24 + 6 + read-write + + + + + PA_RAMP_TBL3 + PA_RAMP_TBL3 + 0x3C + 32 + read-write + 0x3C38322C + 0xFFFFFFFF + + + PA_RAMP12 + PA_RAMP12 + 0 + 6 + read-write + + + PA_RAMP13 + PA_RAMP13 + 8 + 6 + read-write + + + PA_RAMP14 + PA_RAMP14 + 16 + 6 + read-write + + + PA_RAMP15 + PA_RAMP15 + 24 + 6 + read-write + + + + + SWITCH_TX_CTRL + SWITCH_TX_CTRL + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWITCH_MOD + SWITCH_MOD + 0 + 1 + read-write + + + SWITCH_FIR_SEL + SWITCH_FIR_SEL + 1 + 2 + read-write + + + SWITCH_GFSK_COEFF + SWITCH_GFSK_COEFF + 3 + 1 + read-write + + + SWITCH_TGT_PWR + SWITCH_TGT_PWR + 8 + 6 + read-write + + + + + RF_DFT_TX_CTRL0 + RF_DFT_TX_CTRL0 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_MAX_RAM_SIZE + DFT_MAX_RAM_SIZE + 0 + 15 + read-write + + + DFT_RAM_BASE_ADDR + DFT_RAM_BASE_ADDR + 16 + 15 + read-write + + + DFT_RAM_EN + DFT_RAM_EN + 31 + 1 + read-write + + + + + RF_DFT_TX_CTRL1 + RF_DFT_TX_CTRL1 + 0x48 + 32 + read-write + 0x2101FFFF + 0xFFFFFFFF + + + LFSR_OUT + LFSR_OUT + 0 + 17 + read-only + + + LFSR_CLK_SEL + LFSR_CLK_SEL + 24 + 3 + read-write + + + LFSR_LENGTH + LFSR_LENGTH + 27 + 3 + read-write + + + LRM + LRM + 30 + 1 + read-write + + + LFSR_EN + LFSR_EN + 31 + 1 + read-write + + + + + RF_DFT_TX_CTRL2 + RF_DFT_TX_CTRL2 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_PA_AM_MOD_FREQ + DFT_PA_AM_MOD_FREQ + 0 + 4 + read-write + + + DFT_PA_AM_MOD_ENTRIES + DFT_PA_AM_MOD_ENTRIES + 4 + 4 + read-write + + + DFT_PA_AM_MOD_EN + DFT_PA_AM_MOD_EN + 8 + 1 + read-write + + + DFT_PATTERN_EN + DFT_PATTERN_EN + 31 + 1 + read-write + + + + + RF_DFT_PATTERN + RF_DFT_PATTERN + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_MOD_PATTERN + DFT_MOD_PATTERN + 0 + 32 + read-write + + + + + DATARATE_CONFIG_FSK_CTRL + DATARATE_CONFIG_FSK_CTRL + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATARATE_CONFIG_FSK_FDEV0 + DATARATE_CONFIG_DATA_PAD_MFDEV + 0 + 13 + read-write + + + DATARATE_CONFIG_FSK_FDEV1 + DATARATE_CONFIG_DATA_PAD_PFDEV + 16 + 13 + read-write + + + + + DATARATE_CONFIG_GFSK_CTRL + DATARATE_CONFIG_GFSK_CTRL + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATARATE_CONFIG_GFSK_FDEV + DATARATE_CONFIG_GFSK_FDEV + 0 + 12 + read-write + + + + + DATARATE_CONFIG_FILTER_CTRL + DATARATE_CONFIG_FILTER_CTRL + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN + DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN + 0 + 1 + read-write + + + DATARATE_CONFIG_FIR_FILTER_OVRD + DATARATE_CONFIG_FIR_FILTER_OVRD + 1 + 1 + read-write + + + DATARATE_CONFIG_SYNC0_FILTER_OVRD + DATARATE_CONFIG_SYNC0_FILTER_OVRD + 2 + 1 + read-write + + + DATARATE_CONFIG_SYNC1_FILTER_OVRD + DATARATE_CONFIG_SYNC1_FILTER_OVRD + 3 + 1 + read-write + + + DATARATE_CONFIG_GFSK_FILT_CLK_SEL + DATARATE_CONFIG_GFSK_FILT_CLK_SEL + 16 + 3 + read-write + + + DATARATE_CONFIG_SYNC0_CLK_SEL + DATARATE_CONFIG_IMAGE_SYNC0_CLK_SEL + 20 + 3 + read-write + + + DATARATE_CONFIG_SYNC1_CLK_SEL + DATARATE_CONFIG_IMAGE_SYNC1_CLK_SEL + 24 + 3 + read-write + + + DATARATE_CONFIG_IMAGE_FIR_CLK_SEL + DATARATE_CONFIG_IMAGE_FIR_CLK_SEL + 28 + 1 + read-write + + + + + + + XCVR_PLL_DIG + XCVR_PLL_DIG + XCVR_PLL_DIG + 0x48A07300 + + 0 + 0x100 + registers + + + + HPM_BUMP + PLL HPM Analog Bump Control + 0 + 32 + read-write + 0x441012 + 0xFFFFFFFF + + + HPM_VCM_TX + a_ip_2p4ghz_reg_dac_trim_vcm_dig[2:0] during Transmission + 0 + 3 + read-write + + + HPM_VCM_TX_0 + 0.120 (0.122) + 0 + + + HPM_VCM_TX_1 + 0.153 (0.189) + 0x1 + + + HPM_VCM_TX_2 + 0.182 (0.247) + 0x2 + + + HPM_VCM_TX_3 + 0.209 (0.300) + 0x3 + + + HPM_VCM_TX_4 + 0.234 (0.348) + 0x4 + + + HPM_VCM_TX_5 + 0.258 (0.393) + 0x5 + + + HPM_VCM_TX_6 + 0.279 (0.434) + 0x6 + + + HPM_VCM_TX_7 + 0.318 (0.509) + 0x7 + + + + + HPM_VCM_CAL + a_ip_2p4ghz_reg_dac_trim_vcm_dig[2:0] during Calibration + 4 + 3 + read-write + + + HPM_VCM_CAL_0 + 0.120 (0.122) + 0 + + + HPM_VCM_CAL_1 + 0.153 (0.189) + 0x1 + + + HPM_VCM_CAL_2 + 0.182 (0.247) + 0x2 + + + HPM_VCM_CAL_3 + 0.209 (0.300) + 0x3 + + + HPM_VCM_CAL_4 + 0.234 (0.348) + 0x4 + + + HPM_VCM_CAL_5 + 0.258 (0.393) + 0x5 + + + HPM_VCM_CAL_6 + 0.279 (0.434) + 0x6 + + + HPM_VCM_CAL_7 + 0.318 (0.509) + 0x7 + + + + + HPM_FDB_RES_TX + a_ip_2p4ghz_reg_dac_trim_rfbk_dig[1:0] during Transmission + 8 + 2 + read-write + + + HPM_FDB_RES_TX_0 + 38.0k (1.0) + 0 + + + HPM_FDB_RES_TX_1 + 76.0k (0.5) + 0x1 + + + HPM_FDB_RES_TX_2 + 32.5k (1.14) + 0x2 + + + HPM_FDB_RES_TX_3 + 25.3k (1.4) + 0x3 + + + + + HPM_FDB_RES_CAL + a_ip_2p4ghz_reg_dac_trim_rfbk_dig[1:0] during Calibration + 12 + 2 + read-write + + + HPM_FDB_RES_CAL_0 + 38.0k (1.0) + 0 + + + HPM_FDB_RES_CAL_1 + 76.0k (0.5) + 0x1 + + + HPM_FDB_RES_CAL_2 + 32.5k (1.14) + 0x2 + + + HPM_FDB_RES_CAL_3 + 25.3k (1.4) + 0x3 + + + + + PLL_VCO_TRIM_KVM_TX + reg_vco_trim_kvm_dig[2:0] for transmitt + 16 + 3 + read-write + + + PLL_VCO_TRIM_KVM_TX_0 + 10MHz/V + 0 + + + PLL_VCO_TRIM_KVM_TX_4 + 20MHz/V + 0x4 + + + PLL_VCO_TRIM_KVM_TX_6 + 30MHz/V + 0x6 + + + PLL_VCO_TRIM_KVM_TX_7 + 40MHz/V + 0x7 + + + + + PLL_VCO_TRIM_KVM_CAL + reg_vco_trim_kvm_dig[2:0] for calibration + 20 + 3 + read-write + + + PLL_VCO_TRIM_KVM_CAL_0 + 10MHz/V + 0 + + + PLL_VCO_TRIM_KVM_CAL_4 + 20MHz/V + 0x4 + + + PLL_VCO_TRIM_KVM_CAL_6 + 30MHz/V + 0x6 + + + PLL_VCO_TRIM_KVM_CAL_7 + 40MHz/V + 0x7 + + + + + + + MOD_CTRL + PLL Modulation Control + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MODULATION_WORD_MANUAL + Manual Modulation Word + 0 + 13 + read-write + + + MOD_DISABLE + Disable Modulation Word + 15 + 1 + read-write + + + HPM_MOD_MANUAL + Manual HPM Modulation + 16 + 8 + read-write + + + HPM_MOD_DISABLE + Disable HPM Modulation + 27 + 1 + read-write + + + HPM_SDM_OUT_MANUAL + Manual HPM SDM out + 28 + 2 + read-write + + + HPM_SDM_OUT_DISABLE + Disable HPM SDM out + 31 + 1 + read-write + + + + + CHAN_MAP + PLL Channel Mapping + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHANNEL_NUM_OVRD + Channel Selection Override + 0 + 16 + read-write + + + BAND_SELECT + Channel Mapping Band Select + 16 + 3 + read-write + + + BAND_SELECT_0 + Bluetooth Low Energy + 0 + + + BAND_SELECT_1 + Bluetooth Low Energy in MBAN + 0x1 + + + BAND_SELECT_2 + Bluetooth Low Energy overlap MBAN + 0x2 + + + BAND_SELECT_4 + IEEE 802.15.4 O-QPSK PHY in ISM band + 0x4 + + + BAND_SELECT_5 + IEEE 802.15.4 O-QPSK PHY in MBAN band + 0x5 + + + BAND_SELECT_6 + Radio Channels 0-127 selectable + 0x6 + + + BAND_SELECT_7 + Radio Channels 0-127 selectable + 0x7 + + + + + BMR + Bluetooth Low Energy MBAN Channel Remap + 19 + 1 + read-write + + + BMR_0 + Bluetooth Low Energy channel 39 is mapped to Bluetooth Low Energy channel 39, 2.480 GHz + 0 + + + BMR_1 + Bluetooth Low Energy channel 39 is mapped to MBAN channel 39, 2.399 GHz + 0x1 + + + + + HOP_TBL_CFG_OVRD + Hop Table Configuration Override + 24 + 3 + read-write + + + HOP_TBL_CFG_OVRD_0 + CHANNEL_NUM_OVRD[6:0] is used as the mapped channel number. CHANNEL_NUM_OVRD[15:7] is unused. + 0 + + + HOP_TBL_CFG_OVRD_1 + CHANNEL_NUM_OVRD[6:0] is used as the mapped channel number. CHANNEL_NUM_OVRD[15:7] is unused. + 0x1 + + + HOP_TBL_CFG_OVRD_2 + CHANNEL_NUM_OVRD[15:7] is signed Numerator offset to CHANNEL_NUM_OVRD[6:0] mapped channel number + 0x2 + + + HOP_TBL_CFG_OVRD_3 + CHANNEL_NUM_OVRD[15:1] is selected as the signed Numerator, CHANNEL_NUM_OVRD[0] is integer selection + 0x3 + + + + + HOP_TBL_CFG_OVRD_EN + Hop Table Configuration Override Enable + 27 + 1 + read-write + + + + + CHAN_MAP_EXT + PLL Channel Mapping Extended + 0x10 + 32 + read-write + 0x100000 + 0xFFFFFFFF + + + NUM_OFFSET + Numerator Offset + 0 + 28 + read-write + + + CTUNE_TGT_OFFSET + Coarse Tune Target Frequency Offset + 28 + 3 + read-write + + + + + LOCK_DETECT + PLL Lock Detect Control + 0x18 + 32 + read-write + 0x606800 + 0xFFFFFFFF + + + CT_FAIL + Real time status of Coarse Tune Fail signal + 0 + 1 + read-only + + + CTFF + CTUNE Failure Flag, held until cleared + 1 + 1 + read-write + oneToClear + + + FT_FAIL + Real time status of Frequency Target Failure + 4 + 1 + read-only + + + FTFF + Frequency Target Failure Flag + 5 + 1 + read-write + oneToClear + + + CTUNE_LDF_LEV + CTUNE Lock Detect Fail Level + 8 + 4 + read-write + + + FTF_RX_THRSH + RX Frequency Target Fail Threshold + 12 + 6 + read-write + + + FTF_TX_THRSH + TX Frequency Target Fail Threshold + 18 + 6 + read-write + + + FCAL_HOLD_EN + Frequency Counter Hold Enable + 24 + 1 + read-write + + + FCAL_HOLD_EN_0 + The frequency counter is turned off after CTUNE (RX Mode) or HPM CAL (TX Mode) + 0 + + + FCAL_HOLD_EN_1 + The frequency counter is held on after CTUNE (RX Mode) or HPM CAL (TX Mode) for an optional lock detect sequence. + 0x1 + + + + + FTW_TXRX + TX and RX Frequency Target Window time select + 25 + 3 + read-write + + + FTW_TXRX_0 + FTW_TX = 4us ; FTW_RX = 4us + 0 + + + FTW_TXRX_1 + FTW_TX = 4us ; FTW_RX = 8us + 0x1 + + + FTW_TXRX_2 + FTW_TX = 8us ; FTW_RX = 4us + 0x2 + + + FTW_TXRX_3 + FTW_TX = 8us ; FTW_RX = 8us + 0x3 + + + FTW_TXRX_4 + FTW_TX = 16us ; FTW_RX = 16us + 0x4 + + + FTW_TXRX_5 + FTW_TX = 16us ; FTW_RX = 32us + 0x5 + + + FTW_TXRX_6 + FTW_TX = 32us ; FTW_RX = 16us + 0x6 + + + FTW_TXRX_7 + FTW_TX = 32us ; FTW_RX = 32us + 0x7 + + + + + FREQ_COUNT_GO + Start the Frequency Meter + 28 + 1 + read-write + + + FREQ_COUNT_FINISHED + Frequency Meter has finished the Count Time + 29 + 1 + read-only + + + FREQ_COUNT_TIME + Frequency Meter Count Time + 30 + 2 + read-write + + + FREQ_COUNT_TIME_0 + 800 us + 0 + + + FREQ_COUNT_TIME_1 + 25 us + 0x1 + + + FREQ_COUNT_TIME_2 + 50 us + 0x2 + + + FREQ_COUNT_TIME_3 + 100 us + 0x3 + + + + + + + HPM_CTRL + PLL High Port Modulator Control + 0x1C + 32 + read-write + 0x840000 + 0xFFFFFFFF + + + HPM_SDM_IN_MANUAL + Manual High Port SDM Fractional value + 0 + 10 + read-write + + + HPM_CLK_CONFIG + HPM Clock Config + 12 + 1 + read-write + + + HPFF + HPM SDM Invalid Flag + 13 + 1 + read-write + oneToClear + + + HPM_SDM_OUT_INVERT + Invert HPM SDM Output + 14 + 1 + read-write + + + HPM_SDM_IN_DISABLE + Disable HPM SDM Input + 15 + 1 + read-write + + + HPM_LFSR_SIZE + HPM LFSR Length + 16 + 3 + read-write + + + HPM_LFSR_SIZE_0 + LFSR 9, tap mask 100010000 + 0 + + + HPM_LFSR_SIZE_1 + LFSR 10, tap mask 1001000000 + 0x1 + + + HPM_LFSR_SIZE_2 + LFSR 11, tap mask 11101000000 + 0x2 + + + HPM_LFSR_SIZE_3 + LFSR 13, tap mask 1101100000000 + 0x3 + + + HPM_LFSR_SIZE_4 + LFSR 15, tap mask 111010000000000 + 0x4 + + + HPM_LFSR_SIZE_5 + LFSR 17, tap mask 11110000000000000 + 0x5 + + + + + RX_HPM_CAL_EN + Receive HPM Calibration Enable + 19 + 1 + read-write + + + HPM_DTH_SCL + HPM Dither Scale + 20 + 1 + read-write + + + HPM_DTH_EN + Dither Enable for HPM LFSR + 23 + 1 + read-write + + + HPM_SCALE + High Port Modulation Scale + 24 + 3 + read-write + + + HPM_SCALE_0 + No Scaling + 0 + + + HPM_SCALE_1 + Divide by 2 + 0x1 + + + HPM_SCALE_2 + Multiply by 2 + 0x2 + + + HPM_SCALE_3 + Multiply by 4 + 0x3 + + + HPM_SCALE_4 + Divide by 4 + 0x4 + + + HPM_SCALE_5 + Multiply by 8 + 0x5 + + + HPM_SCALE_6 + Divide by 8 + 0x6 + + + HPM_SCALE_7 + N/A + 0x7 + + + + + HPM_INTEGER_INVERT + Invert High Port Modulation Integer + 27 + 1 + read-write + + + HPM_CAL_INVERT + Invert High Port Modulator Calibration + 28 + 1 + read-write + + + HPM_CAL_TIME + High Port Modulation Calibration Time + 29 + 2 + read-write + + + HPM_CAL_TIME_0 + 25 us + 0 + + + HPM_CAL_TIME_1 + 50 us + 0x1 + + + HPM_CAL_TIME_2 + 100 us + 0x2 + + + HPM_CAL_TIME_3 + N/A + 0x3 + + + + + HPM_MOD_IN_INVERT + Invert High Port Modulation + 31 + 1 + read-write + + + + + HPMCAL_CTRL + PLL High Port Calibration Control + 0x20 + 32 + read-write + 0x2221 + 0xFFFFFFFF + + + HPM_CAL_FACTOR + High Port Modulation Calibration Factor + 0 + 13 + read-only + + + HPM_CAL_ARRAY_SIZE + High Port Modulation Calibration Array Size + 13 + 1 + read-write + + + HPM_CAL_ARRAY_SIZE_0 + 128 + 0 + + + HPM_CAL_ARRAY_SIZE_1 + 256 + 0x1 + + + + + HPM_CAL_COUNT_SCALE + HPM_CAL_COUNT_SCALE + 14 + 1 + read-write + + + HP_CAL_DISABLE + Disable HPM Manual Calibration + 15 + 1 + read-write + + + HPM_CAL_FACTOR_MANUAL + Manual HPM Calibration Factor + 16 + 13 + read-write + + + HPM_CAL_SKIP + HPM_CAL_SKIP + 29 + 1 + read-write + + + HPM_CAL_BUMPED + HPM_CAL_BUMPED + 30 + 2 + read-write + + + HPM_CAL_BUMPED_0 + No calibration boost + 0 + + + HPM_CAL_BUMPED_1 + x2 + 0x1 + + + HPM_CAL_BUMPED_2 + x4 + 0x2 + + + HPM_CAL_BUMPED_3 + x8 + 0x3 + + + + + + + HPM_CAL1 + PLL High Port Calibration Result 1 + 0x24 + 32 + read-only + 0x44300000 + 0xFFFFFFFF + + + HPM_COUNT_1 + High Port Modulation Counter Value 1 + 0 + 19 + read-only + + + + + HPM_CAL2 + PLL High Port Calibration Result 2 + 0x28 + 32 + read-only + 0x2100000 + 0xFFFFFFFF + + + HPM_COUNT_2 + High Port Modulation Counter Value 2 + 0 + 19 + read-only + + + + + HPM_SDM_RES + PLL High Port Sigma Delta Results + 0x2C + 32 + read-write + 0x1000000 + 0xFFFFFFFF + + + HPM_NUM_SELECTED + High Port Modulator SDM Numerator + 0 + 10 + read-only + + + HPM_DENOM + High Port Modulator SDM Denominator + 16 + 10 + read-write + + + HPM_COUNT_ADJUST + HPM_COUNT_ADJUST + 28 + 4 + read-write + + + + + LPM_CTRL + PLL Low Port Modulator Control + 0x30 + 32 + read-write + 0x8000800 + 0xFFFFFFFF + + + PLL_LD_MANUAL + Manual PLL Loop Divider value + 0 + 5 + read-write + + + HPM_CAL_SCALE + High Port Calibration Word Scaling + 8 + 4 + read-write + + + HPM_CAL_SCALE_0 + No Scaling + 0 + + + HPM_CAL_SCALE_1 + No Scaling + 0x1 + + + HPM_CAL_SCALE_2 + No Scaling + 0x2 + + + HPM_CAL_SCALE_3 + Divide by 32 + 0x3 + + + HPM_CAL_SCALE_4 + Divide by 16 + 0x4 + + + HPM_CAL_SCALE_5 + Divide by 8 + 0x5 + + + HPM_CAL_SCALE_6 + Divide by 4 + 0x6 + + + HPM_CAL_SCALE_7 + Divide by 2 + 0x7 + + + HPM_CAL_SCALE_8 + No Scaling + 0x8 + + + HPM_CAL_SCALE_9 + Multiply by 2 + 0x9 + + + HPM_CAL_SCALE_10 + Multiply by 4 + 0xA + + + HPM_CAL_SCALE_11 + Multiply by 8 + 0xB + + + HPM_CAL_SCALE_12 + No Scaling + 0xC + + + HPM_CAL_SCALE_13 + No Scaling + 0xD + + + HPM_CAL_SCALE_14 + No Scaling + 0xE + + + HPM_CAL_SCALE_15 + No Scaling + 0xF + + + + + PLL_LD_DISABLE + Disable PLL Loop Divider + 12 + 1 + read-write + + + LPFF + LPM SDM Invalid Flag + 13 + 1 + read-write + oneToClear + + + LPM_SDM_INV + Invert LPM SDM + 14 + 1 + read-write + + + LPM_DISABLE + Disable LPM SDM + 15 + 1 + read-write + + + LPM_DTH_SCL + LPM Dither Scale + 16 + 4 + read-write + + + LPM_DTH_SCL_5 + -128 to 96 + 0x5 + + + LPM_DTH_SCL_6 + -256 to 192 + 0x6 + + + LPM_DTH_SCL_7 + -512 to 384 + 0x7 + + + LPM_DTH_SCL_8 + -1024 to 768 + 0x8 + + + LPM_DTH_SCL_9 + -2048 to 1536 + 0x9 + + + LPM_DTH_SCL_10 + -4096 to 3072 + 0xA + + + LPM_DTH_SCL_11 + -8192 to 6144 + 0xB + + + + + LPM_D_CTRL + LPM Dither Control in Override Mode + 22 + 1 + read-write + + + LPM_D_OVRD + LPM Dither Override Mode Select + 23 + 1 + read-write + + + LPM_SCALE + LPM Scale Factor + 24 + 4 + read-write + + + LPM_SCALE_0 + No Scaling + 0 + + + LPM_SCALE_1 + Multiply by 2 + 0x1 + + + LPM_SCALE_2 + Multiply by 4 + 0x2 + + + LPM_SCALE_3 + Multiply by 8 + 0x3 + + + LPM_SCALE_4 + Multiply by 16 + 0x4 + + + LPM_SCALE_5 + Multiply by 32 + 0x5 + + + LPM_SCALE_6 + Multiply by 64 + 0x6 + + + LPM_SCALE_7 + Multiply by 128 + 0x7 + + + LPM_SCALE_8 + Multiply by 256 + 0x8 + + + LPM_SCALE_9 + Multiply by 512 + 0x9 + + + LPM_SCALE_10 + Multiply by 1024 + 0xA + + + LPM_SCALE_11 + Multiply by 2048 + 0xB + + + + + LPM_SDM_USE_NEG + Use the Negedge of the Sigma Delta clock + 31 + 1 + read-write + + + + + LPM_SDM_CTRL1 + PLL Low Port Sigma Delta Control 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPM_INTG_SELECTED + Low Port Modulation Integer Value Selected + 0 + 7 + read-only + + + HPM_ARRAY_BIAS + Bias value for High Port DAC Array Midpoint + 8 + 7 + read-write + + + LPM_INTG + Manual Low Port Modulation Integer Value + 16 + 7 + read-write + + + SDM_MAP_DISABLE + Disable SDM Mapping + 31 + 1 + read-write + + + + + LPM_SDM_CTRL2 + PLL Low Port Sigma Delta Control 2 + 0x38 + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + LPM_NUM + Low Port Modulation Numerator + 0 + 28 + read-write + + + + + LPM_SDM_CTRL3 + PLL Low Port Sigma Delta Control 3 + 0x3C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + LPM_DENOM + Low Port Modulation Denominator + 0 + 28 + read-write + + + + + LPM_SDM_RES1 + PLL Low Port Sigma Delta Result 1 + 0x40 + 32 + read-only + 0xE200000 + 0xFFFFFFFF + + + LPM_NUM_SELECTED + Low Port Modulation Numerator Applied + 0 + 28 + read-only + + + + + LPM_SDM_RES2 + PLL Low Port Sigma Delta Result 2 + 0x44 + 32 + read-only + 0x4000000 + 0xFFFFFFFF + + + LPM_DENOM_SELECTED + Low Port Modulation Denominator Selected + 0 + 28 + read-only + + + + + DELAY_MATCH + PLL Delay Matching + 0x48 + 32 + read-write + 0x204 + 0xFFFFFFFF + + + LPM_SDM_DELAY + Low Port SDM Delay Matching + 0 + 4 + read-write + + + HPM_SDM_DELAY + High Port SDM Delay Matching + 8 + 4 + read-write + + + HPM_INTEGER_DELAY + High Port Integer Delay Matching + 16 + 4 + read-write + + + + + TUNING_CAP_TX_CTRL + Tuning Cap Settings in Transmit Mode + 0x4C + 32 + read-write + 0x6DB6DB + 0xFFFFFFFF + + + TUNING_RANGE_0 + Tuning Range 0 + 0 + 3 + read-write + + + TUNING_RANGE_1 + Tuning Range 1 + 3 + 3 + read-write + + + TUNING_RANGE_2 + Tuning Range 2 + 6 + 3 + read-write + + + TUNING_RANGE_3 + Tuning Range 3 + 9 + 3 + read-write + + + TUNING_RANGE_4 + Tuning Range 4 + 12 + 3 + read-write + + + TUNING_RANGE_5 + Tuning Range 5 + 15 + 3 + read-write + + + TUNING_RANGE_6 + Tuning Range 6 + 18 + 3 + read-write + + + TUNING_RANGE_7 + Tuning Range 7 + 21 + 3 + read-write + + + + + TUNING_CAP_RX_CTRL + Tuning Cap Settings in Receive Mode + 0x50 + 32 + read-write + 0x6DB6DB + 0xFFFFFFFF + + + TUNING_RANGE_0 + Tuning Range 0 + 0 + 3 + read-write + + + TUNING_RANGE_1 + Tuning Range 1 + 3 + 3 + read-write + + + TUNING_RANGE_2 + Tuning Range 2 + 6 + 3 + read-write + + + TUNING_RANGE_3 + Tuning Range 3 + 9 + 3 + read-write + + + TUNING_RANGE_4 + Tuning Range 4 + 12 + 3 + read-write + + + TUNING_RANGE_5 + Tuning Range 5 + 15 + 3 + read-write + + + TUNING_RANGE_6 + Tuning Range 6 + 18 + 3 + read-write + + + TUNING_RANGE_7 + Tuning Range 7 + 21 + 3 + read-write + + + + + MAX_TX_CFG1_FREQ + Max Transmit Frequency For TX Configuration 1 + 0x58 + 32 + read-write + 0xFFF + 0xFFFFFFFF + + + MAX_TX_CFG1_FREQ + Maximum Transmit Frequency for Standard TX Settings + 0 + 12 + read-write + + + + + CTUNE_CTRL + PLL Coarse Tune Control + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + CTUNE_TARGET_MANUAL + Manual Coarse Tune Target + 0 + 12 + read-write + + + CTUNE_CNTR_RLS_RST + Coarse Tune Counter Release Reset + 12 + 3 + read-write + + + CTUNE_TARGET_DISABLE + Disable Coarse Tune Target + 15 + 1 + read-write + + + CTUNE_ADJUST + Coarse Tune Count Adjustment + 16 + 4 + read-write + + + CTUNE_MANUAL + Manual Coarse Tune Setting + 20 + 8 + read-write + + + CTUNE_DISABLE + Coarse Tune Disable + 31 + 1 + read-write + + + + + DATA_RATE_OVRD_CTRL1 + PLL Data Rate Override Control + 0x60 + 32 + read-write + 0x188 + 0xFFFFFFFF + + + HPM_CAL_SCALE_CFG1 + HPM Scale Configuration1 + 0 + 4 + read-write + + + LPM_SCALE_CFG1 + LPM Scale Configuration1 + 4 + 4 + read-write + + + HPM_FDB_RES_CAL_CFG1 + HPM FDB RES Calibration Configuration1 + 8 + 2 + read-write + + + HPM_FDB_RES_TX_CFG1 + HPM FDB RES Transmit Configuration1 + 10 + 2 + read-write + + + + + DATA_RATE_OVRD_CTRL2 + PLL Data Rate Override Control + 0x64 + 32 + read-write + 0x180000 + 0xFFFFFFFF + + + NUM_OFFSET_CFG1 + Numerator Offset Configuration1 + 0 + 28 + read-write + + + + + CTUNE_RES + PLL Coarse Tune Results + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + CTUNE_SELECTED + Coarse Tune Setting to VCO + 0 + 8 + read-only + + + CTUNE_BEST_DIFF + Coarse Tune Absolute Best Difference + 10 + 8 + read-only + + + CTUNE_FREQ_SELECTED + Coarse Tune Frequency Selected + 18 + 12 + read-only + + + + + HPM_CAL_TIMING + PLL HPM Calibration Timing Attributes + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPM_CTUNE_SETTLE_TIME + CTUNE Settling Time + 0 + 4 + read-write + + + HPM_CAL1_SETTLE_TIME + HPM Calibration1 Settling Time + 4 + 4 + read-write + + + HPM_CAL2_SETTLE_TIME + HPM Calibration2 Settling Time + 8 + 4 + read-write + + + HPM_VCO_MOD_DELAY + HPM VCO Modification Output Delay + 16 + 16 + read-write + + + + + PLL_OFFSET_CTRL + PLL Offset Control + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PLL_NUMERATOR_OFFSET + PLL Numerator Offset + 0 + 28 + read-write + + + + + PLL_DATARATE_CTRL + PLL Data Rate Switch Control + 0xA8 + 32 + read-write + 0x6612 + 0xFFFFFFFF + + + HPM_VCM_TX_DRS + Data Rate Switch for hpm_vcm_tx + 0 + 3 + read-write + + + HPM_VCM_TX_DRS_0 + 432 mV + 0 + + + HPM_VCM_TX_DRS_1 + 328 mV + 0x1 + + + HPM_VCM_TX_DRS_2 + 456 mV + 0x2 + + + HPM_VCM_TX_DRS_3 + 473 mV + 0x3 + + + HPM_VCM_TX_DRS_4 + 488 mV + 0x4 + + + HPM_VCM_TX_DRS_5 + 408 mV + 0x5 + + + HPM_VCM_TX_DRS_6 + 392 mV + 0x6 + + + HPM_VCM_TX_DRS_7 + 376 mV + 0x7 + + + + + HPM_VCM_CAL_DRS + Data Rate Switch for hpm_vcm_cal + 4 + 3 + read-write + + + HPM_VCM_CAL_DRS_0 + 432 mV + 0 + + + HPM_VCM_CAL_DRS_1 + 328 mV + 0x1 + + + HPM_VCM_CAL_DRS_2 + 456 mV + 0x2 + + + HPM_VCM_CAL_DRS_3 + 473 mV + 0x3 + + + HPM_VCM_CAL_DRS_4 + 488 mV + 0x4 + + + HPM_VCM_CAL_DRS_5 + 408 mV + 0x5 + + + HPM_VCM_CAL_DRS_6 + 392 mV + 0x6 + + + HPM_VCM_CAL_DRS_7 + 376 mV + 0x7 + + + + + PLL_VCO_TRIM_KVM_TX_DRS + Data Rate Switch for pll_vco_trim_kvm_tx. + 8 + 3 + read-write + + + PLL_VCO_TRIM_KVM_TX_DRS_0 + 10MHz/V + 0 + + + PLL_VCO_TRIM_KVM_TX_DRS_4 + 20MHz/V + 0x4 + + + PLL_VCO_TRIM_KVM_TX_DRS_6 + 30MHz/V + 0x6 + + + PLL_VCO_TRIM_KVM_TX_DRS_7 + 40MHz/V + 0x7 + + + + + PLL_VCO_TRIM_KVM_CAL_DRS + Data Rate Switch for pll_vco_trim_kvm_cal + 12 + 3 + read-write + + + PLL_VCO_TRIM_KVM_CAL_DRS_0 + 10MHz/V + 0 + + + PLL_VCO_TRIM_KVM_CAL_DRS_4 + 20MHz/V + 0x4 + + + PLL_VCO_TRIM_KVM_CAL_DRS_6 + 30MHz/V + 0x6 + + + PLL_VCO_TRIM_KVM_CAL_DRS_7 + 40MHz/V + 0x7 + + + + + LPM_SDM_DELAY_DRS + DRS LPM_SDM_DELAY + 16 + 4 + read-write + + + HPM_SDM_DELAY_DRS + DRS HPM_SDM_DELAY + 20 + 4 + read-write + + + HPM_INTEGER_DELAY_DRS + DRS HPM_SDM_DELAY + 24 + 4 + read-write + + + + + + + XCVR_ZBDEMOD + XCVR_ZBDEMOD + XCVR_ZBDEMOD + 0x48A07500 + + 0 + 0x2C + registers + + + + CORR_CTRL + 802.15.4 DEMOD CORRELATOR CONTROL + 0 + 32 + read-write + 0x482 + 0xFFFFFFFF + + + CORR_VT + CORR_VT + 0 + 8 + read-write + + + CORR_NVAL + CORR_NVAL + 8 + 3 + read-write + + + MAX_CORR_EN + MAX_CORR_EN + 11 + 1 + read-write + + + ZBDEM_CLK_ON + Force 802.15.4 Demodulator Clock On + 15 + 1 + read-write + + + ZBDEM_CLK_ON_0 + Normal Operation + 0 + + + ZBDEM_CLK_ON_1 + Force 802.15.4 Demodulator Clock On (debug purposes only) + 0x1 + + + + + RX_MAX_CORR + RX_MAX_CORR + 16 + 8 + read-only + + + RX_MAX_PREAMBLE + RX_MAX_PREAMBLE + 24 + 8 + read-only + + + + + PN_TYPE + 802.15.4 DEMOD PN TYPE + 0x4 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PN_TYPE + PN_TYPE + 0 + 1 + read-write + + + TX_INV + TX_INV + 1 + 1 + read-write + + + + + PN_CODE + 802.15.4 DEMOD PN CODE + 0x8 + 32 + read-write + 0x744AC39B + 0xFFFFFFFF + + + PN_LSB + PN_LSB + 0 + 16 + read-write + + + PN_MSB + PN_MSB + 16 + 16 + read-write + + + + + SYNC_CTRL + 802.15.4 DEMOD SYMBOL SYNC CONTROL + 0xC + 32 + read-write + 0x8 + 0xFFFFFFFF + + + SYNC_PER + Symbol Sync Tracking Period + 0 + 3 + read-write + + + TRACK_ENABLE + TRACK_ENABLE + 3 + 1 + read-write + + + TRACK_ENABLE_0 + symbol timing synchronization tracking disabled in Rx frontend + 0 + + + TRACK_ENABLE_1 + symbol timing synchronization tracking enabled in Rx frontend (default) + 0x1 + + + + + + + CCA_LQI_SRC + 802.15.4 CCA/LQI SOURCE + 0x10 + 32 + read-write + 0xC + 0xFFFFFFFF + + + CCA1_FROM_RX_DIG + Selects the Source of CCA1 (Clear Channel Assessment Mode 1) Information Provided to the 802.15.4 Link Layer + 0 + 1 + read-write + + + CCA1_FROM_RX_DIG_0 + Use the CCA1 information computed internally in the 802.15.4 Demod + 0 + + + CCA1_FROM_RX_DIG_1 + Use the CCA1 information computed by the RX Digital + 0x1 + + + + + LQI_FROM_RX_DIG + Selects the Source of LQI (Link Quality Indicator) Information Provided to the 802.15.4 Link Layer + 1 + 1 + read-write + + + LQI_FROM_RX_DIG_0 + Use the LQI information computed internally in the 802.15.4 Demod + 0 + + + LQI_FROM_RX_DIG_1 + Use the LQI information computed by the RX Digital + 0x1 + + + + + LQI_START_AT_SFD + Select Start Point for LQI Computation + 2 + 1 + read-write + + + LQI_START_AT_SFD_0 + Start LQI computation at Preamble Detection (similar to previous NXP 802.15.4 products) + 0 + + + LQI_START_AT_SFD_1 + Start LQI computation at SFD (Start of Frame Delimiter) Detection + 0x1 + + + + + ZBDEM_CCA_CLK_ON + 802.15.4 Demodulator CCA Clock Enable + 3 + 1 + read-write + + + + + FAD_LPPS_THR + FAD CORRELATOR THRESHOLD + 0x14 + 32 + read-write + 0x60606082 + 0xFFFFFFFF + + + FAD_THR + FAD_THR + 0 + 8 + read-write + + + FAD_FILL1 + Pre-detection buffer filling duration + 8 + 7 + read-write + + + LPPS_FILL_COUNT + Wait duration after lpps_lp_enable is de-asserted + 16 + 7 + read-write + + + LPPS_LP_EN_COUNT + LPPS_LP_EN high time + 24 + 7 + read-write + + + + + ZBDEM_AFC + 802.15.4 AFC STATUS + 0x18 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + AFC_EN + AFC_EN + 0 + 1 + read-write + + + AFC_EN_0 + AFC is disabled + 0 + + + AFC_EN_1 + AFC is enabled + 0x1 + + + + + DCD_EN + DCD_EN + 1 + 1 + read-write + + + DCD_EN_0 + NCD Mode (default) + 0 + + + DCD_EN_1 + DCD Mode + 0x1 + + + + + AFC_OUT + AFC_OUT + 8 + 5 + read-only + + + + + CCA2_CTRL + CCA MODE 2 CONTROL REGISTER + 0x1C + 32 + read-write + 0xFF05 + 0xFFFFFFFF + + + CCA2_INTERVAL + CCA Mode 2 Measurement Window Duration + 0 + 2 + read-write + + + CCA2_INTERVAL_0 + 64 us + 0 + + + CCA2_INTERVAL_1 + 128 us + 0x1 + + + CCA2_INTERVAL_2 + 256 us + 0x2 + + + CCA2_INTERVAL_3 + 512 us + 0x3 + + + + + USE_DEMOD_CCA2 + Selects CCA Mode 2 Computation Engine + 2 + 1 + read-write + + + USE_DEMOD_CCA2_0 + Use standalone (new) CCA Mode 2 Engine, decoupled from demodulator + 0 + + + USE_DEMOD_CCA2_1 + Use 802.15.4 demodulator-based (legacy) CCA Mode 2 Engine (default) + 0x1 + + + + + CCA2_REF_SEQ + CCA Mode 2 Sequence Address + 8 + 8 + read-write + + + + + CCA2_THRESH + CCA MODE 2 CONTROL REGISTER + 0x20 + 32 + read-write + 0x400080 + 0xFFFFFFFF + + + CCA2_CNT_THRESH + CCA Mode 2 Count Threshold + 0 + 10 + read-write + + + CCA2_SYM_THRESH + CCA Mode 2 Symbol Threshold + 16 + 10 + read-write + + + + + CCA2_STATUS + CCA MODE 2 STATUS REGISTER + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CCA2_CNT_MAX + CCA Mode 2 Maximum Count + 0 + 10 + read-only + + + CCA2_COMPLETE + CCA Mode 2 Measurement Complete + 10 + 1 + read-only + + + CCA2_CHANNEL_STATE + CCA Mode 2 Channel State + 11 + 1 + read-only + + + CCA2_CNT_SYM + CCA Mode 2 Repetition Sequence Addresses Count + 16 + 10 + read-only + + + + + CORR_CTRL2 + 802.15.4 DEMOD CORRELATOR CONTROL2 + 0x28 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + EARLY_PD_THRESH + EARLY_PD_THRESH + 0 + 8 + read-write + + + + + + + XCVR_2P4GHZ_PHY + 2.4GHz PHY REGISTERS + GEN4PHY + 0x48A07600 + + 0 + 0x200 + registers + + + + FSK_PD_CFG0 + PHY Uncoded Preamble Detect Config 0 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PREAMBLE_T_SCALE + Scaling factor used for fractional time estimation during preamble search. + 0 + 4 + read-write + + + PD_IIR_ALPHA + Forgetting factor used by the complex correlations smoothing leaky integrator. + 8 + 8 + read-write + + + + + FSK_PD_CFG1 + PHY Uncoded Preamble Detect Config 1 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PREAMBLE_PATTERN + 8-bit preamble pattern used in FM-domain preamble detector. + 0 + 8 + read-write + + + + + FSK_PD_CFG2 + PHY Uncoded Preamble Detect Config 2 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PD_THRESH_ACQ_1_3_1M + Preamble detect threshold for acq mode 1 and 3 at data rate 1Mbps + 0 + 8 + read-write + + + PD_THRESH_ACQ_1_3_2M + Preamble detect threshold for acq mode 1 and 3 at data rate 2Mbps + 16 + 8 + read-write + + + + + 2 + 0x4 + FSK_PD_PH[%s] + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + REF0 + Uncoded preamble reference waveform sample 0 (sfix6en5) + 0 + 6 + read-write + + + REF1 + Uncoded preamble reference waveform sample 1 (sfix6en5) + 8 + 6 + read-write + + + REF2 + Uncoded preamble reference waveform sample 2 (sfix6en5) + 16 + 6 + read-write + + + REF3 + Uncoded preamble reference waveform sample 3 (sfix6en5) + 24 + 6 + read-write + + + + + 4 + 0x4 + 2,3,4,5 + FSK_PD_RO_PH%s + no description available + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + REF0 + Uncoded preamble reference waveform sample 16 (sfix6en5) + 0 + 6 + read-only + + + REF1 + Uncoded preamble reference waveform sample 17 (sfix6en5) + 8 + 6 + read-only + + + REF2 + Uncoded preamble reference waveform sample 18 (sfix6en5) + 16 + 6 + read-only + + + REF3 + Uncoded preamble reference waveform sample 19 (sfix6en5) + 24 + 6 + read-only + + + + + FSK_CFG0 + PHY Uncoded Config 0 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + AA_OUT_SEL + Specifies which AA bits to be played-back to the LL: + 1 + 1 + read-write + + + A0 + output the received AA bits + 0 + + + A1 + output the programmed AA bits + 0x1 + + + + + FSK_BIT_INVERT + This applies at the demodulator, so it affects both AA and the data portions of the packet. + 2 + 1 + read-write + + + A0 + Normal demodulation + 0 + + + A1 + Invert demodulated bits + 0x1 + + + + + MSK_EN + Configures PHY for MSK decoding. + 5 + 1 + read-write + + + MSK2FSK_SEED + Last bit of preamble. + 6 + 1 + read-write + + + AA_ACQ_1_2_3_THRESH_1M + For 1Mbps data rate, Correlation threshold applicable to AA detection; uses ufix5_En5 fixed-point format. + 8 + 5 + read-write + + + HAMMING_AA_LOW_PWR + Maximum hamming distance from the given AA pattern that may still be accepted as a match; valid range [0,7]. This threshold value are performed on lower power case. + 16 + 4 + read-write + + + BLE_NTW_ADR_THR + Maximum hamming distance from the given AA pattern that may still be accepted as a match; valid range [0,7]. This threshold value are performed on lower power case. + 20 + 3 + read-write + + + AA_ACQ_1_2_3_THRESH_2M + For 2Mbps data rate, correlation threshold applicable to AA detection; uses ufix5_En5 fixed-point format. + 24 + 5 + read-write + + + + + FSK_CFG1 + PHY Uncoded Config 1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + OVERH + Modulation index; represented in ufix9_En6 format. + 0 + 9 + read-write + + + OVERH_INV + Reciprocal of modulation index; represented in ufix9_En7 format. + 11 + 9 + read-write + + + SYNCTSCALE + Scaling factor used for fractional time estimation during AA search; represented in ufix4_En3 format. + 24 + 4 + read-write + + + + + FSK_CFG2 + PHY Uncoded Config 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAG_WIN + Indicates the forgetting factor used in received signal level measurement; + 28 + 4 + read-write + + + + + FSK_PT + PHY Uncoded Power Threshold Config + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + AGC_TIMEOUT + Time-out, applicable to special conditioning of signal power detection in the Power threshold block, after each AGC gain adjustment. It is expressed in number of samples. + 0 + 16 + read-write + + + COND_SIG_PRST_EN + Enables special conditioning of signal detection; + 16 + 1 + read-write + + + A0 + disable. + 0 + + + A1 + enable. + 0x1 + + + + + COND_AA_BUFF_EN + Enables special condition for enabling AA detector buffer; + 17 + 1 + read-write + + + A0 + disable. + 0 + + + A1 + enable. + 0x1 + + + + + BYPASS_WITH_RSSI + Bypass signal power measurement with RSSI measurement; + 18 + 1 + read-write + + + A0 + no + 0 + + + A1 + yes + 0x1 + + + + + + + FSK_FAD_CTRL + PHY Uncoded FAD Control + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FAD_EN + Enables FAD; + 0 + 1 + read-write + + + A0 + disable. + 0 + + + A1 + enable. + 0x1 + + + + + + + FSK_FAD_CFG + PHY Uncoded FAD Config + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + WIN_FAD_WAIT_SYNCH + Time-window to wait for clean samples, before transitioning to AA search PHY state, if PD was found after antenna switch (refered to as T3 in the PHY state-machine section). + 0 + 7 + read-write + + + WIN_FAD_WAIT_PD + Time-window to wait for clean samples if PD was not found after antenna switch (refered to as T2 in the PHY state-machine section). + 8 + 7 + read-write + + + WIN_FAD_SEARCH_PD + Time-window to match preamble pattern on samples coming from the previously selected antenna (refered to as T1 in the PHY state-machine section). + 16 + 7 + read-write + + + WIN_SEARCH_PD + Time-window to match preamble pattern on samples coming from the currently selected antenna (refered to as T0 in the PHY state-machine section). + 24 + 7 + read-write + + + + + FSK_STAT + PHY Uncoded Status + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + AA_FOUND + Indicates that a uncoded AA detect is active. + 2 + 1 + read-only + + + AA_MATCH + Indicates which non-coded AA has matched. This will clear when the PHY is re-initialized. + 4 + 4 + read-only + + + HAMM_DIST + Indicates the hamming distance witnessed when AA match occurred. + 8 + 7 + read-only + + + CORR_MAX + Indicates the correlation witnessed when AA match occurred + 16 + 5 + read-only + + + TOF_OFF + Timing offset for use in time-of-flight calculation. + 28 + 4 + read-only + + + + + LR_PD_CFG + PHY Long Range Preamble Detect Config + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORR_TH + Correlation threshold applicable to preamble detection; uses (0,8,8) fixed-point format. + 0 + 8 + read-write + + + FREQ_TH + Threshold used to compare CFO estimates in the LR preamble detector; uses ufix5_En5 format. + 8 + 5 + read-write + + + NO_PEAKS + Number of consecutive correlation values that have to exceed the PD correlation threshold,for the same preamble phase, to assert preamble found; + 16 + 2 + read-write + + + A0 + 2 peaks; + 0 + + + A1 + 3 peaks; + 0x1 + + + A2 + 4 peaks; + 0x2 + + + A3 + 5 peaks; + 0x3 + + + + + + + 4 + 0x4 + LR_PD_PH[%s] + no description available + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + REF0 + Long range preamble reference waveform sample 0 (sfix6en5) + 0 + 6 + read-write + + + REF1 + Long range preamble reference waveform sample 1 (sfix6en5) + 8 + 6 + read-write + + + REF2 + Long range preamble reference waveform sample 2 (sfix6en5) + 16 + 6 + read-write + + + REF3 + Long range preamble reference waveform sample 3 (sfix6en5) + 24 + 6 + read-write + + + + + 13 + 0x4 + 4,5,6,7,8,9,10,11,12,13,14,15,16 + LR_PD_RO_PH%s + no description available + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + REF0 + Long range preamble reference waveform sample 16 (sfix6en5) + 0 + 6 + read-only + + + REF1 + Long range preamble reference waveform sample 17 (sfix6en5) + 8 + 6 + read-only + + + REF2 + Long range preamble reference waveform sample 18 (sfix6en5) + 16 + 6 + read-only + + + REF3 + Long range preamble reference waveform sample 19 (sfix6en5) + 24 + 6 + read-only + + + + + LR_AA_CFG + PHY Long Range AA Config + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + AA_COR_THRESH + Threshold use to compare the correlation magnitude in the long-range AA correlator. + 0 + 8 + read-write + + + AA_HAM_THRESH + Threshold use to compare the Hamming distance, between reference coded sequence and received coded sequence, in the long-range AA correlator. + 8 + 6 + read-write + + + ACCESS_ADDR_HAM + Threshold use to compare the Hamming distance, between the reference AA sequence and the received Viterbi decoded AA sequence. + 16 + 5 + read-write + + + AA_LR_CORR_GAIN + AA correlator gain. Format ufix6en3. This gain is applied to soft bits from the demodulator before they are used for address search synchronization. + 24 + 6 + read-write + + + + + LR_STAT + PHY Long Range Status + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + DECODED_HAMM_DIST + Hamming distance between the reference sequence and the Viterbi decoded received sequence + 0 + 6 + read-only + + + AA_FOUND + Indicates that a AA detect is active for both LR and uncoded. + 6 + 1 + read-only + + + CI + CI received. + 7 + 1 + read-only + + + CODED_HAMM_DIST + Hamming distance between the coded reference sequence and the coded received sequence. + 8 + 7 + read-only + + + AA_CORR_MAX + Indicates the AA correlation magnitude witnessed when AA match occurred + 16 + 8 + read-only + + + CMAG_MAX + Indicates the maximum preamble correlation magnitude during preamble found + 24 + 8 + read-only + + + + + SM_CFG + PHY State Machine Config + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACQ_MODE + Acquisition mode for non-coded reception + 0 + 2 + read-write + + + A1 + Use preamble and verify a correlation peak, the synch at the symbol rate as symbol timing is established by the preamble acquisition + 0x1 + + + A2 + Use synch only (which may incorporate part of the preamble) + 0x2 + + + A3 + Use mainly the sync detection: Use a low threshold on the preamble detector and launch the synch detection only if the preamble has shown a recent peak + 0x3 + + + + + EN_PHY_SM_EXT_RST + Enable PHY state-machine reset on the external reset port; Reserved, should keep 0. + 2 + 1 + read-write + + + A0 + Reset is not allowed. + 0 + + + A1 + Reset is allowed. + 0x1 + + + + + AGC_FRZ_ON_PD_FOUND_ACQ1_LR + Specfies AGC freeze condition for non-coded acq.1 and Bluetooth LE long range. + 3 + 1 + read-write + + + A1 + AGC freeze on AA found. + 0 + + + A0 + AGC freeze asserted on PD found. + 0x1 + + + + + PH_BUFF_PTR_SYM + Phase buffer size to demodulator, long range only. + 4 + 2 + read-write + + + EARLY_PD_TIMEOUT + Time-out used to reset the AGC state-machine for the eventuality that an "PD found early" event occurs but it is not followed by an "PD found" event + 8 + 6 + read-write + + + AA_TIMEOUT_UNCODED + Time-out value for access address search for uncoded packets + 16 + 10 + read-write + + + + + MISC + PHY Misc Config + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSSI_CORR_TH + Threshold use to compare a correlation magnitude value, computed in the acquisition block, in order to determine the correlation flag value provided by the PHY to the LQI computation block. Format is ufix8_En8 + 0 + 8 + read-write + + + DMA_PAGE_SEL + Select which DMA page is send out + 8 + 3 + read-write + + + A0 + Select DMA PAGE 0 for M3C with cfo; + 0 + + + A1 + Select DMA PAGE 1 for M3C with magnitude; + 0x1 + + + A2 + Select DMA PAGE 2 for un-coded; + 0x2 + + + A3 + Select DMA PAGE 3 for Long Range Preampble Detect; + 0x3 + + + A4 + Select DMA PAGE 4 for Long Range AA Detect; + 0x4 + + + + + ECO1_RSVD + Reserved. Must be programed as reset value 0. + 11 + 5 + read-write + + + PHY_CLK_CTRL + Enables various clock gating features. Bits are individually decoded, so any combination is allowable. + 16 + 10 + read-write + + + ECO2_RSVD + Reserved + 26 + 4 + read-write + + + DTEST_MUX_EN + Reserved. Should be programed as reset value 0. + 30 + 1 + read-write + + + PHY_CLK_ON + Force PHY clock ON + 31 + 1 + read-write + + + + + STAT0 + PHY Status 0 + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PD_FOUND + PD_FOUND for LR or uncoded + 0 + 1 + read-only + + + LR_DET_FLAG + Indicates Bluetooth LE long range was detected + 1 + 1 + read-only + + + AA_MATCHED + Indicates AA was matched for LR or uncoded + 2 + 1 + read-only + + + AA_FOUND_ID + Indicates which AA was matched for LR and uncode + 3 + 3 + read-only + + + A0 + uncoded address 0 matched + 0 + + + A1 + uncoded address 1 matched + 0x1 + + + A2 + uncoded address 2 matched + 0x2 + + + A3 + uncoded address 3 matched + 0x3 + + + A4 + long range address matched + 0x4 + + + + + DATA_RATE + Indicates the data rate of received bit + 6 + 2 + read-only + + + A0 + 1Mbps + 0 + + + A1 + 2Mbps + 0x1 + + + A2 + 125kbps + 0x2 + + + A3 + 500kbps + 0x3 + + + + + FRAC + Indicates the fractional timing estimate determined in the acquisition block. Format is sfix6_en5(sign extend from sfix3_En2). + 8 + 6 + read-only + + + CFO_EST + Indicates the currently estimated CFO. Format is sfix10_en9(sign extend form sfix8_en9) + 16 + 10 + read-only + + + + + STAT1 + PHY Status 1 + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + AA_BITS + AA bits either received or programed + 0 + 32 + read-only + + + + + STAT2 + PHY Status 2 + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CNT_ANT_SW + Count of uncoded ANT switch event when FAD was enabled. + 0 + 2 + read-only + + + CNT_UNCAA_TIMEOUT + Count of uncoded AA search timeout event + 2 + 2 + read-only + + + CNT_LRAA_TIMEOUT + Count of lang range AA search timeout event + 4 + 2 + read-only + + + CNT_AACI_TIMEOUT + Count of long range AACI detect timeout event + 6 + 2 + read-only + + + CNT_AGC_RST + Count of AGC soft reset event + 8 + 2 + read-only + + + + + PREPHY_MISC + PHY PrePHY Misc Config + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFF_PTR_LR + Pointer to the PrePHY IQ buffer for the reception of the long-range packets. + 0 + 5 + read-write + + + BUFF_PTR_GFSK + Pointer to the PrePHY IQ buffer for the reception of the uncoded packets. + 8 + 5 + read-write + + + + + DMD_CTRL0 + PHY Demodulator Control 0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + TED_ACT_WIN + Active window size for the time tracking mechanism, expressed in symbols. + 0 + 2 + read-write + + + FED_ACT_WIN + Active window size for the frequency tracking mechanism, expressed in symbols. + 8 + 2 + read-write + + + DREP_SCALE_FREQ + Frequency domain signal scaling factor used by the de-repeater. + 16 + 4 + read-write + + + REPEAT_FACTOR + Repetition factor used by the de-repeater. + 20 + 3 + read-write + + + FED_ERR_SCALE + Scaling factor used by the freqency tracking loop. + 23 + 3 + read-write + + + TERR_TRK_EN + Enables time tracking in the demodulator. + 26 + 1 + read-write + + + FERR_TRK_EN + Enables frequency tracking in the demodulator. + 27 + 1 + read-write + + + DREP_SINE_EN + Flag used to enable the non-linear operation in the de-repeater. + 28 + 1 + read-write + + + DEMOD_MOD + Determines the number of taps used by the demodulator correlators; + 29 + 2 + read-write + + + A0 + use 12 taps + 0 + + + A1 + use 4 taps + 0x1 + + + A2 + use 7 taps + 0x2 + + + A3 + use 13 taps + 0x3 + + + + + + + DMD_CTRL1 + PHY Dmodulator Control 1 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FED_IDLE_WIN + Idle window size for the frequency tracking mechanism, expressed in symbols. + 0 + 10 + read-write + + + TED_ERR_SCALE + Scaling factor used by the time tracking loop. + 10 + 4 + read-write + + + FED_IMM_MEAS_EN + Specifies whether the frequency tracking starts with an active window; + 15 + 1 + read-write + + + A0 + start with idle window + 0 + + + A1 + start with active window + 0x1 + + + + + TED_IDLE_WIN + Idle window size for the time tracking mechanism, expressed in symbols. + 16 + 10 + read-write + + + TTRK_INT_RANGE + Timing error correction interpolation range, expressed in samples. The value must equal or bigger than 1. + 26 + 4 + read-write + + + TED_IMM_MEAS_EN + Specifies whether the time tracking starts with an active window; + 31 + 1 + read-write + + + A0 + start with idle window + 0 + + + A1 + start with active window + 0x1 + + + + + + + DMD_CTRL2 + PHY Demodulator Control 2 + 0xB4 + 32 + read-write + 0x111 + 0xFFFFFFFF + + + WAIT_DMD_LR_ADJ + Reserved. Must be programed as reset value 1. + 0 + 4 + read-write + + + WAIT_VIA_AFTER_AA_ADJ + Reserved. Must be programed as reset value 1. + 4 + 4 + read-write + + + WAIT_DMD_CLKEN_ADJ + Reserved. Must be programed as reset value 1. + 8 + 4 + read-write + + + + + 8 + 0xC + DEMOD_WAVE[%s] + no description available + 0xB8 + + DMD_WAVE_REG0 + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 0 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 0 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 0 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 0 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 0 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE_REG1 + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 0 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 0 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 0 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 0 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 0 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE_REG2 + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 0 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 0 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 0 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + + DMDAA_CTRL + PHY Demodulator Based SFD Confirmation control register. + 0x164 + 32 + read-write + 0x9 + 0xFFFFFFFF + + + DMDAA_HAMM_LP + Maximum hamming distance from the given AA pattern that may still be accepted as a match in low power case; valid range [0,7]. + 0 + 3 + read-write + + + DMDAA_HAMM_HP + Maximum hamming distance from the given AA pattern that may still be accepted as a match in high power case; valid range [0,7]. + 3 + 3 + read-write + + + HIPOW_DIS_OVRD + Override the feature: disable DMDAA when power sensitivity is higher; + 6 + 1 + read-write + + + A0 + disable override, DMDAA disabled when power is high + 0 + + + A1 + enable override, DMDAA enabled when power is high + 0x1 + + + + + DMDAA_EN + Enables Demodulator Based SFD Confirmation; + 7 + 1 + read-write + + + A0 + disable + 0 + + + A1 + enable + 0x1 + + + + + + + RTT_STAT + High resolution Time-Of-Flight calculation Status. + 0x168 + 32 + read-only + 0x54010001 + 0xFFFFFFFF + + + RTT_CFO + The high accuracy CFO computed by the HARTT block through the CORDIC algorithm. + 0 + 16 + read-only + + + RTT_P_DELTA + Difference between the squared correlation magnitude values, pm-pp provided by the HARTT block, format is sfix10En9. + 16 + 10 + read-only + + + RTT_DIST_SAT + Computed Hamming distance saturated to 2 bits, format is ufix2. + 26 + 2 + read-only + + + RTT_INT_ADJ + An integer adjustment of the timing which takes a value different of 0 when the early-late mechanism in the HARTT block chooses a peak different of the one chosen in the acquisition module (possible values are {-1,0,+1}). + 28 + 2 + read-only + + + RTT_FOUND + Flag that indicates that the HARTT operation is done and a valid PN pattern was detected. + 30 + 1 + read-only + + + + + RTT_CTRL + PHY RTT control register. + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + HA_RTT_THRESHOLD + threshold used to validate a HA RTT result. + 0 + 9 + read-write + + + FIRST_PDU_BIT + is programmed by software - used for regular packets high accuracy RTT; + 12 + 1 + read-write + + + RTT_SEQ_LEN + can be either 32 (when 0) or 64 bits (when 1) depending on the RTT configuration; + 13 + 1 + read-write + + + OVERRD_PROGR_AA + Enables overriding the programmed AA bits with the PN sequence used by RTT; + 14 + 1 + read-write + + + EN_HIGH_ACC_RTT + enables the use of the HA RTT block; + 15 + 1 + read-write + + + + + RTT_REF + PHY RTT reference register. + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + FM_REF_010 + Contextual values used to derive the FM reference ha_rtt_threshold . + 0 + 8 + read-write + + + FM_REF_110 + Contextual values used to derive the FM reference ha_rtt_threshold . + 8 + 8 + read-write + + + FM_REF_111 + Contextual values used to derive the FM reference ha_rtt_threshold . + 16 + 8 + read-write + + + + + + + XCVR_TSM + XCVR_TSM + XCVR_TSM + 0x48A07800 + + 0 + 0x400 + registers + + + + CTRL + TSM CONTROL + 0 + 32 + read-write + 0xFF000400 + 0xFFFFFFFF + + + TSM_SOFT_RESET + TSM Soft Reset + 1 + 1 + read-write + + + TSM_SOFT_RESET_0 + TSM Soft Reset removed. Normal operation. + 0 + + + TSM_SOFT_RESET_1 + TSM Soft Reset engaged. TSM forced to IDLE, and holds there until the bit is cleared. + 0x1 + + + + + FORCE_TX_EN + Force Transmit Enable + 2 + 1 + read-write + + + FORCE_TX_EN_0 + TSM Idle + 0 + + + FORCE_TX_EN_1 + TSM executes a TX sequence + 0x1 + + + + + FORCE_RX_EN + Force Receive Enable + 3 + 1 + read-write + + + FORCE_RX_EN_0 + TSM Idle + 0 + + + FORCE_RX_EN_1 + TSM executes a RX sequence + 0x1 + + + + + TX_ABORT_DIS + Transmit Abort Disable + 4 + 1 + read-write + + + RX_ABORT_DIS + Receive Abort Disable + 5 + 1 + read-write + + + ABORT_ON_CTUNE + Abort On Coarse Tune Lock Detect Failure + 6 + 1 + read-write + + + ABORT_ON_CTUNE_0 + don't allow TSM abort on Coarse Tune Unlock Detect + 0 + + + ABORT_ON_CTUNE_1 + allow TSM abort on Coarse Tune Unlock Detect + 0x1 + + + + + ABORT_ON_FREQ_TARG + Abort On Frequency Target Lock Detect Failure + 7 + 1 + read-write + + + ABORT_ON_FREQ_TARG_0 + don't allow TSM abort on Frequency Target Unlock Detect + 0 + + + ABORT_ON_FREQ_TARG_1 + allow TSM abort on Frequency Target Unlock Detect + 0x1 + + + + + TSM_IRQ0_EN + TSM_IRQ0 Enable/Disable bit + 8 + 1 + read-write + + + TSM_IRQ0_EN_0 + TSM_IRQ0 is disabled + 0 + + + TSM_IRQ0_EN_1 + TSM_IRQ0 is enabled + 0x1 + + + + + TSM_IRQ1_EN + TSM_IRQ1 Enable/Disable bit + 9 + 1 + read-write + + + TSM_IRQ1_EN_0 + TSM_IRQ1 is disabled + 0 + + + TSM_IRQ1_EN_1 + TSM_IRQ1 is enabled + 0x1 + + + + + PLL_UNLOCK_IRQ_EN + PLL Unlock Interrupt Enable + 10 + 1 + read-write + + + PLL_UNLOCK_IRQ_EN_0 + allows PLL unlock event to generate an interrupt + 0 + + + PLL_UNLOCK_IRQ_EN_1 + A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but an interrupt is not generated + 0x1 + + + + + PLL_UNLOCK_IRQ + PLL Unlock IRQ + 11 + 1 + read-write + oneToClear + + + PLL_UNLOCK_IRQ_0 + A PLL Unlock Interrupt has not occurred + 0 + + + PLL_UNLOCK_IRQ_1 + A PLL Unlock Interrupt has occurred + 0x1 + + + + + TSM_LL_INHIBIT + TSM Per-Link-Layer Inhibit + 12 + 4 + read-write + + + TSM_SPARE1_EXTEND + TSM RF_ACTIVE Extension Duration + 16 + 8 + read-write + + + BKPT + TSM Breakpoint + 24 + 8 + read-write + + + + + LPPS_CTRL + TSM CONTROL + 0x4 + 32 + read-write + 0xFFFF0000 + 0xFFFFFFFF + + + LPPS_LNA_MIX_ALLOW + LPPS_LNA_MIX_ALLOW + 1 + 1 + read-write + + + LPPS_CBPF_ALLOW + LPPS_CBPF_ALLOW + 2 + 1 + read-write + + + LPPS_ADC_ALLOW + LPPS_ADC_ALLOW + 3 + 1 + read-write + + + LPPS_LO_RX_ALLOW + LPPS_LO_RX_ALLOW + 4 + 1 + read-write + + + LPPS_LO_RXDRV_ALLOW + LPPS_LO_RXDRV_ALLOW + 5 + 1 + read-write + + + LPPS_RX_DIG_ALLOW + LPPS_RX_DIG_ALLOW + 6 + 1 + read-write + + + LPPS_RX_PHY_ALLOW + LPPS_RX_PHY_ALLOW + 7 + 1 + read-write + + + LPPS_START_RX + LPPS Fast TSM RX Warmup "Jump-from" Point + 16 + 8 + read-write + + + LPPS_DEST_RX + LPPS Fast TSM RX Warmup "Jump-to" Point + 24 + 8 + read-write + + + + + END_OF_SEQ + TSM END OF SEQUENCE + 0x8 + 32 + read-write + 0x5C5A7270 + 0xFFFFFFFF + + + END_OF_TX_WU + End of TX Warmup + 0 + 8 + read-write + + + END_OF_TX_WD + End of TX Warmdown + 8 + 8 + read-write + + + END_OF_RX_WU + End of RX Warmup + 16 + 8 + read-write + + + END_OF_RX_WD + End of RX Warmdown + 24 + 8 + read-write + + + + + WU_LATENCY + WARMUP LATENCY + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATAPATH_LATENCY + TX Datapath Latency + 0 + 8 + read-write + + + RX_SETTLING_LATENCY + RX Settling Latency + 16 + 8 + read-write + + + + + RECYCLE_COUNT + TSM RECYCLE COUNT + 0x10 + 32 + read-write + 0x2A1258 + 0xFFFFFFFF + + + RECYCLE_COUNT0 + TSM RX Recycle Count 0 + 0 + 8 + read-write + + + RECYCLE_COUNT1 + TSM RX Recycle Count 1 + 8 + 8 + read-write + + + RECYCLE_COUNT2 + TSM RX Recycle Count 2 + 16 + 8 + read-write + + + + + FAST_CTRL1 + TSM FAST WARMUP CONTROL 1 + 0x14 + 32 + read-write + 0xFF00 + 0xFFFFFFFF + + + FAST_TX_WU_EN + Fast TSM TX Warmup Enable + 0 + 1 + read-write + + + FAST_TX_WU_EN_0 + Fast TSM TX Warmups are disabled + 0 + + + FAST_TX_WU_EN_1 + Fast TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for Bluetooth LE mode, the RF channel is not an advertising channel. + 0x1 + + + + + FAST_RX_WU_EN + Fast TSM RX Warmup Enable + 1 + 1 + read-write + + + FAST_RX_WU_EN_0 + Fast TSM RX Warmups are disabled + 0 + + + FAST_RX_WU_EN_1 + Fast TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for Bluetooth LE mode, the RF channel is not an advertising channel. + 0x1 + + + + + FAST_RX2TX_EN + Fast TSM RX-to-TX Transition Enable + 2 + 1 + read-write + + + FAST_RX2TX_EN_0 + Disable Fast RX-to-TX transitions + 0 + + + FAST_RX2TX_EN_1 + Enable Fast RX-to-TX transitions (if fast_rx2tx_wu is asserted by the Link Layer) + 0x1 + + + + + PWRSAVE_TX_WU_EN + Power Save TSM TX Warmup Enable + 4 + 1 + read-write + + + PWRSAVE_TX_WU_EN_0 + PowerSave TSM TX Warmups are disabled + 0 + + + PWRSAVE_TX_WU_EN_1 + PowerSave TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup. + 0x1 + + + + + PWRSAVE_RX_WU_EN + Power Save TSM RX Warmup Enable + 5 + 1 + read-write + + + PWRSAVE_RX_WU_EN_0 + PowerSave TSM RX Warmups are disabled + 0 + + + PWRSAVE_RX_WU_EN_1 + PowerSave TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup. + 0x1 + + + + + PWRSAVE_WU_CLEAR + PowerSave TSM Warmup Clear State + 6 + 1 + read-write + + + FAST_RX2TX_START + TSM "Jump-to" point for a Fast TSM RX-to-TX Transition. + 8 + 8 + read-write + + + FAST_TX2RX_EN + Fast TSM TX-to-RX Transition Enable + 23 + 1 + read-write + + + FAST_TX2RX_EN_0 + Disable Fast TX-to-RX transitions + 0 + + + FAST_TX2RX_EN_1 + Enable Fast TX-to-RX transitions (if fast_tx2rx_wu is asserted by Ranging sequence manager) + 0x1 + + + + + FAST_TX2RX_START + TSM "Jump-to" point for a Fast TSM TX-to-RX Transition. + 24 + 8 + read-write + + + + + FAST_CTRL2 + TSM FAST WARMUP CONTROL 2 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FAST_START_TX + Fast TSM TX "Jump-from" Point + 0 + 8 + read-write + + + FAST_DEST_TX + Fast TSM TX "Jump-to" Point + 8 + 8 + read-write + + + FAST_START_RX + Fast TSM RX "Jump-from" Point + 16 + 8 + read-write + + + FAST_DEST_RX + Fast TSM RX "Jump-to" Point + 24 + 8 + read-write + + + + + FAST_CTRL3 + TSM FAST WARMUP CONTROL 3 + 0x1C + 32 + read-write + 0xFF00 + 0xFFFFFFFF + + + FAST_RX2TX_START_FC + TSM "Jump-to" point for RSM's FC RX-to-TX Transition + 8 + 8 + read-write + + + FAST_TX2RX_START_FC + TSM "Jump-to" point for RSM's FC TX-to-RX Transition + 24 + 8 + read-write + + + + + TIMING00 + TSM_TIMING00 + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RF_ACTIVE_TX_HI + Assertion time setting for RF_ACTIVE (TX) + 0 + 8 + read-write + + + RF_ACTIVE_TX_LO + De-assertion time setting for RF_ACTIVE (TX) + 8 + 8 + read-write + + + RF_ACTIVE_RX_HI + Assertion time setting for RF_ACTIVE_EN (RX) + 16 + 8 + read-write + + + RF_ACTIVE_RX_LO + De-assertion time setting for RF_ACTIVE (RX) + 24 + 8 + read-write + + + + + TIMING01 + TSM_TIMING01 + 0x24 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RF_STATUS_TX_HI + Assertion time setting for RF_STATUS (TX) + 0 + 8 + read-write + + + RF_STATUS_TX_LO + De-assertion time setting for RF_STATUS (TX) + 8 + 8 + read-write + + + RF_STATUS_RX_HI + Assertion time setting for RF_STATUS (RX) + 16 + 8 + read-write + + + RF_STATUS_RX_LO + De-assertion time setting for RF_STATUS (RX) + 24 + 8 + read-write + + + + + TIMING02 + TSM_TIMING02 + 0x28 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RF_PRIORITY_TX_HI + Assertion time setting for RF_PRIORITY (TX) + 0 + 8 + read-write + + + RF_PRIORITY_TX_LO + De-assertion time setting for RF_PRIORITY (TX) + 8 + 8 + read-write + + + RF_PRIORITY_RX_HI + Assertion time setting for RF_PRIORITY (RX) + 16 + 8 + read-write + + + RF_PRIORITY_RX_LO + De-assertion time setting for RF_PRIORITY (RX) + 24 + 8 + read-write + + + + + TIMING03 + TSM_TIMING03 + 0x2C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + IRQ0_START_TRIG_TX_HI + Assertion time setting for IRQ0_START_TRIG (TX) + 0 + 8 + read-write + + + IRQ0_START_TRIG_TX_LO + De-assertion time setting for IRQ0_START_TRIG (TX) + 8 + 8 + read-write + + + IRQ0_START_TRIG_RX_HI + Assertion time setting for IRQ0_START_TRIG (RX) + 16 + 8 + read-write + + + IRQ0_START_TRIG_RX_LO + De-assertion time setting for IRQ0_START_TRIG (RX) + 24 + 8 + read-write + + + + + TIMING04 + TSM_TIMING04 + 0x30 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + IRQ1_STOP_TRIG_TX_HI + Assertion time setting for IRQ1_STOP_TRIG (TX) + 0 + 8 + read-write + + + IRQ1_STOP_TRIG_TX_LO + De-assertion time setting for IRQ1_STOP_TRIG (TX) + 8 + 8 + read-write + + + IRQ1_STOP_TRIG_RX_HI + Assertion time setting for IRQ1_STOP_TRIG (RX) + 16 + 8 + read-write + + + IRQ1_STOP_TRIG_RX_LO + De-assertion time setting for IRQ1_STOP_TRIG (RX) + 24 + 8 + read-write + + + + + TIMING05 + TSM_TIMING05 + 0x34 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO0_TRIG_EN_TX_HI + Assertion time setting for GPIO0_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO0_TRIG_EN_TX_LO + De-assertion time setting for GPIO0_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO0_TRIG_EN_RX_HI + Assertion time setting for GPIO0_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO0_TRIG_EN_RX_LO + De-assertion time setting for GPIO0_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING06 + TSM_TIMING06 + 0x38 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO1_TRIG_EN_TX_HI + Assertion time setting for GPIO1_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO1_TRIG_EN_TX_LO + De-assertion time setting for GPIO1_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO1_TRIG_EN_RX_HI + Assertion time setting for GPIO1_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO1_TRIG_EN_RX_LO + De-assertion time setting for GPIO1_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING07 + TSM_TIMING07 + 0x3C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO2_TRIG_EN_TX_HI + Assertion time setting for GPIO2_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO2_TRIG_EN_TX_LO + De-assertion time setting for GPIO2_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO2_TRIG_EN_RX_HI + Assertion time setting for GPIO2_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO2_TRIG_EN_RX_LO + De-assertion time setting for GPIO2_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING08 + TSM_TIMING08 + 0x40 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO3_TRIG_EN_TX_HI + Assertion time setting for GPIO3_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO3_TRIG_EN_TX_LO + De-assertion time setting for GPIO3_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO3_TRIG_EN_RX_HI + Assertion time setting for GPIO3_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO3_TRIG_EN_RX_LO + De-assertion time setting for GPIO3_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING09 + TSM_TIMING09 + 0x44 + 32 + read-write + 0x5700FFFF + 0xFFFFFFFF + + + DCOC_GAIN_CFG_EN_TX_HI + Assertion time setting for DCOC_GAIN_CFG_EN (TX) + 0 + 8 + read-write + + + DCOC_GAIN_CFG_EN_TX_LO + De-assertion time setting for DCOC_GAIN_CFG_EN (TX) + 8 + 8 + read-write + + + DCOC_GAIN_CFG_EN_RX_HI + Assertion time setting for DCOC_GAIN_CFG_EN (RX) + 16 + 8 + read-write + + + DCOC_GAIN_CFG_EN_RX_LO + De-assertion time setting for DCOC_GAIN_CFG_EN (RX) + 24 + 8 + read-write + + + + + TIMING10 + TSM_TIMING10 + 0x48 + 32 + read-write + 0x11081108 + 0xFFFFFFFF + + + LDO_CAL_EN_TX_HI + Assertion time setting for LDO_CAL_EN (TX) + 0 + 8 + read-write + + + LDO_CAL_EN_TX_LO + De-assertion time setting for LDO_CAL_EN (TX) + 8 + 8 + read-write + + + LDO_CAL_EN_RX_HI + Assertion time setting for LDO_CAL_EN (RX) + 16 + 8 + read-write + + + LDO_CAL_EN_RX_LO + De-assertion time setting for LDO_CAL_EN (RX) + 24 + 8 + read-write + + + + + TIMING11 + TSM_TIMING11 + 0x4C + 32 + read-write + 0x5B137113 + 0xFFFFFFFF + + + PLL_DIG_EN_TX_HI + Assertion time setting for PLL_DIG_EN (TX) + 0 + 8 + read-write + + + PLL_DIG_EN_TX_LO + De-assertion time setting for PLL_DIG_EN (TX) + 8 + 8 + read-write + + + PLL_DIG_EN_RX_HI + Assertion time setting for PLL_DIG_EN (RX) + 16 + 8 + read-write + + + PLL_DIG_EN_RX_LO + De-assertion time setting for PLL_DIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING12 + TSM_TIMING12 + 0x50 + 32 + read-write + 0x5B19714F + 0xFFFFFFFF + + + SIGMA_DELTA_EN_TX_HI + Assertion time setting for SIGMA_DELTA_EN (TX) + 0 + 8 + read-write + + + SIGMA_DELTA_EN_TX_LO + De-assertion time setting for SIGMA_DELTA_EN (TX) + 8 + 8 + read-write + + + SIGMA_DELTA_EN_RX_HI + Assertion time setting for SIGMA_DELTA_EN (RX) + 16 + 8 + read-write + + + SIGMA_DELTA_EN_RX_LO + De-assertion time setting for SIGMA_DELTA_EN (RX) + 24 + 8 + read-write + + + + + TIMING13 + TSM_TIMING13 + 0x54 + 32 + read-write + 0x572DFFFF + 0xFFFFFFFF + + + DCOC_CAL_EN_TX_HI + Assertion time setting for DCOC_CAL_EN (TX) + 0 + 8 + read-write + + + DCOC_CAL_EN_TX_LO + De-assertion time setting for DCOC_CAL_EN (TX) + 8 + 8 + read-write + + + DCOC_CAL_EN_RX_HI + Assertion time setting for DCOC_CAL_EN (RX) + 16 + 8 + read-write + + + DCOC_CAL_EN_RX_LO + De-assertion time setting for DCOC_CAL_EN (RX) + 24 + 8 + read-write + + + + + TIMING14 + TSM_TIMING14 + 0x58 + 32 + read-write + 0x716F + 0xFFFFFFFF + + + TX_DIG_EN_TX_HI + Assertion time setting for TX_DIG_EN (TX) + 0 + 8 + read-write + + + TX_DIG_EN_TX_LO + De-assertion time setting for TX_DIG_EN (TX) + 8 + 8 + read-write + + + + + TIMING15 + TSM_TIMING15 + 0x5C + 32 + read-write + 0x5B58716F + 0xFFFFFFFF + + + FREQ_TARG_LD_EN_TX_HI + Assertion time setting for FREQ_TARG_LD_EN (TX) + 0 + 8 + read-write + + + FREQ_TARG_LD_EN_TX_LO + De-assertion time setting for FREQ_TARG_LD_EN (TX) + 8 + 8 + read-write + + + FREQ_TARG_LD_EN_RX_HI + Assertion time setting for FREQ_TARG_LD_EN (RX) + 16 + 8 + read-write + + + FREQ_TARG_LD_EN_RX_LO + De-assertion time setting for FREQ_TARG_LD_EN (RX) + 24 + 8 + read-write + + + + + TIMING16 + TSM_TIMING16 + 0x60 + 32 + read-write + 0x59580000 + 0xFFFFFFFF + + + RX_INIT_RX_HI + Assertion time setting for RX_INIT (RX) + 16 + 8 + read-write + + + RX_INIT_RX_LO + De-assertion time setting for RX_INIT (RX) + 24 + 8 + read-write + + + + + TIMING17 + TSM_TIMING17 + 0x64 + 32 + read-write + 0x5B580000 + 0xFFFFFFFF + + + RX_DIG_EN_RX_HI + Assertion time setting for RX_DIG_EN (RX) + 16 + 8 + read-write + + + RX_DIG_EN_RX_LO + De-assertion time setting for RX_DIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING18 + TSM_TIMING18 + 0x68 + 32 + read-write + 0x5B580000 + 0xFFFFFFFF + + + RX_PHY_EN_RX_HI + Assertion time setting for RX_PHY_EN (RX) + 16 + 8 + read-write + + + RX_PHY_EN_RX_LO + De-assertion time setting for RX_PHY_EN (RX) + 24 + 8 + read-write + + + + + TIMING19 + TSM_TIMING19 + 0x6C + 32 + read-write + 0x11001100 + 0xFFFFFFFF + + + SEQ_BG_PUP_IBG_CAL_TX_HI + Assertion time setting for SEQ_BG_PUP_IBG_CAL (TX) + 0 + 8 + read-write + + + SEQ_BG_PUP_IBG_CAL_TX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_CAL (TX) + 8 + 8 + read-write + + + SEQ_BG_PUP_IBG_CAL_RX_HI + Assertion time setting for SEQ_BG_PUP_IBG_CAL (RX) + 16 + 8 + read-write + + + SEQ_BG_PUP_IBG_CAL_RX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_CAL (RX) + 24 + 8 + read-write + + + + + TIMING20 + TSM_TIMING20 + 0x70 + 32 + read-write + 0x11001100 + 0xFFFFFFFF + + + SEQ_LDOTRIM_PUP_TX_HI + Assertion time setting for SEQ_LDOTRIM_PUP (TX) + 0 + 8 + read-write + + + SEQ_LDOTRIM_PUP_TX_LO + De-assertion time setting for SEQ_LDOTRIM_PUP (TX) + 8 + 8 + read-write + + + SEQ_LDOTRIM_PUP_RX_HI + Assertion time setting for SEQ_LDOTRIM_PUP (RX) + 16 + 8 + read-write + + + SEQ_LDOTRIM_PUP_RX_LO + De-assertion time setting for SEQ_LDOTRIM_PUP (RX) + 24 + 8 + read-write + + + + + TIMING21 + TSM_TIMING21 + 0x74 + 32 + read-write + 0x19001100 + 0xFFFFFFFF + + + SEQ_LDO_CAL_PUP_TX_HI + Assertion time setting for SEQ_LDO_CAL_PUP (TX) + 0 + 8 + read-write + + + SEQ_LDO_CAL_PUP_TX_LO + De-assertion time setting for SEQ_LDO_CAL_PUP (TX) + 8 + 8 + read-write + + + SEQ_LDO_CAL_PUP_RX_HI + Assertion time setting for SEQ_LDO_CAL_PUP (RX) + 16 + 8 + read-write + + + SEQ_LDO_CAL_PUP_RX_LO + De-assertion time setting for SEQ_LDO_CAL_PUP (RX) + 24 + 8 + read-write + + + + + TIMING22 + TSM_TIMING22 + 0x78 + 32 + read-write + 0x58006F00 + 0xFFFFFFFF + + + SEQ_BG_FC_TX_HI + Assertion time setting for SEQ_BG_FC (TX) + 0 + 8 + read-write + + + SEQ_BG_FC_TX_LO + De-assertion time setting for SEQ_BG_FC (TX) + 8 + 8 + read-write + + + SEQ_BG_FC_RX_HI + Assertion time setting for SEQ_BG_FC (RX) + 16 + 8 + read-write + + + SEQ_BG_FC_RX_LO + De-assertion time setting for SEQ_BG_FC (RX) + 24 + 8 + read-write + + + + + TIMING23 + TSM_TIMING23 + 0x7C + 32 + read-write + 0x58006F00 + 0xFFFFFFFF + + + SEQ_LDO_GANG_FC_TX_HI + Assertion time setting for SEQ_LDO_GANG_FC (TX) + 0 + 8 + read-write + + + SEQ_LDO_GANG_FC_TX_LO + De-assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (TX) + 8 + 8 + read-write + + + SEQ_LDO_GANG_FC_RX_HI + Assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (RX) + 16 + 8 + read-write + + + SEQ_LDO_GANG_FC_RX_LO + De-assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (RX) + 24 + 8 + read-write + + + + + TIMING24 + TSM_TIMING24 + 0x80 + 32 + read-write + 0x5B007100 + 0xFFFFFFFF + + + SEQ_LDO_GANG_PUP_TX_HI + Assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (TX) + 0 + 8 + read-write + + + SEQ_LDO_GANG_PUP_TX_LO + De-assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (TX) + 8 + 8 + read-write + + + SEQ_LDO_GANG_PUP_RX_HI + Assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (RX) + 16 + 8 + read-write + + + SEQ_LDO_GANG_PUP_RX_LO + De-assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (RX) + 24 + 8 + read-write + + + + + TIMING25 + TSM_TIMING25 + 0x84 + 32 + read-write + 0x5C007200 + 0xFFFFFFFF + + + SEQ_LDO_LV_PUP_TX_HI + Assertion time setting for SEQ_LDO_LV_PUP (TX) + 0 + 8 + read-write + + + SEQ_LDO_LV_PUP_TX_LO + De-assertion time setting for SEQ_LDO_LV_PUP (TX) + 8 + 8 + read-write + + + SEQ_LDO_LV_PUP_RX_HI + Assertion time setting for SEQ_LDO_LV_PUP (RX) + 16 + 8 + read-write + + + SEQ_LDO_LV_PUP_RX_LO + De-assertion time setting for SEQ_LDO_LV_PUP (RX) + 24 + 8 + read-write + + + + + TIMING26 + TSM_TIMING26 + 0x88 + 32 + read-write + 0x5C007200 + 0xFFFFFFFF + + + SEQ_BG_PUP_TX_HI + Assertion time setting for SEQ_BG_PUP (TX) + 0 + 8 + read-write + + + SEQ_BG_PUP_TX_LO + De-assertion time setting for SEQ_BG_PUP (TX) + 8 + 8 + read-write + + + SEQ_BG_PUP_RX_HI + Assertion time setting for SEQ_BG_PUP (RX) + 16 + 8 + read-write + + + SEQ_BG_PUP_RX_LO + De-assertion time setting for SEQ_BG_PUP (RX) + 24 + 8 + read-write + + + + + TIMING27 + TSM_TIMING27 + 0x8C + 32 + read-write + 0x5C007200 + 0xFFFFFFFF + + + SEQ_BG_PUP_IBG_ANT_TX_HI + Assertion time setting for SEQ_BG_PUP_IBG_ANT (TX) + 0 + 8 + read-write + + + SEQ_BG_PUP_IBG_ANT_TX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_ANT (TX) + 8 + 8 + read-write + + + SEQ_BG_PUP_IBG_ANT_RX_HI + Assertion time setting for SEQ_BG_PUP_IBG_ANT (RX) + 16 + 8 + read-write + + + SEQ_BG_PUP_IBG_ANT_RX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_ANT (RX) + 24 + 8 + read-write + + + + + TIMING28 + TSM_TIMING28 + 0x90 + 32 + read-write + 0x5C007200 + 0xFFFFFFFF + + + SEQ_BG_PUP_IBG_XO_DIST_TX_HI + Assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (TX) + 0 + 8 + read-write + + + SEQ_BG_PUP_IBG_XO_DIST_TX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (TX) + 8 + 8 + read-write + + + SEQ_BG_PUP_IBG_XO_DIST_RX_HI + Assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (RX) + 16 + 8 + read-write + + + SEQ_BG_PUP_IBG_XO_DIST_RX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (RX) + 24 + 8 + read-write + + + + + TIMING29 + TSM_TIMING29 + 0x94 + 32 + read-write + 0xFFFF7200 + 0xFFFFFFFF + + + SEQ_BG_PUP_IBG_TX_TX_HI + Assertion time setting for SEQ_BG_PUP_IBG_TX (TX) + 0 + 8 + read-write + + + SEQ_BG_PUP_IBG_TX_TX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_TX (TX) + 8 + 8 + read-write + + + SEQ_BG_PUP_IBG_TX_RX_HI + Assertion time setting for SEQ_BG_PUP_IBG_TX (RX) + 16 + 8 + read-write + + + SEQ_BG_PUP_IBG_TX_RX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_TX (RX) + 24 + 8 + read-write + + + + + TIMING30 + TSM_TIMING30 + 0x98 + 32 + read-write + 0x5C00FFFF + 0xFFFFFFFF + + + SEQ_BG_PUP_IBG_RX_TX_HI + Assertion time setting for SEQ_BG_PUP_IBG_RX (TX) + 0 + 8 + read-write + + + SEQ_BG_PUP_IBG_RX_TX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_RX (TX) + 8 + 8 + read-write + + + SEQ_BG_PUP_IBG_RX_RX_HI + Assertion time setting for SEQ_BG_PUP_IBG_RX (RX) + 16 + 8 + read-write + + + SEQ_BG_PUP_IBG_RX_RX_LO + De-assertion time setting for SEQ_BG_PUP_IBG_RX (RX) + 24 + 8 + read-write + + + + + TIMING31 + TSM_TIMING31 + 0x9C + 32 + read-write + 0x5B087108 + 0xFFFFFFFF + + + SEQ_TSM_ISO_B_2P4GHZ_TX_HI + Assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (TX) + 0 + 8 + read-write + + + SEQ_TSM_ISO_B_2P4GHZ_TX_LO + De-assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (TX) + 8 + 8 + read-write + + + SEQ_TSM_ISO_B_2P4GHZ_RX_HI + Assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (RX) + 16 + 8 + read-write + + + SEQ_TSM_ISO_B_2P4GHZ_RX_LO + De-assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (RX) + 24 + 8 + read-write + + + + + TIMING32 + TSM_TIMING32 + 0xA0 + 32 + read-write + 0x1911FFFF + 0xFFFFFFFF + + + SEQ_RCCAL_PUP_TX_HI + Assertion time setting for SEQ_RCCAL_PUP (TX) + 0 + 8 + read-write + + + SEQ_RCCAL_PUP_TX_LO + De-assertion time setting for SEQ_RCCAL_PUP (TX) + 8 + 8 + read-write + + + SEQ_RCCAL_PUP_RX_HI + Assertion time setting for SEQ_RCCAL_PUP (RX) + 16 + 8 + read-write + + + SEQ_RCCAL_PUP_RX_LO + De-assertion time setting for SEQ_RCCAL_PUP (RX) + 24 + 8 + read-write + + + + + TIMING33 + TSM_TIMING33 + 0xA4 + 32 + read-write + 0x23115A11 + 0xFFFFFFFF + + + SEQ_PD_EN_FCAL_BIAS_TX_HI + Assertion time setting for SEQ_PD_EN_FCAL_BIAS (TX) + 0 + 8 + read-write + + + SEQ_PD_EN_FCAL_BIAS_TX_LO + De-assertion time setting for SEQ_PD_EN_FCAL_BIAS (TX) + 8 + 8 + read-write + + + SEQ_PD_EN_FCAL_BIAS_RX_HI + Assertion time setting for SEQ_PD_EN_FCAL_BIAS (RX) + 16 + 8 + read-write + + + SEQ_PD_EN_FCAL_BIAS_RX_LO + De-assertion time setting for SEQ_PD_EN_FCAL_BIAS (RX) + 24 + 8 + read-write + + + + + TIMING34 + TSM_TIMING34 + 0xA8 + 32 + read-write + 0x5B117111 + 0xFFFFFFFF + + + SEQ_PD_PUP_TX_HI + Assertion time setting for SEQ_PD_PUP (TX) + 0 + 8 + read-write + + + SEQ_PD_PUP_TX_LO + De-assertion time setting for SEQ_PD_PUP (TX) + 8 + 8 + read-write + + + SEQ_PD_PUP_RX_HI + Assertion time setting for SEQ_PD_PUP (RX) + 16 + 8 + read-write + + + SEQ_PD_PUP_RX_LO + De-assertion time setting for SEQ_PD_PUP (RX) + 24 + 8 + read-write + + + + + TIMING35 + TSM_TIMING35 + 0xAC + 32 + read-write + 0x5B117111 + 0xFFFFFFFF + + + SEQ_VCO_PUP_TX_HI + Assertion time setting for SEQ_VCO_PUP (TX) + 0 + 8 + read-write + + + SEQ_VCO_PUP_TX_LO + De-assertion time setting for SEQ_VCO_PUP (TX) + 8 + 8 + read-write + + + SEQ_VCO_PUP_RX_HI + Assertion time setting for SEQ_VCO_PUP (RX) + 16 + 8 + read-write + + + SEQ_VCO_PUP_RX_LO + De-assertion time setting for SEQ_VCO_PUP (RX) + 24 + 8 + read-write + + + + + TIMING36 + TSM_TIMING36 + 0xB0 + 32 + read-write + 0x5B117111 + 0xFFFFFFFF + + + SEQ_XO_DIST_EN_TX_HI + Assertion time setting for SEQ_XO_DIST_EN (TX) + 0 + 8 + read-write + + + SEQ_XO_DIST_EN_TX_LO + De-assertion time setting for SEQ_XO_DIST_EN (TX) + 8 + 8 + read-write + + + SEQ_XO_DIST_EN_RX_HI + Assertion time setting for SEQ_XO_DIST_EN (RX) + 16 + 8 + read-write + + + SEQ_XO_DIST_EN_RX_LO + De-assertion time setting for SEQ_XO_DIST_EN (RX) + 24 + 8 + read-write + + + + + TIMING37 + TSM_TIMING37 + 0xB4 + 32 + read-write + 0x5B117111 + 0xFFFFFFFF + + + SEQ_XO_DIST_EN_CLK_REF_TX_HI + Assertion time setting for SEQ_XO_DIST_EN_CLK_REF (TX) + 0 + 8 + read-write + + + SEQ_XO_DIST_EN_CLK_REF_TX_LO + De-assertion time setting for SEQ_XO_DIST_EN_CLK_REF (TX) + 8 + 8 + read-write + + + SEQ_XO_DIST_EN_CLK_REF_RX_HI + Assertion time setting for SEQ_XO_DIST_EN_CLK_REF (RX) + 16 + 8 + read-write + + + SEQ_XO_DIST_EN_CLK_REF_RX_LO + De-assertion time setting for SEQ_XO_DIST_EN_CLK_REF (RX) + 24 + 8 + read-write + + + + + TIMING38 + TSM_TIMING38 + 0xB8 + 32 + read-write + 0x5B117111 + 0xFFFFFFFF + + + SEQ_XO_EN_CLK_2P4G_TX_HI + Assertion time setting for SEQ_XO_EN_CLK_2P4G (TX) + 0 + 8 + read-write + + + SEQ_XO_EN_CLK_2P4G_TX_LO + De-assertion time setting for SEQ_XO_EN_CLK_2P4G (TX) + 8 + 8 + read-write + + + SEQ_XO_EN_CLK_2P4G_RX_HI + Assertion time setting for SEQ_XO_EN_CLK_2P4G (RX) + 16 + 8 + read-write + + + SEQ_XO_EN_CLK_2P4G_RX_LO + De-assertion time setting for SEQ_XO_EN_CLK_2P4G (RX) + 24 + 8 + read-write + + + + + TIMING39 + TSM_TIMING39 + 0xBC + 32 + read-write + 0x5B2B7111 + 0xFFFFFFFF + + + SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI + Assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (TX) + 0 + 8 + read-write + + + SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO + De-assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (TX) + 8 + 8 + read-write + + + SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI + Assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (RX) + 16 + 8 + read-write + + + SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO + De-assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (RX) + 24 + 8 + read-write + + + + + TIMING40 + TSM_TIMING40 + 0xC0 + 32 + read-write + 0xFFFF7111 + 0xFFFFFFFF + + + SEQ_DAC_PUP_TX_HI + Assertion time setting for SEQ_DAC_PUP (TX) + 0 + 8 + read-write + + + SEQ_DAC_PUP_TX_LO + De-assertion time setting for SEQ_DAC_PUP (TX) + 8 + 8 + read-write + + + SEQ_DAC_PUP_RX_HI + Assertion time setting for SEQ_DAC_PUP (RX) + 16 + 8 + read-write + + + SEQ_DAC_PUP_RX_LO + De-assertion time setting for SEQ_DAC_PUP (RX) + 24 + 8 + read-write + + + + + TIMING41 + TSM_TIMING41 + 0xC4 + 32 + read-write + 0xFFFF7111 + 0xFFFFFFFF + + + SEQ_VCO_EN_HPM_TX_HI + Assertion time setting for SEQ_VCO_EN_HPM (TX) + 0 + 8 + read-write + + + SEQ_VCO_EN_HPM_TX_LO + De-assertion time setting for SEQ_VCO_EN_HPM (TX) + 8 + 8 + read-write + + + SEQ_VCO_EN_HPM_RX_HI + Assertion time setting for SEQ_VCO_EN_HPM (RX) + 16 + 8 + read-write + + + SEQ_VCO_EN_HPM_RX_LO + De-assertion time setting for SEQ_VCO_EN_HPM (RX) + 24 + 8 + read-write + + + + + TIMING42 + TSM_TIMING42 + 0xC8 + 32 + read-write + 0x5B127112 + 0xFFFFFFFF + + + SEQ_LO_PUP_VLO_FBK_TX_HI + Assertion time setting for SEQ_LO_PUP_VLO_FBK (TX) + 0 + 8 + read-write + + + SEQ_LO_PUP_VLO_FBK_TX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_FBK (TX) + 8 + 8 + read-write + + + SEQ_LO_PUP_VLO_FBK_RX_HI + Assertion time setting for SEQ_LO_PUP_VLO_FBK (RX) + 16 + 8 + read-write + + + SEQ_LO_PUP_VLO_FBK_RX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_FBK (RX) + 24 + 8 + read-write + + + + + TIMING43 + TSM_TIMING43 + 0xCC + 32 + read-write + 0x5B12FFFF + 0xFFFFFFFF + + + SEQ_LO_PUP_VLO_RX_TX_HI + Assertion time setting for SEQ_LO_PUP_VLO_RX (TX) + 0 + 8 + read-write + + + SEQ_LO_PUP_VLO_RX_TX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_RX (TX) + 8 + 8 + read-write + + + SEQ_LO_PUP_VLO_RX_RX_HI + Assertion time setting for SEQ_LO_PUP_VLO_RX (RX) + 16 + 8 + read-write + + + SEQ_LO_PUP_VLO_RX_RX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_RX (RX) + 24 + 8 + read-write + + + + + TIMING44 + TSM_TIMING44 + 0xD0 + 32 + read-write + 0x5B12FFFF + 0xFFFFFFFF + + + SEQ_LO_PUP_VLO_RXDRV_TX_HI + Assertion time setting for SEQ_LO_PUP_VLO_RXDRV (TX) + 0 + 8 + read-write + + + SEQ_LO_PUP_VLO_RXDRV_TX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_RXDRV (TX) + 8 + 8 + read-write + + + SEQ_LO_PUP_VLO_RXDRV_RX_HI + Assertion time setting for SEQ_LO_PUP_VLO_RXDRV (RX) + 16 + 8 + read-write + + + SEQ_LO_PUP_VLO_RXDRV_RX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_RXDRV (RX) + 24 + 8 + read-write + + + + + TIMING45 + TSM_TIMING45 + 0xD4 + 32 + read-write + 0xFFFF7112 + 0xFFFFFFFF + + + SEQ_LO_PUP_VLO_TX_TX_HI + Assertion time setting for SEQ_LO_PUP_VLO_TX (TX) + 0 + 8 + read-write + + + SEQ_LO_PUP_VLO_TX_TX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_TX (TX) + 8 + 8 + read-write + + + SEQ_LO_PUP_VLO_TX_RX_HI + Assertion time setting for SEQ_LO_PUP_VLO_TX (RX) + 16 + 8 + read-write + + + SEQ_LO_PUP_VLO_TX_RX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_TX (RX) + 24 + 8 + read-write + + + + + TIMING46 + TSM_TIMING46 + 0xD8 + 32 + read-write + 0xFFFF7112 + 0xFFFFFFFF + + + SEQ_LO_PUP_VLO_TXDRV_TX_HI + Assertion time setting for SEQ_LO_PUP_VLO_TXDRV (TX) + 0 + 8 + read-write + + + SEQ_LO_PUP_VLO_TXDRV_TX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_TXDRV (TX) + 8 + 8 + read-write + + + SEQ_LO_PUP_VLO_TXDRV_RX_HI + Assertion time setting for SEQ_LO_PUP_VLO_TXDRV (RX) + 16 + 8 + read-write + + + SEQ_LO_PUP_VLO_TXDRV_RX_LO + De-assertion time setting for SEQ_LO_PUP_VLO_TXDRV (RX) + 24 + 8 + read-write + + + + + TIMING47 + TSM_TIMING47 + 0xDC + 32 + read-write + 0x5B137157 + 0xFFFFFFFF + + + SEQ_DIVN_PUP_TX_HI + Assertion time setting for SEQ_DIVN_PUP (TX) + 0 + 8 + read-write + + + SEQ_DIVN_PUP_TX_LO + De-assertion time setting for SEQ_DIVN_PUP (TX) + 8 + 8 + read-write + + + SEQ_DIVN_PUP_RX_HI + Assertion time setting for SEQ_DIVN_PUP (RX) + 16 + 8 + read-write + + + SEQ_DIVN_PUP_RX_LO + De-assertion time setting for SEQ_DIVN_PUP (RX) + 24 + 8 + read-write + + + + + TIMING48 + TSM_TIMING48 + 0xE0 + 32 + read-write + 0x5B23715A + 0xFFFFFFFF + + + SEQ_DIVN_CLOSEDLOOP_TX_HI + Assertion time setting for SEQ_DIVN_CLOSEDLOOP (TX) + 0 + 8 + read-write + + + SEQ_DIVN_CLOSEDLOOP_TX_LO + De-assertion time setting for SEQ_DIVN_CLOSEDLOOP (TX) + 8 + 8 + read-write + + + SEQ_DIVN_CLOSEDLOOP_RX_HI + Assertion time setting for SEQ_DIVN_CLOSEDLOOP (RX) + 16 + 8 + read-write + + + SEQ_DIVN_CLOSEDLOOP_RX_LO + De-assertion time setting for SEQ_DIVN_CLOSEDLOOP (RX) + 24 + 8 + read-write + + + + + TIMING49 + TSM_TIMING49 + 0xE4 + 32 + read-write + 0x5B23715A + 0xFFFFFFFF + + + SEQ_PD_EN_PD_DRV_TX_HI + Assertion time setting for SEQ_PD_EN_PD_DRV (TX) + 0 + 8 + read-write + + + SEQ_PD_EN_PD_DRV_TX_LO + De-assertion time setting for SEQ_PD_EN_PD_DRV (TX) + 8 + 8 + read-write + + + SEQ_PD_EN_PD_DRV_RX_HI + Assertion time setting for SEQ_PD_EN_PD_DRV (RX) + 16 + 8 + read-write + + + SEQ_PD_EN_PD_DRV_RX_LO + De-assertion time setting for SEQ_PD_EN_PD_DRV (RX) + 24 + 8 + read-write + + + + + TIMING50 + TSM_TIMING50 + 0xE8 + 32 + read-write + 0x5B2BFFFF + 0xFFFFFFFF + + + SEQ_CBPF_EN_DCOC_TX_HI + Assertion time setting for SEQ_CBPF_EN_DCOC (TX) + 0 + 8 + read-write + + + SEQ_CBPF_EN_DCOC_TX_LO + De-assertion time setting for SEQ_CBPF_EN_DCOC (TX) + 8 + 8 + read-write + + + SEQ_CBPF_EN_DCOC_RX_HI + Assertion time setting for SEQ_CBPF_EN_DCOC (RX) + 16 + 8 + read-write + + + SEQ_CBPF_EN_DCOC_RX_LO + De-assertion time setting for SEQ_CBPF_EN_DCOC (RX) + 24 + 8 + read-write + + + + + TIMING51 + TSM_TIMING51 + 0xEC + 32 + read-write + 0x5B2BFFFF + 0xFFFFFFFF + + + SEQ_RX_GANG_PUP_TX_HI + Assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (TX) + 0 + 8 + read-write + + + SEQ_RX_GANG_PUP_TX_LO + De-assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (TX) + 8 + 8 + read-write + + + SEQ_RX_GANG_PUP_RX_HI + Assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (RX) + 16 + 8 + read-write + + + SEQ_RX_GANG_PUP_RX_LO + De-assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (RX) + 24 + 8 + read-write + + + + + TIMING52 + TSM_TIMING52 + 0xF0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SEQ_SPARE3_TX_HI + Assertion time setting for SEQ_SPARE3 (TX) + 0 + 8 + read-write + + + SEQ_SPARE3_TX_LO + De-assertion time setting for SEQ_SPARE3 (TX) + 8 + 8 + read-write + + + SEQ_SPARE3_RX_HI + Assertion time setting for SEQ_SPARE3 (RX) + 16 + 8 + read-write + + + SEQ_SPARE3_RX_LO + De-assertion time setting for SEQ_SPARE3 (RX) + 24 + 8 + read-write + + + + + OVRD0 + TSM OVERRIDE REGISTER 0 + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSM_RF_ACTIVE_OVRD_EN + Override control for TSM_RF_ACTIVE + 0 + 1 + read-write + + + TSM_RF_ACTIVE_OVRD_EN_0 + Normal operation. + 0 + + + TSM_RF_ACTIVE_OVRD_EN_1 + Use the state of TSM_RF_ACTIVE_OVRD to override the signal "tsm_rf_active". + 0x1 + + + + + TSM_RF_ACTIVE_OVRD + Override value for tsm_rf_active + 1 + 1 + read-write + + + TSM_RF_STATUS_OVRD_EN + Override control for TSM_RF_STATUS_EN + 2 + 1 + read-write + + + TSM_RF_STATUS_OVRD_EN_0 + Normal operation. + 0 + + + TSM_RF_STATUS_OVRD_EN_1 + Use the state of TSM_RF_STATUS_OVRD to override the signal "tsm_rf_status". + 0x1 + + + + + TSM_RF_STATUS_OVRD + Override value for TSM_RF_STATUS + 3 + 1 + read-write + + + TSM_RF_PRIORITY_OVRD_EN + Override control for TSM_RF_PRIORITY_EN + 4 + 1 + read-write + + + TSM_RF_PRIORITY_OVRD_EN_0 + Normal operation. + 0 + + + TSM_RF_PRIORITY_OVRD_EN_1 + Use the state of TSM_RF_PRIORITY_OVRD to override the signal "tsm_rf_priority". + 0x1 + + + + + TSM_RF_PRIORITY_OVRD + Override value for tsm_rf_priority + 5 + 1 + read-write + + + TSM_IRQ0_START_TRIG_OVRD_EN + Override control for TSM_IRQ0_START_TRIG_EN + 6 + 1 + read-write + + + TSM_IRQ0_START_TRIG_OVRD_EN_0 + Normal operation. + 0 + + + TSM_IRQ0_START_TRIG_OVRD_EN_1 + Use the state of TSM_IRQ0_START_TRIG_OVRD to override the signal "tsm_irq0_start_trig". + 0x1 + + + + + TSM_IRQ0_START_TRIG_OVRD + Override value for TSM_IRQ0_START_TRIG + 7 + 1 + read-write + + + TSM_IRQ1_STOP_TRIG_OVRD_EN + Override control for TSM_IRQ1_STOP_TRIG + 8 + 1 + read-write + + + TSM_IRQ1_STOP_TRIG_OVRD_EN_0 + Normal operation. + 0 + + + TSM_IRQ1_STOP_TRIG_OVRD_EN_1 + Use the state of TSM_IRQ1_STOP_TRIG_OVRD to override the signal "tsm_irq1_stop_trig". + 0x1 + + + + + TSM_IRQ1_STOP_TRIG_OVRD + Override value for TSM_IRQ1_STOP_TRIG + 9 + 1 + read-write + + + DCOC_GAIN_CFG_EN_OVRD_EN + Override control for DCOC_GAIN_CFG_EN + 10 + 1 + read-write + + + DCOC_GAIN_CFG_EN_OVRD_EN_0 + Normal operation. + 0 + + + DCOC_GAIN_CFG_EN_OVRD_EN_1 + Use the state of DCOC_GAIN_CFG_EN_OVRD to override the signal "dcoc_gain_cfg_en". + 0x1 + + + + + DCOC_GAIN_CFG_EN_OVRD + Override value for DCOC_GAIN_CFG_EN + 11 + 1 + read-write + + + LDO_CAL_EN_OVRD_EN + Override control for LDO_CAL_EN_ + 12 + 1 + read-write + + + LDO_CAL_EN_OVRD_EN_0 + Normal operation. + 0 + + + LDO_CAL_EN_OVRD_EN_1 + Use the state of LDO_CAL_EN_OVRD to override the signal "ldo_cal_en". + 0x1 + + + + + LDO_CAL_EN_OVRD + Override value for LDO_CAL_EN + 13 + 1 + read-write + + + PLL_DIG_EN_OVRD_EN + Override control for PLL_DIG_EN + 14 + 1 + read-write + + + PLL_DIG_EN_OVRD_EN_0 + Normal operation. + 0 + + + PLL_DIG_EN_OVRD_EN_1 + Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en". + 0x1 + + + + + PLL_DIG_EN_OVRD + Override value for PLL_DIG_EN + 15 + 1 + read-write + + + SIGMA_DELTA_EN_OVRD_EN + Override control for SIGMA_DELTA_EN + 16 + 1 + read-write + + + SIGMA_DELTA_EN_OVRD_EN_0 + Normal operation. + 0 + + + SIGMA_DELTA_EN_OVRD_EN_1 + Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en". + 0x1 + + + + + SIGMA_DELTA_EN_OVRD + Override value for SIGMA_DELTA_EN + 17 + 1 + read-write + + + DCOC_CAL_EN_OVRD_EN + Override control for DCOC_CAL_EN + 18 + 1 + read-write + + + DCOC_CAL_EN_OVRD_EN_0 + Normal operation. + 0 + + + DCOC_CAL_EN_OVRD_EN_1 + Use the state of DCOC_CAL_EN_OVRD to override the signal "dcoc_cal_en". + 0x1 + + + + + DCOC_CAL_EN_OVRD + Override value for DCOC_CAL_EN + 19 + 1 + read-write + + + TX_DIG_EN_OVRD_EN + Override control for TX_DIG_EN + 20 + 1 + read-write + + + TX_DIG_EN_OVRD_EN_0 + Normal operation. + 0 + + + TX_DIG_EN_OVRD_EN_1 + Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en". + 0x1 + + + + + TX_DIG_EN_OVRD + Override value for TX_DIG_EN + 21 + 1 + read-write + + + FREQ_TARG_LD_EN_OVRD_EN + Override control for FREQ_TARG_LD_EN + 22 + 1 + read-write + + + FREQ_TARG_LD_EN_OVRD_EN_0 + Normal operation. + 0 + + + FREQ_TARG_LD_EN_OVRD_EN_1 + Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en". + 0x1 + + + + + FREQ_TARG_LD_EN_OVRD + Override value for FREQ_TARG_LD_EN + 23 + 1 + read-write + + + RX_INIT_EN_OVRD_EN + Override control for RX_INIT_EN + 24 + 1 + read-write + + + RX_INIT_EN_OVRD_EN_0 + Normal operation. + 0 + + + RX_INIT_EN_OVRD_EN_1 + Use the state of RX_INIT_EN_OVRD to override the signal "rx_init_en". + 0x1 + + + + + RX_INIT_EN_OVRD + Override value for RX_INIT_EN + 25 + 1 + read-write + + + RX_DIG_EN_OVRD_EN + Override control for RX_DIG_EN + 26 + 1 + read-write + + + RX_DIG_EN_OVRD_EN_0 + Normal operation. + 0 + + + RX_DIG_EN_OVRD_EN_1 + Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en". + 0x1 + + + + + RX_DIG_EN_OVRD + Override value for RX_DIG_EN + 27 + 1 + read-write + + + RX_PHY_EN_OVRD_EN + Override control for RX_PHY_EN + 28 + 1 + read-write + + + RX_PHY_EN_OVRD_EN_0 + Normal operation. + 0 + + + RX_PHY_EN_OVRD_EN_1 + Use the state of RX_PHY_EN_OVRD to override the signal "rx_phy_en". + 0x1 + + + + + RX_PHY_EN_OVRD + Override value for RX_PHY_EN + 29 + 1 + read-write + + + SEQ_BG_PUP_IBG_CAL_OVRD_EN + Override control for SEQ_BG_PUP_IBG_CAL + 30 + 1 + read-write + + + SEQ_BG_PUP_IBG_CAL_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_PUP_IBG_CAL_OVRD_EN_1 + Use the state of SEQ_BG_PUP_IBG_CAL_OVRD to override the signal "seq_bg_pup_ibg_cal". + 0x1 + + + + + SEQ_BG_PUP_IBG_CAL_OVRD + Override value for SEQ_BG_PUP_IBG_CAL + 31 + 1 + read-write + + + + + OVRD1 + TSM OVERRIDE REGISTER 1 + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQ_LDOTRIM_PUP_OVRD_EN + Override control for SEQ_LDOTRIM_PUP + 0 + 1 + read-write + + + SEQ_LDOTRIM_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDOTRIM_PUP_OVRD_EN_1 + Use the state of SEQ_LDOTRIM_PUP_OVRD to override the signal "seq_ldotrim_pup". + 0x1 + + + + + SEQ_LDOTRIM_PUP_OVRD + Override value for SEQ_LDOTRIM_PUP + 1 + 1 + read-write + + + SEQ_LDO_CAL_PUP_OVRD_EN + Override control for SEQ_LDO_CAL_PUP + 2 + 1 + read-write + + + SEQ_LDO_CAL_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_CAL_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_CAL_PUP_OVRD to override the signal "seq_ldo_cal_pup". + 0x1 + + + + + SEQ_LDO_CAL_PUP_OVRD + Override value for SEQ_LDO_CAL_PUP + 3 + 1 + read-write + + + SEQ_BG_FC_OVRD_EN + Override control for SEQ_BG_FC + 4 + 1 + read-write + + + SEQ_BG_FC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_FC_OVRD_EN_1 + Use the state of SEQ_BG_FC_OVRD to override the signal "seq_bg_fc". + 0x1 + + + + + SEQ_BG_FC_OVRD + Override value for SEQ_BG_FC + 5 + 1 + read-write + + + SEQ_LDO_PLL_FC_OVRD_EN + Override control for SEQ_LDO_PLL_FC + 6 + 1 + read-write + + + SEQ_LDO_PLL_FC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_PLL_FC_OVRD_EN_1 + Use the state of SEQ_LDO_PLL_FC_OVRD to override the signal "seq_ldo_pll_fc". + 0x1 + + + + + SEQ_LDO_PLL_FC_OVRD + Override value for SEQ_LDO_PLL_FC + 7 + 1 + read-write + + + SEQ_LDO_VCO_FC_OVRD_EN + Override control for SEQ_LDO_VCO_FC + 8 + 1 + read-write + + + SEQ_LDO_VCO_FC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_VCO_FC_OVRD_EN_1 + Use the state of SEQ_LDO_VCO_FC_OVRD to override the signal "seq_ldo_vco_fc". + 0x1 + + + + + SEQ_LDO_VCO_FC_OVRD + Override value for SEQ_LDO_VCO_FC + 9 + 1 + read-write + + + SEQ_LDO_RXTXHF_FC_OVRD_EN + Override control for SEQ_LDO_RXTXHF_FC + 10 + 1 + read-write + + + SEQ_LDO_RXTXHF_FC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_RXTXHF_FC_OVRD_EN_1 + Use the state of SEQ_LDO_RXTXHF_FC_OVRD to override the signal "seq_ldo_rxtxhf_fc". + 0x1 + + + + + SEQ_LDO_RXTXHF_FC_OVRD + Override value for SEQ_LDO_RXTXHF_FC + 11 + 1 + read-write + + + SEQ_LDO_RXTXLF_FC_OVRD_EN + Override control for SEQ_LDO_RXTXLF_FC + 12 + 1 + read-write + + + SEQ_LDO_RXTXLF_FC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_RXTXLF_FC_OVRD_EN_1 + Use the state of SEQ_LDO_RXTXLF_FC_OVRD to override the signal "seq_ldo_rxtxlf_fc". + 0x1 + + + + + SEQ_LDO_RXTXLF_FC_OVRD + Override value for SEQ_LDO_RXTXLF_FC + 13 + 1 + read-write + + + SEQ_LDO_ANT_PUP_OVRD_EN + Override control for SEQ_LDO_ANT_PUP + 14 + 1 + read-write + + + SEQ_LDO_ANT_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_ANT_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_ANT_PUP_OVRD to override the signal "seq_ldo_ant_pup". + 0x1 + + + + + SEQ_LDO_ANT_PUP_OVRD + Override value for SEQ_LDO_ANT_PUP + 15 + 1 + read-write + + + SEQ_LDO_PLL_PUP_OVRD_EN + Override control for SEQ_LDO_PLL_PUP + 16 + 1 + read-write + + + SEQ_LDO_PLL_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_PLL_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_PLL_PUP_OVRD to override the signal "seq_ldo_pll_pup". + 0x1 + + + + + SEQ_LDO_PLL_PUP_OVRD + Override value for SEQ_LDO_PLL_PUP + 17 + 1 + read-write + + + SEQ_LDO_VCO_PUP_OVRD_EN + Override control for SEQ_LDO_VCO_PUP + 18 + 1 + read-write + + + SEQ_LDO_VCO_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_VCO_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_VCO_PUP_OVRD to override the signal "seq_ldo_vco_pup". + 0x1 + + + + + SEQ_LDO_VCO_PUP_OVRD + Override value for SEQ_LDO_VCO_PUP + 19 + 1 + read-write + + + SEQ_LDO_XO_DIST_PUP_OVRD_EN + Override control for SEQ_LDO_XO_DIST_PUP + 20 + 1 + read-write + + + SEQ_LDO_XO_DIST_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_XO_DIST_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_XO_DIST_PUP_OVRD to override the signal "seq_ldo_xo_dist_pup". + 0x1 + + + + + SEQ_LDO_XO_DIST_PUP_OVRD + Override value for SEQ_LDO_XO_DIST_PUP + 21 + 1 + read-write + + + SEQ_LDO_RXTXHF_PUP_OVRD_EN + Override control for SEQ_LDO_RXTXHF_PUP + 22 + 1 + read-write + + + SEQ_LDO_RXTXHF_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_RXTXHF_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_RXTXHF_PUP_OVRD to override the signal "seq_ldo_rxtxhf_pup". + 0x1 + + + + + SEQ_LDO_RXTXHF_PUP_OVRD + Override value for SEQ_LDO_RXTXHF_PUP + 23 + 1 + read-write + + + SEQ_LDO_RXTXLF_PUP_OVRD_EN + Override control for SEQ_LDO_RXTXLF_PUP + 24 + 1 + read-write + + + SEQ_LDO_RXTXLF_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_RXTXLF_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_RXTXLF_PUP_OVRD to override the signal "seq_ldo_rxtxlf_pup". + 0x1 + + + + + SEQ_LDO_RXTXLF_PUP_OVRD + Override value for SEQ_LDO_RXTXLF_PUP + 25 + 1 + read-write + + + SEQ_LDO_LV_PUP_OVRD_EN + Override control for SEQ_LDO_LV_PUP + 26 + 1 + read-write + + + SEQ_LDO_LV_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LDO_LV_PUP_OVRD_EN_1 + Use the state of SEQ_LDO_LV_PUP_OVRD to override the signal "seq_ldo_lv_pup". + 0x1 + + + + + SEQ_LDO_LV_PUP_OVRD + Override value for SEQ_LDO_LV_PUP + 27 + 1 + read-write + + + SEQ_BG_PUP_OVRD_EN + Override control for SEQ_BG_PUP_OVRD_EN + 28 + 1 + read-write + + + SEQ_BG_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_PUP_OVRD_EN_1 + Use the state of SEQ_BG_PUP_OVRD to override the signal "seq_bg_pup". + 0x1 + + + + + SEQ_BG_PUP_OVRD + Override value for SEQ_BG_PUP + 29 + 1 + read-write + + + SEQ_BG_PUP_IBG_ANT_OVRD_EN + Override control for SEQ_BG_PUP_IBG_ANT + 30 + 1 + read-write + + + SEQ_BG_PUP_IBG_ANT_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_PUP_IBG_ANT_OVRD_EN_1 + Use the state of SEQ_BG_PUP_IBG_ANT_OVRD to override the signal "seq_bg_pup_ibg_ant". + 0x1 + + + + + SEQ_BG_PUP_IBG_ANT_OVRD + Override value for SEQ_BG_PUP_IBG_ANT + 31 + 1 + read-write + + + + + OVRD2 + TSM OVERRIDE REGISTER 2 + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN + Override control for SEQ_BG_PUP_IBG_XO_DIST + 0 + 1 + read-write + + + SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN_1 + Use the state of SEQ_BG_PUP_IBG_XO_DIST_OVRD to override the signal "seq_bg_pup_ibg_xo_dist". + 0x1 + + + + + SEQ_BG_PUP_IBG_XO_DIST_OVRD + Override value for SEQ_BG_PUP_IBG_XO_DIST + 1 + 1 + read-write + + + SEQ_BG_PUP_IBG_TX_OVRD_EN + Override control for SEQ_BG_PUP_IBG_TX + 2 + 1 + read-write + + + SEQ_BG_PUP_IBG_TX_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_PUP_IBG_TX_OVRD_EN_1 + Use the state of SEQ_BG_PUP_IBG_TX_OVRD to override the signal "seq_bg_pup_ibg_tx". + 0x1 + + + + + SEQ_BG_PUP_IBG_TX_OVRD + Override value for SEQ_BG_PUP_IBG_TX + 3 + 1 + read-write + + + SEQ_BG_PUP_IBG_RX_OVRD_EN + Override control for SEQ_BG_PUP_IBG_RX + 4 + 1 + read-write + + + SEQ_BG_PUP_IBG_RX_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_BG_PUP_IBG_RX_OVRD_EN_1 + Use the state of SEQ_BG_PUP_IBG_RX_OVRD to override the signal "seq_bg_pup_ibg_rx". + 0x1 + + + + + SEQ_BG_PUP_IBG_RX_OVRD + Override value for SEQ_BG_PUP_IBG_RX + 5 + 1 + read-write + + + SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN + Override control for SEQ_TSM_ISO_B_2P4GHZ + 6 + 1 + read-write + + + SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN_1 + Use the state of SEQ_TSM_ISO_B_2P4GHZ_OVRD to override the signal "seq_tsm_iso_b_2p4ghz". + 0x1 + + + + + SEQ_TSM_ISO_B_2P4GHZ_OVRD + Override value for SEQ_TSM_ISO_B_2P4GHZ + 7 + 1 + read-write + + + SEQ_RCCAL_PUP_OVRD_EN + Override control for SEQ_RCCAL_PUP + 8 + 1 + read-write + + + SEQ_RCCAL_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_RCCAL_PUP_OVRD_EN_1 + Use the state of SEQ_RCCAL_PUP_OVRD to override the signal "rx_rccal_pup". + 0x1 + + + + + SEQ_RCCAL_PUP_OVRD + Override value for SEQ_RCCAL_PUP + 9 + 1 + read-write + + + SEQ_PD_EN_FCAL_BIAS_OVRD_EN + Override control for SEQ_PD_EN_FCAL_BIAS + 10 + 1 + read-write + + + SEQ_PD_EN_FCAL_BIAS_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_PD_EN_FCAL_BIAS_OVRD_EN_1 + Use the state of SEQ_PD_EN_FCAL_BIAS_OVRD to override the signal "seq_pd_en_fcal_bias". + 0x1 + + + + + SEQ_PD_EN_FCAL_BIAS_OVRD + Override value for SEQ_PD_EN_FCAL_BIAS + 11 + 1 + read-write + + + SEQ_PD_PUP_OVRD_EN + Override control for SEQ_PD_PUP + 12 + 1 + read-write + + + SEQ_PD_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_PD_PUP_OVRD_EN_1 + Use the state of SEQ_PD_PUP_OVRD to override the signal "seq_pd_pup". + 0x1 + + + + + SEQ_PD_PUP_OVRD + Override value for SEQ_PD_PUP + 13 + 1 + read-write + + + SEQ_VCO_PUP_OVRD_EN + Override control for SEQ_VCO_PUP + 14 + 1 + read-write + + + SEQ_VCO_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_VCO_PUP_OVRD_EN_1 + Use the state of SEQ_VCO_PUP_OVRD to override the signal "seq_vco_pup". + 0x1 + + + + + SEQ_VCO_PUP_OVRD + Override value for SEQ_VCO_PUP + 15 + 1 + read-write + + + SEQ_XO_DIST_EN_OVRD_EN + Override control for SEQ_XO_DIST_EN + 16 + 1 + read-write + + + SEQ_XO_DIST_EN_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_XO_DIST_EN_OVRD_EN_1 + Use the state of SEQ_XO_DIST_EN_OVRD to override the signal "seq_xo_dist_en". + 0x1 + + + + + SEQ_XO_DIST_EN_OVRD + Override value for SEQ_XO_DIST_EN + 17 + 1 + read-write + + + SEQ_XO_DIST_EN_CLK_REF_OVRD_EN + Override control for SEQ_XO_DIST_EN_CLK_REF + 18 + 1 + read-write + + + SEQ_XO_DIST_EN_CLK_REF_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_XO_DIST_EN_CLK_REF_OVRD_EN_1 + Use the state of SEQ_XO_DIST_EN_CLK_REF_OVRD to override the signal "seq_xo_dist_en_clk_ref". + 0x1 + + + + + SEQ_XO_DIST_EN_CLK_REF_OVRD + Override value for SEQ_XO_DIST_EN_CLK_REF + 19 + 1 + read-write + + + SEQ_XO_EN_CLK_2P4G_OVRD_EN + Override control for SEQ_XO_EN_CLK_2P4G + 20 + 1 + read-write + + + SEQ_XO_EN_CLK_2P4G_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_XO_EN_CLK_2P4G_OVRD_EN_1 + Use the state of SEQ_XO_EN_CLK_2P4G_OVRD to override the signal "seq_xo_en_clk_2p4g". + 0x1 + + + + + SEQ_XO_EN_CLK_2P4G_OVRD + Override value for SEQ_XO_EN_CLK_2P4G_OVRD_EN + 21 + 1 + read-write + + + SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN + Override control for SEQ_XO_DIST_EN_CLK_ADCDAC + 22 + 1 + read-write + + + SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN_1 + Use the state of SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN to override the signal "seq_xo_dist_en_clk_adcdac". + 0x1 + + + + + SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD + Override value for SEQ_XO_DIST_EN_CLK_ADCDAC + 23 + 1 + read-write + + + SEQ_DAC_PUP_OVRD_EN + Override control for SEQ_DAC_PUP + 24 + 1 + read-write + + + SEQ_DAC_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_DAC_PUP_OVRD_EN_1 + Use the state of SEQ_DAC_PUP_OVRD to override the signal "seq_dac_pup". + 0x1 + + + + + SEQ_DAC_PUP_OVRD + Override value for SEQ_DAC_PUP + 25 + 1 + read-write + + + SEQ_VCO_EN_HPM_OVRD_EN + Override control for SEQ_VCO_EN_HPM + 26 + 1 + read-write + + + SEQ_VCO_EN_HPM_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_VCO_EN_HPM_OVRD_EN_1 + Use the state of SEQ_VCO_EN_HPM_OVRD to override the signal "seq_vco_en_hpm". + 0x1 + + + + + SEQ_VCO_EN_HPM_OVRD + Override value for SEQ_VCO_EN_HPM + 27 + 1 + read-write + + + SEQ_LO_PUP_VLO_FBK_OVRD_EN + Override control for SEQ_LO_PUP_VLO_FBK + 28 + 1 + read-write + + + SEQ_LO_PUP_VLO_FBK_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LO_PUP_VLO_FBK_OVRD_EN_1 + Use the state of SEQ_LO_PUP_VLO_FBK_OVRD to override the signal "seq_lo_pup_vlo_fbk". + 0x1 + + + + + SEQ_LO_PUP_VLO_FBK_OVRD + Override value for SEQ_LO_PUP_VLO_FBK + 29 + 1 + read-write + + + SEQ_LO_PUP_VLO_RXDRV_OVRD_EN + Override control for SEQ_LO_PUP_VLO_RXDRV + 30 + 1 + read-write + + + SEQ_LO_PUP_VLO_RXDRV_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LO_PUP_VLO_RXDRV_OVRD_EN_1 + Use the state of SEQ_LO_PUP_VLO_RXDRV_OVRD to override the signal "seq_lo_pup_vlo_rxdrv". + 0x1 + + + + + SEQ_LO_PUP_VLO_RXDRV_OVRD + Override value for SEQ_LO_PUP_VLO_RXDRV + 31 + 1 + read-write + + + + + OVRD3 + TSM OVERRIDE REGISTER 3 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQ_LO_PUP_VLO_RX_OVRD_EN + Override control for SEQ_LO_PUP_VLO_RX + 0 + 1 + read-write + + + SEQ_LO_PUP_VLO_RX_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LO_PUP_VLO_RX_OVRD_EN_1 + Use the state of SEQ_LO_PUP_VLO_RX_OVRD to override the signal "seq_lo_pup_vlo_rx". + 0x1 + + + + + SEQ_LO_PUP_VLO_RX_OVRD + Override value for SEQ_LO_PUP_VLO_RX + 1 + 1 + read-write + + + SEQ_LO_PUP_VLO_TX_OVRD_EN + Override control for SEQ_LO_PUP_VLO_TX + 2 + 1 + read-write + + + SEQ_LO_PUP_VLO_TX_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LO_PUP_VLO_TX_OVRD_EN_1 + Use the state of SEQ_LO_PUP_VLO_TX_OVRD to override the signal "seq_lo_pup_vlo_tx". + 0x1 + + + + + SEQ_LO_PUP_VLO_TX_OVRD + Override value for SEQ_LO_PUP_VLO_TX + 3 + 1 + read-write + + + SEQ_LO_PUP_VLO_TXDRV_OVRD_EN + Override control for SEQ_LO_PUP_VLO_TXDRV + 4 + 1 + read-write + + + SEQ_LO_PUP_VLO_TXDRV_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_LO_PUP_VLO_TXDRV_OVRD_EN_1 + Use the state of SEQ_LO_PUP_VLO_TXDRV_OVRD to override the signal "seq_lo_pup_vlo_txdrv". + 0x1 + + + + + SEQ_LO_PUP_VLO_TXDRV_OVRD + Override value for SEQ_LO_PUP_VLO_TXDRV + 5 + 1 + read-write + + + SEQ_DIVN_PUP_OVRD_EN + Override control for SEQ_DIVN_PUP + 6 + 1 + read-write + + + SEQ_DIVN_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_DIVN_PUP_OVRD_EN_1 + Use the state of SEQ_DIVN_PUP_OVRD to override the signal "seq_divn_pup". + 0x1 + + + + + SEQ_DIVN_PUP_OVRD + Override value for SEQ_DIVN_PUP + 7 + 1 + read-write + + + SEQ_DIVN_OPENLOOP_OVRD_EN + Override control for SEQ_DIVN_OPENLOOP + 8 + 1 + read-write + + + SEQ_DIVN_OPENLOOP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_DIVN_OPENLOOP_OVRD_EN_1 + Use the state of SEQ_DIVN_OPENLOOP_OVRD to override the signal "seq_divn_openloop". + 0x1 + + + + + SEQ_DIVN_OPENLOOP_OVRD + Override value for SEQ_DIVN_OPENLOOP + 9 + 1 + read-write + + + SEQ_PD_EN_PD_DRV_OVRD_EN + Override control for SEQ_PD_EN_PD_DRV + 10 + 1 + read-write + + + SEQ_PD_EN_PD_DRV_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_PD_EN_PD_DRV_OVRD_EN_1 + Use the state of SEQ_PD_EN_PD_DRV_OVRD to override the signal "seq_pd_en_pd_drv". + 0x1 + + + + + SEQ_PD_EN_PD_DRV_OVRD + Override value for SEQ_PD_EN_PD_DRV + 11 + 1 + read-write + + + SEQ_CBPF_EN_DCOC_OVRD_EN + Override control for SEQ_CBPF_EN_DCOC + 12 + 1 + read-write + + + SEQ_CBPF_EN_DCOC_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_CBPF_EN_DCOC_OVRD_EN_1 + Use the state of SEQ_CBPF_EN_DCOC_OVRD to override the signal "seq_cbpf_en_dcoc". + 0x1 + + + + + SEQ_CBPF_EN_DCOC_OVRD + Override value for SEQ_CBPF_EN_DCOC + 13 + 1 + read-write + + + SEQ_RX_LNA_PUP_OVRD_EN + Override control for SEQ_RX_LNA_PUP + 14 + 1 + read-write + + + SEQ_RX_LNA_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_RX_LNA_PUP_OVRD_EN_1 + Use the state of SEQ_RX_LNA_PUP_OVRD to override the signal "seq_rx_lna_pup". + 0x1 + + + + + SEQ_RX_LNA_PUP_OVRD + Override value for SEQ_RX_LNA_PUP + 15 + 1 + read-write + + + SEQ_ADC_PUP_OVRD_EN + Override control for SEQ_ADC_PUP + 16 + 1 + read-write + + + SEQ_ADC_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_ADC_PUP_OVRD_EN_1 + Use the state of SEQ_ADC_PUP_OVRD to override the signal "seq_adc_pup". + 0x1 + + + + + SEQ_ADC_PUP_OVRD + Override value for RX_DIG_EN + 17 + 1 + read-write + + + SEQ_CBPF_PUP_OVRD_EN + Override control for SEQ_CBPF_PUP + 18 + 1 + read-write + + + SEQ_CBPF_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_CBPF_PUP_OVRD_EN_1 + Use the state of SEQ_CBPF_PUP_OVRD to override the signal "seq_cbpf_pup". + 0x1 + + + + + SEQ_CBPF_PUP_OVRD + Override value for SEQ_CBPF_PUP + 19 + 1 + read-write + + + SEQ_RX_MIX_PUP_OVRD_EN + Override control for SEQ_RX_MIX_PUP + 20 + 1 + read-write + + + SEQ_RX_MIX_PUP_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_RX_MIX_PUP_OVRD_EN_1 + Use the state of SEQ_RX_MIX_PUP_OVRD to override the signal "seq_rx_mix_pup". + 0x1 + + + + + SEQ_RX_MIX_PUP_OVRD + Override control for SEQ_RX_MIX_PUP + 21 + 1 + read-write + + + SEQ_RX_MIX_PUP_OVRD_0 + Normal operation. + 0 + + + SEQ_RX_MIX_PUP_OVRD_1 + Use the state of SEQ_RX_MIX_PUP_OVRD to override the signal "seq_rx_mix_pup". + 0x1 + + + + + SEQ_SPARE1_OVRD_EN + Override control for SEQ_SPARE1 + 22 + 1 + read-write + + + SEQ_SPARE1_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_SPARE1_OVRD_EN_1 + Use the state of SEQ_SPARE1_OVRD to override the signal "seq_spare1". + 0x1 + + + + + SEQ_SPARE1_OVRD + Override value for SEQ_SPARE1 + 23 + 1 + read-write + + + SEQ_SPARE3_OVRD_EN + Override control for SEQ_SPARE3 + 24 + 1 + read-write + + + SEQ_SPARE3_OVRD_EN_0 + Normal operation. + 0 + + + SEQ_SPARE3_OVRD_EN_1 + Use the state of SEQ_SPARE3_OVRD to override the signal "seq_spare3". + 0x1 + + + + + SEQ_SPARE3_OVRD + Override value for SEQ_SPARE3 + 25 + 1 + read-write + + + TX_MODE_OVRD_EN + Override control for TX_MODE_OVRD + 26 + 1 + read-write + + + TX_MODE_OVRD_EN_0 + Normal operation. + 0 + + + TX_MODE_OVRD_EN_1 + Use the state of TX_MODE_OVRD to override the signal "tx_mode". + 0x1 + + + + + TX_MODE_OVRD + Override value for TX_MODE + 27 + 1 + read-write + + + RX_MODE_OVRD_EN + Override control for RX_MODE + 28 + 1 + read-write + + + RX_MODE_OVRD_EN_0 + Normal operation. + 0 + + + RX_MODE_OVRD_EN_1 + Use the state of RX_MODE_OVRD to override the signal "rx_mode". + 0x1 + + + + + RX_MODE_OVRD + Override value for RX_MODE + 29 + 1 + read-write + + + + + + + XCVR_ANALOG + XCVR_ANALOG + XCVR_ANALOG + 0x48A07C00 + + 0 + 0x24 + registers + + + + LDO_0 + RF Analog Baseband LDO Control 1 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BG_FORCE + reg_bg_force_dig + 3 + 1 + read-write + + + BG_FORCE_0 + force disable + 0 + + + BG_FORCE_1 + force enable + 0x1 + + + + + LDO_LV_TRIM + reg_ldo_lv_trim_dig[1:0] + 4 + 2 + read-write + + + LDO_LV_TRIM_0 + 0.91V Default LDO output + 0 + + + LDO_LV_TRIM_1 + 0.86V + 0x1 + + + LDO_LV_TRIM_2 + 0.97V + 0x2 + + + LDO_LV_TRIM_3 + 1.3V + 0x3 + + + + + LDO_LV_BYPASS + reg_ldo_lv_bypass_dig + 6 + 1 + read-write + + + LDO_LV_BYPASS_0 + disable bypass for ldo_lv + 0 + + + LDO_LV_BYPASS_1 + enable bypass for ldo_lv + 0x1 + + + + + LDO_RXTXHF_FORCE + reg_ldo_rxtxhf_force_dig + 8 + 1 + read-write + + + LDO_RXTXHF_FORCE_0 + Force disabled. + 0 + + + LDO_RXTXHF_FORCE_1 + Force enabled + 0x1 + + + + + LDO_RXTXHF_PTAT_BUMP + reg_ldo_rxtxhf_ptat_bump_dig + 9 + 2 + read-write + + + LDO_RXTXHF_PTAT_BUMP_0 + nominal + 0 + + + LDO_RXTXHF_PTAT_BUMP_1 + +30% + 0x1 + + + LDO_RXTXHF_PTAT_BUMP_2 + nominal + 0x2 + + + LDO_RXTXHF_PTAT_BUMP_3 + +30% + 0x3 + + + + + LDO_RXTXHF_BYPASS + reg_ldo_rxtxihf_bypass_dig + 11 + 1 + read-write + + + LDO_RXTXLF_FORCE + reg_ldo_rxtxlf_force_dig + 12 + 1 + read-write + + + LDO_RXTXLF_FORCE_0 + disable force + 0 + + + LDO_RXTXLF_FORCE_1 + enable force + 0x1 + + + + + LDO_RXTXLF_PTAT_BUMP + reg_ldo_rxtxlf_ptat_bump_dig[1:0] + 13 + 2 + read-write + + + LDO_RXTXLF_PTAT_BUMP_0 + nominal + 0 + + + LDO_RXTXLF_PTAT_BUMP_1 + +30% + 0x1 + + + LDO_RXTXLF_PTAT_BUMP_2 + nominal + 0x2 + + + LDO_RXTXLF_PTAT_BUMP_3 + +30% + 0x3 + + + + + LDO_RXTXLF_BYPASS + reg_ldo_rxtxlf_bypass_dig + 15 + 1 + read-write + + + LDO_RXTXLF_BYPASS_0 + Bypass disable + 0 + + + LDO_RXTXLF_BYPASS_1 + Bypass enable + 0x1 + + + + + LDO_PLL_FORCE + reg_ldo_pll_force_dig + 16 + 1 + read-write + + + LDO_PLL_FORCE_0 + force disable + 0 + + + LDO_PLL_FORCE_1 + force enable + 0x1 + + + + + LDO_PLL_PTAT_BUMP + reg_ldo_pll_ptat_bump_dig[1:0] + 17 + 2 + read-write + + + LDO_PLL_PTAT_BUMP_0 + nominal + 0 + + + LDO_PLL_PTAT_BUMP_1 + +30% + 0x1 + + + LDO_PLL_PTAT_BUMP_2 + nominal + 0x2 + + + LDO_PLL_PTAT_BUMP_3 + +30% + 0x3 + + + + + LDO_PLL_BYPASS + reg_ldo_pll_bypass_dig + 19 + 1 + read-write + + + LDO_PLL_BYPASS_0 + Bypass disabled. + 0 + + + LDO_PLL_BYPASS_1 + Bypass enabled + 0x1 + + + + + LDO_VCO_FORCE + reg_ldo_vco_force_dig + 20 + 1 + read-write + + + LDO_VCO_FORCE_0 + Force disable + 0 + + + LDO_VCO_FORCE_1 + Force enable + 0x1 + + + + + LDO_VCO_PTAT_BUMP + reg_ldo_vco_ptat_bump_dig[1:0] + 21 + 2 + read-write + + + LDO_VCO_PTAT_BUMP_0 + nominal + 0 + + + LDO_VCO_PTAT_BUMP_1 + +30% + 0x1 + + + LDO_VCO_PTAT_BUMP_2 + nominal + 0x2 + + + LDO_VCO_PTAT_BUMP_3 + +30% + 0x3 + + + + + LDO_VCO_BYPASS + reg_ldo_vco_bypass_dig + 23 + 1 + read-write + + + LDO_VCO_BYPASS_0 + disable VCO bypass + 0 + + + LDO_VCO_BYPASS_1 + eable VCO bypass + 0x1 + + + + + LDO_CAL_FORCE + reg_ldo_cal_force_dig + 24 + 1 + read-write + + + LDO_CAL_FORCE_0 + Force disable + 0 + + + LDO_CAL_FORCE_1 + Force enable + 0x1 + + + + + LDO_CAL_PTAT_BUMP + reg_ldo_vco_ptat_bump_dig[1:0] + 25 + 2 + read-write + + + LDO_CAL_PTAT_BUMP_0 + nominal + 0 + + + LDO_CAL_PTAT_BUMP_1 + +30% + 0x1 + + + LDO_CAL_PTAT_BUMP_2 + nominal + 0x2 + + + LDO_CAL_PTAT_BUMP_3 + +30% + 0x3 + + + + + LDO_CAL_BYPASS + reg_ldo_cal_bypass_dig + 27 + 1 + read-write + + + LDO_CAL_BYPASS_0 + disable CAL bypass + 0 + + + LDO_CAL_BYPASS_1 + eable CAL bypass + 0x1 + + + + + LDOTRIM_TRIM_VREF + reg_ldotrim_trim_vref_dig[1:0] + 28 + 2 + read-write + + + LDOTRIM_TRIM_VREF_0 + 0.810 + 0 + + + LDOTRIM_TRIM_VREF_1 + 0.832 + 0x1 + + + LDOTRIM_TRIM_VREF_2 + 0.854 + 0x2 + + + LDOTRIM_TRIM_VREF_3 + 0.788 + 0x3 + + + + + + + LDO_1 + RF Analog Baseband LDO Control 2 + 0x4 + 32 + read-write + 0x80 + 0xFFFFFFFF + + + LDO_ANT_TRIM + reg_ldo_ant_trim_dig[3:0] + 0 + 4 + read-write + + + LDO_ANT_TRIM_0 + 0.91 V ( Default ) + 0 + + + LDO_ANT_TRIM_1 + 0.97 V + 0x1 + + + LDO_ANT_TRIM_2 + 1.04 V + 0x2 + + + LDO_ANT_TRIM_3 + 1.12 V + 0x3 + + + LDO_ANT_TRIM_4 + 1.21 V + 0x4 + + + LDO_ANT_TRIM_5 + 1.32 V + 0x5 + + + LDO_ANT_TRIM_6 + 1.45 V + 0x6 + + + LDO_ANT_TRIM_7 + 1.52 V + 0x7 + + + LDO_ANT_TRIM_8 + 1.61 V + 0x8 + + + LDO_ANT_TRIM_9 + 1.80 V + 0x9 + + + LDO_ANT_TRIM_10 + 2.06 V + 0xA + + + LDO_ANT_TRIM_11 + 2.13 V + 0xB + + + LDO_ANT_TRIM_12 + 2.21 V + 0xC + + + LDO_ANT_TRIM_13 + 2.30 V + 0xD + + + LDO_ANT_TRIM_14 + 2.39 V + 0xE + + + LDO_ANT_TRIM_15 + 2.50 V + 0xF + + + + + LDO_ANT_HIZ + reg_ldo_ant_hiz_dig + 7 + 1 + read-write + + + LDO_ANT_HIZ_0 + high-impedance disabled. + 0 + + + LDO_ANT_HIZ_1 + high-impedance enabled + 0x1 + + + + + LDO_ANT_BYPASS + reg_ldo_ant_bypass_dig + 8 + 1 + read-write + + + LDO_ANT_BYPASS_0 + ANT bypass disable + 0 + + + LDO_ANT_BYPASS_1 + ANT bypass enable + 0x1 + + + + + LDO_ANT_REF_SEL + reg_ldo_ant_ref_sel_dig + 9 + 1 + read-write + + + LDO_ANT_REF_SEL_0 + sel type disable ( Default ) + 0 + + + LDO_ANT_REF_SEL_1 + sel type enable + 0x1 + + + + + + + XO_DIST + RF Analog XO DIST Control + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + XO_DIST_TRIM + reg_xo_dist_trim_dig[1:0] + 0 + 2 + read-write + + + XO_DIST_TRIM_0 + 0.9 V ( Default ) + 0 + + + XO_DIST_TRIM_1 + 0.86 V + 0x1 + + + XO_DIST_TRIM_2 + 0.95 V + 0x2 + + + XO_DIST_TRIM_3 + 1.21 V + 0x3 + + + + + XO_DIST_FLIP + reg_xo_dist_flip_dig + 2 + 1 + read-write + + + XO_DIST_FLIP_0 + XO DIST doesn't flip the output clock relative to input clock + 0 + + + XO_DIST_FLIP_1 + XO DIST flip the output clock relative to input clock + 0x1 + + + + + XO_DIST_BYPASS + reg_xo_dist_bypass + 3 + 1 + read-write + + + XO_DIST_BYPASS_0 + XO DIST not bypass + 0 + + + XO_DIST_BYPASS_1 + XO DIST bypass + 0x1 + + + + + + + PLL + RF Analog PLL Control + 0xC + 32 + read-write + 0x4040 + 0xFFFFFFFF + + + PLL_VCO_TRIM_KVT + reg_vco_trim_kvt_dig[2:0] + 4 + 3 + read-write + + + PLL_VCO_TRIM_KVT_0 + 50MHz/V + 0 + + + PLL_VCO_TRIM_KVT_4 + 60MHz/V for fref = 32M + 0x4 + + + PLL_VCO_TRIM_KVT_6 + 70MHz/V + 0x6 + + + PLL_VCO_TRIM_KVT_7 + 80MHz/V for fref = 26M + 0x7 + + + + + PLL_VCO_EN_PKDET + reg_vco_en_pkdet_dig + 8 + 1 + read-write + + + PLL_VCO_EN_PKDET_0 + PKDET disable + 0 + + + PLL_VCO_EN_PKDET_1 + PKDET enable + 0x1 + + + + + PLL_PD_EN_VPD_PULLDN + reg_pd_en_vpd_pulldn_dig + 22 + 1 + read-write + + + PLL_PD_EN_VPD_PULLDN_0 + not pull down vpd output + 0 + + + PLL_PD_EN_VPD_PULLDN_1 + pull down vpd output + 0x1 + + + + + PLL_PD_EN_VPD_PULLUP + reg_pd_en_vpd_pullup_dig + 23 + 1 + read-write + + + PLL_PD_EN_VPD_PULLUP_0 + not pull up vpd output + 0 + + + PLL_PD_EN_VPD_PULLUP_1 + pull up vpd output + 0x1 + + + + + PLL_PD_TRIM_FCAL_BIAS + reg_pd_trim_fcal_bias_dig[1:0] + 26 + 2 + read-write + + + PLL_PD_TRIM_FCAL_BIAS_0 + 0.276V + 0 + + + PLL_PD_TRIM_FCAL_BIAS_1 + 0.164V + 0x1 + + + PLL_PD_TRIM_FCAL_BIAS_2 + 0.320V + 0x2 + + + PLL_PD_TRIM_FCAL_BIAS_3 + 0.391V + 0x3 + + + + + PLL_FCAL_EN_STATIC_RES + reg_fcal_en_static_res_dig + 31 + 1 + read-write + + + PLL_FCAL_EN_STATIC_RES_0 + resistor is dynamically switched during FCAL operation + 0 + + + PLL_FCAL_EN_STATIC_RES_1 + resistor is always on during FCAL operation + 0x1 + + + + + + + RX_0 + RF Analog RX Control0 + 0x10 + 32 + read-write + 0x10000002 + 0xFFFFFFFF + + + RX_LNA_ITRIM + reg_rx_lna_itrim_dig[1:0] + 0 + 2 + read-write + + + RX_LNA_ITRIM_0 + 3.7u -25% + 0 + + + RX_LNA_ITRIM_1 + 4.4u -15% + 0x1 + + + RX_LNA_ITRIM_2 + 5.1u Default + 0x2 + + + RX_LNA_ITRIM_3 + 5.6u +10% + 0x3 + + + + + RX_LNA_PTAT_FORCE_START + reg_rtfe_ptat_force_dig + 12 + 1 + read-write + + + RX_MIX_VBIAS + reg_rx_mix_vbias_dig[1:0] + 20 + 2 + read-write + + + RX_MIX_VBIAS_0 + 0.800V + 0 + + + RX_MIX_VBIAS_1 + 0.742V + 0x1 + + + RX_MIX_VBIAS_2 + 0.689V + 0x2 + + + RX_MIX_VBIAS_3 + 0.857V + 0x3 + + + + + ADC_TRIM + reg_adc_trim_dig[1:0] + 24 + 2 + read-write + + + ADC_TRIM_0 + 0.965V + 0 + + + ADC_TRIM_1 + 0.935V + 0x1 + + + ADC_TRIM_2 + 0.905V + 0x2 + + + ADC_TRIM_3 + 0.875V + 0x3 + + + + + ADC_INVERT_CLK + reg_adc_invert_clk_dig + 27 + 1 + read-write + + + ADC_INVERT_CLK_0 + not invert clk + 0 + + + ADC_INVERT_CLK_1 + invert clk + 0x1 + + + + + + + RX_1 + RF Analog RX Control1 + 0x14 + 32 + read-write + 0x22008 + 0xFFFFFFFF + + + CBPF_TYPE + reg_cbpf_type_dig + 3 + 1 + read-write + + + CBPF_TYPE_0 + Real + 0 + + + CBPF_TYPE_1 + Complex, + 0x1 + + + + + CBPF_TRIM_I + reg_cbpf_trim_i_dig[1:0] + 4 + 2 + read-write + + + CBPF_TRIM_I_0 + 5u (Default) + 0 + + + CBPF_TRIM_I_1 + 6.25u + 0x1 + + + CBPF_TRIM_I_2 + 7.5u + 0x2 + + + CBPF_TRIM_I_3 + 8.75u + 0x3 + + + + + CBPF_TRIM_Q + reg_cbpf_trim_q_dig[1:0] + 8 + 2 + read-write + + + CBPF_TRIM_Q_0 + 5u (Default) + 0 + + + CBPF_TRIM_Q_1 + 6.25u + 0x1 + + + CBPF_TRIM_Q_2 + 7.5u + 0x2 + + + CBPF_TRIM_Q_3 + 8.75u + 0x3 + + + + + CBPF_VCM_TRIM + reg_cbpf_vcm_trim_dig[1:0] + 12 + 2 + read-write + + + CBPF_VCM_TRIM_0 + 480mV + 0 + + + CBPF_VCM_TRIM_1 + 453mV + 0x1 + + + CBPF_VCM_TRIM_2 + 426mV + 0x2 + + + CBPF_VCM_TRIM_3 + 401mV + 0x3 + + + + + CBPF_TRIM_SHORT_DCBIAS + reg_cbpf_trim_short_dcbias_dig[1:0] + 16 + 2 + read-write + + + CBPF_TRIM_SHORT_DCBIAS_0 + 470mV + 0 + + + CBPF_TRIM_SHORT_DCBIAS_1 + 438mV + 0x1 + + + CBPF_TRIM_SHORT_DCBIAS_2 + 413mV + 0x2 + + + CBPF_TRIM_SHORT_DCBIAS_3 + 385mV + 0x3 + + + + + + + TX_DAC_PA + RF Analog TX DAC PA Control + 0x18 + 32 + read-write + 0x1000000 + 0xFFFFFFFF + + + DAC_INVERT_CLK + reg_dac_invert_clk_dig + 3 + 1 + read-write + + + DAC_TRIM_RLOAD + reg_dac_trim_rload_dig[1:0] + 8 + 2 + read-write + + + DAC_TRIM_RLOAD_0 + 3K + 0 + + + DAC_TRIM_RLOAD_1 + 2.25K + 0x1 + + + DAC_TRIM_RLOAD_2 + 3.75K + 0x2 + + + DAC_TRIM_RLOAD_3 + 4.5K + 0x3 + + + + + DAC_TRIM_IBIAS + reg_dac_trim_ibias_dig[1:0] + 10 + 2 + read-write + + + DAC_TRIM_IBIAS_0 + 3.0uA (I_lsb=250nA) + 0 + + + DAC_TRIM_IBIAS_1 + 2.5uA + 0x1 + + + DAC_TRIM_IBIAS_2 + 3.8uA + 0x2 + + + DAC_TRIM_IBIAS_3 + 5.0uA + 0x3 + + + + + TX_PA_VBIAS + reg_tx_pa_vbias_dig[1:0] + 16 + 2 + read-write + + + TX_PA_VBIAS_0 + 0.460V + 0 + + + TX_PA_VBIAS_1 + 0.431V + 0x1 + + + TX_PA_VBIAS_2 + 0.403V + 0x2 + + + TX_PA_VBIAS_3 + 0.375V + 0x3 + + + + + DAC_TRIM_CFBK + reg_dac_trim_cfbk_dig[1:0] + 24 + 2 + read-write + + + DAC_TRIM_CFBK_0 + 675fF + 0 + + + DAC_TRIM_CFBK_1 + 1.35pF + 0x1 + + + DAC_TRIM_CFBK_2 + 1.35pF + 0x2 + + + DAC_TRIM_CFBK_3 + 2.025pF + 0x3 + + + + + DAC_TRIM_CFBK_DRS + reg_dac_trim_cfbk_dig[1:0] + 26 + 2 + read-write + + + DAC_TRIM_CFBK_DRS_0 + 675fF + 0 + + + DAC_TRIM_CFBK_DRS_1 + 1.35pF + 0x1 + + + DAC_TRIM_CFBK_DRS_2 + 1.35pF + 0x2 + + + DAC_TRIM_CFBK_DRS_3 + 2.025pF + 0x3 + + + + + + + DIAG + RF Analog DIAG Control 1 + 0x1C + 32 + read-write + 0x40000000 + 0xFFFFFFFF + + + DIAG_CODE + reg_diag_code_dig[2:0] + 0 + 3 + read-write + + + LDO_CAL_DIAG_SEL + reg_ldo_cal_diag_sel_dig + 3 + 1 + read-write + + + LDO_VCO_DIAG_SEL + reg_ldo_vco_diag_sel_dig + 4 + 1 + read-write + + + LDO_PLL_DIAG_SEL + reg_ldo_pll_diag_sel_dig + 5 + 1 + read-write + + + LDO_RXTXLF_DIAG_SEL + reg_ldo_rxtxlf_diag_sel_dig + 8 + 1 + read-write + + + LDO_RXTXHF_DIAG_SEL + reg_ldo_rxtxhf_diag_sel_dig + 9 + 1 + read-write + + + LDO_LV_DIAG_SEL + reg_ldo_lv_diag_sel_dig + 10 + 1 + read-write + + + BG_DIAG_SEL + reg_bg_diag_sel_dig + 11 + 1 + read-write + + + LDOTRIM_DIAG_SEL + reg_ldotrim_diag_sel_dig + 12 + 1 + read-write + + + PROC_MON_DIAG_SEL + reg_proc_mon_diag_sel_dig + 13 + 1 + read-write + + + RTFE_DIAG_SEL + reg_rtfe_diag_sel_dig + 15 + 1 + read-write + + + CBPF_I_DIAG_SEL_1 + reg_cbpf_i_diag_sel_1_dig + 16 + 1 + read-write + + + CBPF_I_DIAG_SEL_2 + reg_cbpf_i_diag_sel_2_dig + 17 + 1 + read-write + + + CBPF_Q_DIAG_SEL_1 + reg_cbpf_q_diag_sel_1_dig + 18 + 1 + read-write + + + CBPF_Q_DIAG_SEL_2 + reg_cbpf_q_diag_sel_2_dig + 19 + 1 + read-write + + + CBPF_EN_DIAG_MEAS + reg_cbpf_en_diag_meas_dig + 20 + 1 + read-write + + + ADC_DIAG_SEL + reg_adc_diag_sel_dig + 21 + 1 + read-write + + + PD_DIAG_SEL + reg_pd_diag_sel_dig + 23 + 1 + read-write + + + VCO_DIAG_SEL + reg_vco_diag_sel_dig + 24 + 1 + read-write + + + DAC_DIAG_SEL + reg_dac_diag_sel_dig + 25 + 1 + read-write + + + XO_DIST_DIAG_SEL + reg_xo_dist_diag_sel_dig + 27 + 1 + read-write + + + LDO_ANT_DIAG_SEL + reg_ldo_ant_diag_sel_dig + 28 + 1 + read-write + + + DAC_AMP_DIAG_SEL + reg_dac_amp_diag_sel_dig + 29 + 1 + read-write + + + DIAG_DIS + reg_diag_dis_dig + 30 + 1 + read-write + + + ATX_ON_2P4GHZ + reg_2p4ghz_atx_on_dig + 31 + 1 + read-write + + + + + SPARE + RF Analog SPARE Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPARELV + reg_sparelv_dig[1:0] + 0 + 7 + read-write + + + SPARE_DIAG_SEL + reg_spare_diag_sel_dig[1:0] + 12 + 2 + read-write + + + + + + + XCVR_MISC + XCVR_MISC + XCVR_MISC + 0x48A07D00 + + 0 + 0x100 + registers + + + + XCVR_CTRL + TRANSCEIVER CONTROL + 0 + 32 + read-write + 0x140 + 0xFFFFFFFF + + + XCVR_SOFT_RESET + transciever soft reset control + 0 + 1 + read-write + + + XCVR_SOFT_RESET_0 + no soft reset + 0 + + + XCVR_SOFT_RESET_1 + enable soft reset on transciever + 0x1 + + + + + LPPS_ENABLE + transciever lpps enable control + 1 + 1 + read-write + + + LPPS_ENABLE_0 + no lpps feature + 0 + + + LPPS_ENABLE_1 + enable lpps feature + 0x1 + + + + + SDCLK_OUT_EN + sdclk out control + 3 + 1 + read-write + + + SDCLK_OUT_EN_0 + no sdclk out + 0 + + + SDCLK_OUT_EN_1 + enable sdclk out + 0x1 + + + + + DEMOD_SEL + Demodulator Selector + 6 + 2 + read-write + + + DEMOD_SEL_0 + No demodulator selected + 0 + + + DEMOD_SEL_1 + Use NXP Multi-standard PHY demodulator + 0x1 + + + DEMOD_SEL_2 + Use Legacy 802.15.4 demodulator + 0x2 + + + + + DATA_RATE + Radio data rate setting + 8 + 3 + read-write + + + DATA_RATE_0 + 2Mbps + 0 + + + DATA_RATE_1 + 1Mbps + 0x1 + + + DATA_RATE_2 + 500Kbps + 0x2 + + + DATA_RATE_3 + 250Kbps + 0x3 + + + + + DATA_RATE_DRS + Radio data rate setting, Data Rate Switch + 11 + 3 + read-write + + + DATA_RATE_DRS_0 + 2Mbps + 0 + + + DATA_RATE_DRS_1 + 1Mbps + 0x1 + + + DATA_RATE_DRS_2 + 500Kbps + 0x2 + + + DATA_RATE_DRS_3 + 250Kbps + 0x3 + + + + + REF_CLK_FREQ + transciever ref clk freq control + 15 + 1 + read-write + + + REF_CLK_FREQ_0 + 32MHz + 0 + + + REF_CLK_FREQ_1 + 26MHz + 0x1 + + + + + FO_RX_EN + Fast Overwrite RX Enable + 16 + 1 + read-write + + + FO_TX_EN + Fast Overwrite TX Enable + 17 + 1 + read-write + + + TOF_RX_SEL + Time-of-Flight RX Select + 18 + 1 + read-write + + + TOF_RX_SEL_0 + PHY: aa_fnd_to_ll + 0 + + + TOF_RX_SEL_1 + Localization Control: pattern_found + 0x1 + + + + + TOF_TX_SEL + Time-of-Flight TX Select + 19 + 1 + read-write + + + TOF_TX_SEL_0 + TSM: tx_dig_en + 0 + + + TOF_TX_SEL_1 + TXDIG: pa_wu_complete + 0x1 + + + + + LL_CFG_CAPT_DIS + Link Layer Configuration Capture Disable + 20 + 1 + read-write + + + LL_CFG_CAPT_DIS_0 + Enabled: Link Layer configuration inputs are captured. + 0 + + + LL_CFG_CAPT_DIS_1 + Disabled: Link Layer configurations are not captured. + 0x1 + + + + + + + XCVR_STATUS + TRANSCEIVER STATUS + 0x4 + 32 + read-write + 0 + 0xFFFF3F00 + + + TSM_COUNT + TSM_COUNT + 0 + 8 + read-only + + + TSM_IRQ0 + TSM Interrupt #0 + 8 + 1 + read-write + oneToClear + + + TSM_IRQ0_0 + TSM Interrupt #0 is not asserted. + 0 + + + TSM_IRQ0_1 + TSM Interrupt #0 is asserted. Write '1' to this bit to clear it. + 0x1 + + + + + TSM_IRQ1 + TSM Interrupt #1 + 9 + 1 + read-write + oneToClear + + + TSM_IRQ1_0 + TSM Interrupt #1 is not asserted. + 0 + + + TSM_IRQ1_1 + TSM Interrupt #1 is asserted. Write '1' to this bit to clear it. + 0x1 + + + + + TSM_BUSY + tsm busy status + 13 + 1 + read-only + + + RX_MODE + Receive Mode + 14 + 1 + read-only + + + TX_MODE + Transmit Mode + 15 + 1 + read-only + + + + + FAD_CTRL + FAD CONTROL + 0x8 + 32 + read-write + 0xF080 + 0xFFFFFFFF + + + FAD_EN + Fast Antenna Diversity Enable + 0 + 1 + read-write + + + FAD_EN_0 + Fast Antenna Diversity disabled + 0 + + + FAD_EN_1 + Fast Antenna Diversity enabled + 0x1 + + + + + ANTX + Antenna Selection State + 1 + 1 + read-only + + + ANTX_OVRD_EN + Antenna State Override Enable + 2 + 1 + read-write + + + ANTX_OVRD + Antenna State Override Value + 3 + 1 + read-write + + + ANTX_EN + FAD Antenna Controls Enable + 4 + 2 + read-write + + + ANTX_EN_0 + all disabled (held low) + 0 + + + ANTX_EN_1 + only RX/TX_SWITCH enabled + 0x1 + + + ANTX_EN_2 + only ANT_A/B enabled + 0x2 + + + ANTX_EN_3 + all enabled + 0x3 + + + + + ANTX_CTRLMODE + Antenna Diversity Control Mode + 7 + 1 + read-write + + + ANTX_POL + FAD Antenna Controls Polarity + 8 + 4 + read-write + + + FAD_NOT_GPIO + FAD versus GPIO Mode Selector + 12 + 4 + read-write + + + FAD_LANT_SEL + FAD versus LANT_LUT_GPIO Selector + 16 + 1 + read-write + + + FAD_LANT_SEL_0 + LANT_LUT_GPIO[3:0] + 0 + + + FAD_LANT_SEL_1 + {ANT_B, ANT_A, RX_SWITCH, TX_SWITCH} + 0x1 + + + + + + + DMA_CTRL + TRANSCEIVER DMA CONTROL + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_PAGE + Transceiver DMA Page Selector + 0 + 4 + read-write + + + DMA_PAGE_0 + DMA idle + 0 + + + DMA_PAGE_1 + RXDIG-IQ: Select from (mixer, decimator, pd channel filter, src, cfo-mixer, demod chan filter) in RXDIG. 11bit signed data, MSB aligned + 0x1 + + + DMA_PAGE_2 + RXDIG-IQ-ALT: Same as above + signals on unused LSBs : {antenna switch, GenLL or 802.15.4LL CRC_FAIL} on "Q" LSBs, {preamble_found, aa_sfd_matched} on "I" LSBs. + 0x2 + + + DMA_PAGE_3 + ADC-IQ: 11bit samples are MSB aligned in each 16bit half-word + 0x3 + + + DMA_PAGE_4 + PHASE: Select from (sync phase, demod phase) within RXDIG. MSB aligned + 0x4 + + + DMA_PAGE_5 + RSSI-PHASE: select from 8bit Narrowband (rssi, rssi raw, lqi, snr, noise) and Wideband(rssi, rssi raw) + 8bit high-resolution PHASE + 0x5 + + + DMA_PAGE_6 + MAG-PHASE: RSSI magnitude + 8bit high-resolution PHASE + 0x6 + + + DMA_PAGE_7 + GEN4-PHY + 0x7 + + + DMA_PAGE_8 + DETERMINISTIC + 0x8 + + + + + DMA_START_TRG + DMA Start Trigger Selector + 4 + 4 + read-write + + + DMA_START_TRG_0 + no trigger + 0 + + + DMA_START_TRG_1 + PHY: pd found + 0x1 + + + DMA_START_TRG_2 + PHY: aa found + 0x2 + + + DMA_START_TRG_3 + Zigbee_PHY: pd found + 0x3 + + + DMA_START_TRG_4 + Zigbee_PHY: sfd detect + 0x4 + + + DMA_START_TRG_5 + RXDIG: agc_gain_chg + 0x5 + + + DMA_START_TRG_6 + TSM: rx_dig_en + 0x6 + + + DMA_START_TRG_7 + TSM: tsm_irq0_start_trig + 0x7 + + + DMA_START_TRG_8 + CRC pass + 0x8 + + + DMA_START_TRG_9 + CRC done (Not used for 15.4LL) + 0x9 + + + DMA_START_TRG_10 + Localization control: pattern match + 0xA + + + DMA_START_TRG_11 + GenericLL: cte_present, Bluetooth LE: cte_en + 0xB + + + DMA_START_TRG_12 + Ranging sequence manager: dma_trigger + 0xC + + + + + DMA_START_EDGE + DMA Start Trigger Edge Selector + 8 + 1 + read-write + + + DMA_START_EDGE_0 + Trigger fires on a rising edge of the selected trigger source + 0 + + + DMA_START_EDGE_1 + Trigger fires on a falling edge of the selected trigger source + 0x1 + + + + + DMA_DEC + DMA Decimation Rate + 10 + 2 + read-write + + + DMA_DEC_0 + Data is captured on every data valid + 0 + + + DMA_DEC_1 + Data is captured on every 2nd data valid + 0x1 + + + DMA_DEC_2 + Data is captured on every 4th data valid + 0x2 + + + DMA_DEC_3 + Data is captured on every 8th data valid + 0x3 + + + + + DMA_START_DLY + DMA Start Trigger Delay + 12 + 11 + read-write + + + DMA_EN + DMA Enable + 23 + 1 + read-write + + + DMA_AA_TRIGGERED + DMA Access Address triggered + 24 + 1 + read-only + + + DMA_START_TRIGGERED + DMA Start Trigger Occurred + 25 + 1 + read-only + + + DMA_SIGNAL_VALID_MASK_EN + DMA Signal Valid Mask Enable + 31 + 1 + read-write + + + DMA_SIGNAL_VALID_MASK_EN_0 + Disable use of dma_signal_valid_mask. + 0 + + + DMA_SIGNAL_VALID_MASK_EN_1 + Enable use of dma_signal_valid_mask. + 0x1 + + + + + + + DBG_RAM_CTRL + DBG Ram control register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_PAGE + Packet RAM Debug Page Selector + 0 + 3 + read-write + + + DBG_PAGE_0 + DMA idle + 0 + + + DBG_PAGE_1 + RXDIG-IQ: Select from (mixer, decimator, pd channel filter, src, cfo-mixer, demod chan filter) in RXDIG. 11bit signed data, MSB aligned + 0x1 + + + DBG_PAGE_2 + RXDIG-IQ-ALT: Same as above + signals on unused LSBs : {antenna switch, GenLL or 802.15.4LL CRC_FAIL} on "Q" LSBs, {preamble_found, aa_sfd_matched} on "I" LSBs. + 0x2 + + + DBG_PAGE_3 + ADC-IQ: 11bit samples are MSB aligned in each 16bit half-word + 0x3 + + + DBG_PAGE_4 + PHASE: Select from (sync phase, demod phase) within RXDIG. MSB aligned + 0x4 + + + DBG_PAGE_5 + RSSI-PHASE: select from 8bit Narrowband (rssi, rssi raw, lqi, snr, noise) and Wideband(rssi, rssi raw) + 8bit high-resolution PHASE + 0x5 + + + DBG_PAGE_6 + MAG-PHASE: RSSI magnitude + 8bit high-resolution PHASE + 0x6 + + + DBG_PAGE_7 + GEN4-PHY + 0x7 + + + + + DBG_SIGNAL_VALID_MASK_EN + DBG Signal Valid Mask Enable + 3 + 1 + read-write + + + DBG_SIGNAL_VALID_MASK_EN_0 + Disable use of dbg_signal_valid_mask. + 0 + + + DBG_SIGNAL_VALID_MASK_EN_1 + Enable use of dbg_signal_valid_mask. + 0x1 + + + + + DBG_START_TRG + DMA Start Trigger Selector + 4 + 4 + read-write + + + DBG_START_TRG_0 + no trigger + 0 + + + DBG_START_TRG_1 + PHY: pd found + 0x1 + + + DBG_START_TRG_2 + PHY: aa found + 0x2 + + + DBG_START_TRG_3 + Zigbee_PHY: pd found + 0x3 + + + DBG_START_TRG_4 + Zigbee_PHY: sfd detect + 0x4 + + + DBG_START_TRG_5 + RXDIG: agc_gain_chg + 0x5 + + + DBG_START_TRG_6 + TSM: rx_dig_en + 0x6 + + + DBG_START_TRG_7 + TSM: tsm_irq0_start_trig + 0x7 + + + DBG_START_TRG_8 + CRC pass + 0x8 + + + DBG_START_TRG_9 + CRC done (Not used for 15.4LL) + 0x9 + + + DBG_START_TRG_10 + Localization control: pattern match + 0xA + + + DBG_START_TRG_11 + GenericLL: cte_present, Bluetooth LE: cte_en + 0xB + + + DBG_START_TRG_12 + Ranging sequence manager: dma_trigger + 0xC + + + + + DBG_START_EDGE + DBG Start Trigger Edge Selector + 8 + 1 + read-write + + + DBG_START_EDGE_0 + Trigger fires on a rising edge of the selected trigger source + 0 + + + DBG_START_EDGE_1 + Trigger fires on a falling edge of the selected trigger source + 0x1 + + + + + DBG_STOP_EDGE + DBG Stop Trigger Edge Selector + 9 + 1 + read-write + + + DBG_STOP_EDGE_0 + Trigger stops on a rising edge of the selected trigger source + 0 + + + DBG_STOP_EDGE_1 + Trigger stops on a falling edge of the selected trigger source + 0x1 + + + + + DBG_DEC + DBG Decimation Rate + 10 + 2 + read-write + + + DBG_DEC_0 + Data is captured on every data valid + 0 + + + DBG_DEC_1 + Data is captured on every 2nd data valid + 0x1 + + + DBG_DEC_2 + Data is captured on every 4th data valid + 0x2 + + + DBG_DEC_3 + Data is captured on every 8th data valid + 0x3 + + + + + DBG_START_DLY + DBG Start Trigger Delay + 12 + 11 + read-write + + + DBG_EN + DBG Enable + 23 + 1 + read-write + + + DBG_AA_TRIGGERED + DBG Access Address triggered + 24 + 1 + read-only + + + DBG_START_TRIGGERED + DBG Start Trigger Occurred + 25 + 1 + read-only + + + DBG_STOP_TRIGGERED + DBG Stop Trigger Occurred + 26 + 1 + read-only + + + DBG_RAM_FULL + DBG_RAM_FULL + 27 + 1 + read-only + + + DBG_RAM_FULL_0 + Packet RAM is not full + 0 + + + DBG_RAM_FULL_1 + Packet RAM is full + 0x1 + + + + + DBG_STOP_TRG + Packet RAM Debug Stop Trigger Selector + 28 + 4 + read-write + + + DBG_STOP_TRG_0 + no trigger + 0 + + + DBG_STOP_TRG_1 + PHY: pd found + 0x1 + + + DBG_STOP_TRG_2 + PHY: aa found + 0x2 + + + DBG_STOP_TRG_3 + Zigbee_PHY: pd found + 0x3 + + + DBG_STOP_TRG_4 + Zigbee_PHY: sfd detect + 0x4 + + + DBG_STOP_TRG_5 + RXDIG: agc_gain_chg + 0x5 + + + DBG_STOP_TRG_6 + TSM: rx_dig_en + 0x6 + + + DBG_STOP_TRG_7 + TSM: tsm_irq1_stop_trig + 0x7 + + + DBG_STOP_TRG_8 + CRC fail + 0x8 + + + DBG_STOP_TRG_9 + CRC done (Not used for 15.4LL) + 0x9 + + + DBG_STOP_TRG_10 + RBME: error + 0xA + + + DBG_STOP_TRG_11 + GenericLL header fail + 0xB + + + DBG_STOP_TRG_12 + PLL unlock + 0xC + + + + + + + DBG_RAM_ADDR + DBG RAM ADDRESS + 0x14 + 32 + read-write + 0x47FC0000 + 0xFFFFFFFF + + + DBG_RAM_FIRST + DBG RAM First Address + 0 + 15 + read-write + + + DBG_RAM_LAST + DBG RAM Last Address + 16 + 15 + read-write + + + + + DBG_RAM_STOP_ADDR + DBG RAM STOP ADDRESS + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBG_RAM_STOP + DBG RAM Stop Address + 0 + 15 + read-only + + + + + LDO_TRIM_0 + LDO TRIM Configuration 0 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LDO_PLL_TRIM_OFFSET + LDO PLL TRIM Offset + 0 + 4 + read-write + + + LDO_VCO_TRIM_OFFSET + LDO VCO TRIM Offset + 4 + 4 + read-write + + + LDO_RXTXLF_TRIM_OFFSET + LDO RXTXLF TRIM Offset + 8 + 4 + read-write + + + LDO_RXTXHF_TRIM_OFFSET + LDO RXTXHF TRIM Offset + 12 + 4 + read-write + + + LDO_TRIM_SMPL_DLY + LDO TRIM Sample Delay + 16 + 2 + read-write + + + LDO_TRIM_CMPOUT_INV + LDO TRIM CMPOUT Invert + 19 + 1 + read-write + + + LDO_CAL_TRIMSEL_OVRD + LDO_CAL_TRIMSEL Override Value + 24 + 1 + read-write + + + LDO_PLL_TRIMSEL_OVRD + LDO_PLL_TRIMSEL Override Value + 25 + 1 + read-write + + + LDO_VCO_TRIMSEL_OVRD + LDO_VCO_TRIMSEL Override Value + 26 + 1 + read-write + + + LDO_RXTXHF_TRIMSEL_OVRD + LDO_RXTXHF_TRIMSEL Override Value + 28 + 1 + read-write + + + LDO_TRIM_SAMPLE_OVRD + LDO_TRIM_SAMPLE Override Value + 29 + 1 + read-write + + + LDO_SAMPLE_TRIMSEL_OVRD_EN + LDO SAMPLE TRIMSEL Override Enable + 30 + 1 + read-write + + + + + LDO_TRIM_1 + LDO TRIM Configuration 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + LDO_PLL_TRIM_OVRD + LDO PLL TRIM Override Value + 0 + 6 + read-write + + + LDO_PLL_TRIM_OVRD_EN + LDO PLL TRIM Override Enable + 6 + 1 + read-write + + + LDO_VCO_TRIM_OVRD + LDO VCO TRIM Override Value + 8 + 6 + read-write + + + LDO_VCO_TRIM_OVRD_EN + VCO TRIM Override Enable + 14 + 1 + read-write + + + LDO_RXTXLF_TRIM_OVRD + LDO RXTXLF TRIM Override Value + 16 + 6 + read-write + + + LDO_RXTXLF_TRIM_OVRD_EN + LDO RXTXLF TRIM Override Enable + 22 + 1 + read-write + + + LDO_RXTXHF_TRIM_OVRD + LDO RXTXHF TRIM Override Value + 24 + 6 + read-write + + + LDO_RXTXHF_TRIM_OVRD_EN + LDO RXTXHF TRIM Override Enable + 30 + 1 + read-write + + + + + LDO_TRIM_RES_0 + RF Analog LDO Trim Res Control 0 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + LDO_PLL_TRIM + LDO_PLL_TRIM Result + 0 + 6 + read-only + + + LDO_VCO_TRIM + LDO_VCO_TRIM Result + 8 + 6 + read-only + + + LDO_RXTXLF_TRIM + LDO_RXTXLF_TRIM Result + 16 + 6 + read-only + + + LDO_RXTXHF_TRIM + LDO_RXTXHF_TRIM Result + 24 + 6 + read-only + + + + + LDO_TRIM_RES_1 + RF Analog LDO Trim Res Control 1 + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + LDO_CAL_TRIM + LDO_CAL_TRIM Result + 0 + 6 + read-only + + + LDO_TRIM_CMPOUT + LDO TRIM CMPOUT + 8 + 1 + read-only + + + + + LCL_CFG0 + LCL CTRL CFG 0 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + LCL_EN + Localization Control Module Enable + 0 + 1 + read-write + + + TX_LCL_EN + Enable Switching in TX + 1 + 1 + read-write + + + RX_LCL_EN + Enable Switching in RX + 2 + 1 + read-write + + + LANT_INV + Invert Antenna Switch Output + 3 + 1 + read-write + + + COMP_EN + Pattern Matching Enable + 4 + 1 + read-write + + + COMP_TX_EN + Pattern Matching Enable in TX + 5 + 1 + read-write + + + SW_TRIG + Software Trigger. Can be used with either RX or TX + 6 + 1 + read-write + + + LANT_SW_WIGGLE + LANT_SW Wiggle + 7 + 1 + read-write + + + PM_NUM_BYTES + Number of Bytes to Match + 8 + 2 + read-write + + + PM_NUM_BYTES_0 + 4 bytes + 0 + + + PM_NUM_BYTES_1 + 5 bytes + 0x1 + + + PM_NUM_BYTES_2 + 6 bytes + 0x2 + + + PM_NUM_BYTES_3 + 8 bytes + 0x3 + + + + + LANT_BLOCK_TX + Block LANT_SW for TX + 10 + 1 + read-write + + + LANT_BLOCK_RX + Block LANT_SW for RX + 11 + 1 + read-write + + + CTE_DUR + Total Switching Duration + 16 + 9 + read-write + + + LCL_GPIO_SEL + Localization GPIO Select + 30 + 1 + read-write + + + LCL_MODE + Localization Mode + 31 + 1 + read-write + + + LCL_MODE_0 + GenLL configuration. + 0 + + + LCL_MODE_1 + Bluetooth LE LL configuration. + 0x1 + + + + + + + LCL_CFG1 + LCL CTRL CFG 1 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + M_ON_DELAY + M on Delay + 0 + 10 + read-write + + + N_ON_DELAY + N on Delay + 12 + 4 + read-write + + + LANT_SW_IE + Localization Antenna Switch Interrupt Enable + 30 + 1 + read-write + + + LANT_SW_IE_0 + Localization Antenna Switch interrupt disabled + 0 + + + LANT_SW_IE_1 + Localization Antenna Switch interrupt enabled + 0x1 + + + + + LANT_SW_FLAG + Localization Antenna Switch Flag + 31 + 1 + read-write + oneToClear + + + + + LCL_TX_CFG0 + LCL CTRL TX CONFIG0 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DELAY + Interval delay before TX switching begins. + 0 + 11 + read-write + + + TX_DELAY_OFF + Fine sample delay after TX_DELAY. + 16 + 5 + read-write + + + + + LCL_TX_CFG1 + LCL CTRL TX CONFIG1 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SPINT + Number of TX Samples that define the length of an Interval, where 0=1sample, 1=2sample, etc. + 0 + 5 + read-write + + + TX_ANT_TRIG_SEL + Selects Trigger for TX + 5 + 3 + read-write + + + TX_ANT_TRIG_SEL_0 + Software Trigger + 0 + + + TX_ANT_TRIG_SEL_1 + LCL Pattern Found + 0x1 + + + TX_ANT_TRIG_SEL_2 + CRC Complete + 0x2 + + + TX_ANT_TRIG_SEL_3 + PA Warmup Complete + 0x3 + + + TX_ANT_TRIG_SEL_4 + RBME tx_done_pre + 0x4 + + + TX_ANT_TRIG_SEL_5 + Bluetooth LE cte_en + 0x5 + + + TX_ANT_TRIG_SEL_6 + Ranging sequence manager lcl_tx_trigger + 0x6 + + + + + TX_LO_PER + Primary Number of intervals for antenna LOW + 12 + 5 + read-write + + + TX_HI_PER + Primary Number of intervals for antenna HIGH + 17 + 5 + read-write + + + TX_LO_PER_1 + Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM. + 22 + 5 + read-write + + + TX_HI_PER_1 + Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM. + 27 + 5 + read-write + + + + + LCL_TX_CFG2 + LCL CTRL TX CONFIG2 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_LO_PER_2 + Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM. + 12 + 5 + read-write + + + TX_HI_PER_2 + Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM. + 17 + 5 + read-write + + + TX_LO_PER_3 + Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM. + 22 + 5 + read-write + + + TX_HI_PER_3 + Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM. + 27 + 5 + read-write + + + + + LCL_RX_CFG0 + LCL CTRL RX CONFIG0 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_DELAY + Interval delay before RX switching begins. + 0 + 11 + read-write + + + RX_DELAY_OFF + Fine sample delay after RX_DELAY. + 16 + 5 + read-write + + + + + LCL_RX_CFG1 + LCL CTRL RX CONFIG1 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SPINT + Number of RX Samples that define the length of an Interval, where 0=1sample, 1=2sample, etc. + 0 + 5 + read-write + + + RX_ANT_TRIG_SEL + Selects Trigger for RX + 5 + 3 + read-write + + + RX_ANT_TRIG_SEL_0 + Software Trigger + 0 + + + RX_ANT_TRIG_SEL_1 + LCL Pattern Found + 0x1 + + + RX_ANT_TRIG_SEL_2 + CRC Complete + 0x2 + + + RX_ANT_TRIG_SEL_3 + CRC Pass + 0x3 + + + RX_ANT_TRIG_SEL_4 + GenericLL: cte_present, Bluetooth LE: cte_en + 0x4 + + + RX_ANT_TRIG_SEL_5 + aa_fnd_to_ll + 0x5 + + + RX_ANT_TRIG_SEL_6 + Ranging sequence manager lcl_rx_trigger + 0x6 + + + + + RX_LO_PER + Primary Number of intervals for antenna LOW + 12 + 5 + read-write + + + RX_HI_PER + Primary Number of intervals for antenna HIGH + 17 + 5 + read-write + + + RX_LO_PER_1 + Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM. + 22 + 5 + read-write + + + RX_HI_PER_1 + Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM. + 27 + 5 + read-write + + + + + LCL_RX_CFG2 + LCL CTRL RX CONFIG2 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_LO_PER_2 + Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM. + 12 + 5 + read-write + + + RX_HI_PER_2 + Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM. + 17 + 5 + read-write + + + RX_LO_PER_3 + Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM. + 22 + 5 + read-write + + + RX_HI_PER_3 + Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM. + 27 + 5 + read-write + + + + + LCL_PM_MSB + LCL CTRL PM MSB + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP_PATTERN_MSB + Upper bytes of pattern to be matched, bits 63:32 + 0 + 32 + read-write + + + + + LCL_PM_LSB + LCL CTRL PM LSB + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP_PATTERN_LSB + Lower bytes of pattern to be matched, bits 31:0 + 0 + 32 + read-write + + + + + LCL_GPIO_CTRL0 + LCL GPIO CTRL 0 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_0 + GPIO antenna state LUT entry + 0 + 4 + read-write + + + LUT_1 + GPIO antenna state LUT entry + 4 + 4 + read-write + + + LUT_2 + GPIO antenna state LUT entry + 8 + 4 + read-write + + + LUT_3 + GPIO antenna state LUT entry + 12 + 4 + read-write + + + LUT_4 + GPIO antenna state LUT entry + 16 + 4 + read-write + + + LUT_5 + GPIO antenna state LUT entry + 20 + 4 + read-write + + + LUT_6 + GPIO antenna state LUT entry + 24 + 4 + read-write + + + LUT_7 + GPIO antenna state LUT entry + 28 + 4 + read-write + + + + + LCL_GPIO_CTRL1 + LCL GPIO CTRL 1 + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_8 + GPIO antenna state LUT entry + 0 + 4 + read-write + + + LUT_9 + GPIO antenna state LUT entry + 4 + 4 + read-write + + + LUT_10 + GPIO antenna state LUT entry + 8 + 4 + read-write + + + LUT_11 + GPIO antenna state LUT entry + 12 + 4 + read-write + + + LUT_12 + GPIO antenna state LUT entry + 16 + 4 + read-write + + + LUT_13 + GPIO antenna state LUT entry + 20 + 4 + read-write + + + LUT_14 + GPIO antenna state LUT entry + 24 + 4 + read-write + + + LUT_15 + GPIO antenna state LUT entry + 28 + 4 + read-write + + + + + LCL_GPIO_CTRL2 + LCL GPIO CTRL 2 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_16 + GPIO antenna state LUT entry + 0 + 4 + read-write + + + LUT_17 + GPIO antenna state LUT entry + 4 + 4 + read-write + + + LUT_18 + GPIO antenna state LUT entry + 8 + 4 + read-write + + + LUT_19 + GPIO antenna state LUT entry + 12 + 4 + read-write + + + LUT_20 + GPIO antenna state LUT entry + 16 + 4 + read-write + + + LUT_21 + GPIO antenna state LUT entry + 20 + 4 + read-write + + + LUT_22 + GPIO antenna state LUT entry + 24 + 4 + read-write + + + LUT_23 + GPIO antenna state LUT entry + 28 + 4 + read-write + + + + + LCL_GPIO_CTRL3 + LCL GPIO CTRL 3 + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_24 + GPIO antenna state LUT entry + 0 + 4 + read-write + + + LUT_25 + GPIO antenna state LUT entry + 4 + 4 + read-write + + + LUT_26 + GPIO antenna state LUT entry + 8 + 4 + read-write + + + LUT_27 + GPIO antenna state LUT entry + 12 + 4 + read-write + + + LUT_28 + GPIO antenna state LUT entry + 16 + 4 + read-write + + + LUT_29 + GPIO antenna state LUT entry + 20 + 4 + read-write + + + LUT_30 + GPIO antenna state LUT entry + 24 + 4 + read-write + + + LUT_31 + GPIO antenna state LUT entry + 28 + 4 + read-write + + + + + LCL_GPIO_CTRL4 + LCL GPIO CTRL 4 + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_WRAP_PTR + Wrap point for the LUT table in generating the 4 antenna GPIO wire states. + 0 + 5 + read-write + + + + + LCL_DMA_MASK_DELAY + LCL_DMA_MASK_DELAY + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_MASK_DELAY_OFF + DMA_MASK_DELAY_OFF + 0 + 5 + read-write + + + DMA_MASK_DELAY + DMA_MASK_DELAY + 5 + 11 + read-write + + + + + LCL_DMA_MASK_PERIOD + LCL_DMA_MASK_PERIOD + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_MASK_REF_PER + DMA_MASK_REF_PER + 0 + 5 + read-write + + + + + RSM_CSR + Ranging Sequence Manager Control and Status + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSM_IRQ_IP1_EN + RSM_IRQ_IP1_EN + 0 + 1 + read-write + + + RSM_IRQ_IP1 + RSM_IRQ_IP1 Flag + 1 + 1 + read-write + oneToClear + + + RSM_IRQ_IP2_EN + RSM_IRQ_IP2_EN + 2 + 1 + read-write + + + RSM_IRQ_IP2 + RSM_IRQ_IP2 Flag + 3 + 1 + read-write + oneToClear + + + RSM_IRQ_FC_EN + RSM_IRQ_FC_EN + 4 + 1 + read-write + + + RSM_IRQ_FC + RSM_IRQ_FC Flag + 5 + 1 + read-write + oneToClear + + + RSM_IRQ_EOS_EN + RSM_IRQ_EOS_EN + 6 + 1 + read-write + + + RSM_IRQ_EOS + RSM_IRQ_EOS Flag + 7 + 1 + read-write + oneToClear + + + RSM_IRQ_ABORT_EN + RSM_IRQ_ABORT_EN + 8 + 1 + read-write + + + RSM_IRQ_ABORT + RSM_IRQ_ABORT Flag + 9 + 1 + read-write + oneToClear + + + RSM_STATE + RSM_STATE + 16 + 5 + read-only + + + RSM_STATE_0 + IDLE + 0 + + + RSM_STATE_1 + DELAY. Used only for the trigger delay in SQTE + 0x1 + + + RSM_STATE_2 + EXT_TX (Extend TX). Used only for PDE + 0x2 + + + RSM_STATE_3 + EXT_RX (Extend RX). Used only for PDE + 0x3 + + + RSM_STATE_4 + WU (Warmup). Used only for SQTE + 0x4 + + + RSM_STATE_5 + DT_TX (Packet TX). Used only for SQTE + 0x5 + + + RSM_STATE_6 + DT_RX (Packet RX). Used only for SQTE + 0x6 + + + RSM_STATE_7 + DT_RX_SYNC (Packet RX Sync). Used only for SQTE + 0x7 + + + RSM_STATE_8 + FM_TX (Frequency Measurement TX). Used only for SQTE + 0x8 + + + RSM_STATE_9 + FM_RX (Frequency Measurement RX). Used only for SQTE + 0x9 + + + RSM_STATE_10 + PM_TX (Phase Measurement TX). + 0xA + + + RSM_STATE_11 + PM_RX (Phase Measurement RX). + 0xB + + + RSM_STATE_12 + IP1_RX2TX (Interlude Period 1 RX2TX). Used only for SQTE + 0xC + + + RSM_STATE_13 + IP1_TX2RX (Interlude Period 1 TX2RX). Used only for SQTE + 0xD + + + RSM_STATE_14 + S_RX2RX (Short Period RX2RX). Used only for SQTE + 0xE + + + RSM_STATE_15 + S_TX2TX (Short Period TX2TX). Used only for SQTE + 0xF + + + RSM_STATE_16 + IP2_RX2TX (Interlude Period 2 RX2TX). + 0x10 + + + RSM_STATE_17 + IP2_TX2RX (Interlude Period 2 TX2RX). + 0x11 + + + RSM_STATE_18 + FC_RX2TX (Frequency Change RX2TX). + 0x12 + + + RSM_STATE_19 + FC_TX2RX (Frequency Change TX2RX). + 0x13 + + + RSM_STATE_20 + WD (Warmdown) + 0x14 + + + + + RSM_STEP_FORMAT + RSM_STEP_FORMAT + 21 + 2 + read-only + + + RSM_CURRENT_STEPS + RSM_CURRENT_STEPS + 24 + 8 + read-only + + + + + RSM_CTRL0 + Ranging Sequence Manager Control + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSM_MODE + RSM_MODE + 0 + 1 + read-write + + + RSM_MODE_0 + SQTE + 0 + + + RSM_MODE_1 + PDE + 0x1 + + + + + RSM_RATE + RSM_RATE + 1 + 1 + read-write + + + RSM_RATE_0 + 1Mbps + 0 + + + RSM_RATE_1 + 2Mbps + 0x1 + + + + + RSM_RX_EN + RSM_RX_EN + 2 + 1 + read-write + + + RSM_TX_EN + RSM_TX_EN + 3 + 1 + read-write + + + RSM_FAST_IP_RX_WU + RSM_FAST_IP_RX_WU + 4 + 1 + read-write + + + RSM_FAST_IP_TX_WU + RSM_FAST_IP_TX_WU + 5 + 1 + read-write + + + RSM_FAST_FC_RX_WU + RSM_FAST_FC_RX_WU + 6 + 1 + read-write + + + RSM_FAST_FC_TX_WU + RSM_FAST_FC_TX_WU + 7 + 1 + read-write + + + RSM_SW_ABORT + RSM_SW_ABORT + 8 + 1 + read-write + + + RSM_TRIG_SEL + RSM_TRIG_SEL + 10 + 3 + read-write + + + RSM_TRIG_SEL_0 + software trigger + 0 + + + RSM_TRIG_SEL_1 + crc_vld + 0x1 + + + RSM_TRIG_SEL_2 + aa_fnd_to_ll + 0x2 + + + RSM_TRIG_SEL_3 + tx_dig_en + 0x3 + + + RSM_TRIG_SEL_4 + seq_spare3 + 0x4 + + + RSM_TRIG_SEL_5 + lcl pattern_match + 0x5 + + + + + RSM_TRIG_DLY + RSM_TRIG_DLY + 13 + 11 + read-write + + + RSM_STEPS + RSM_FREQUENCY_STEP + 24 + 8 + read-write + + + + + RSM_CTRL1 + Ranging Sequence Manager Control + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSM_T_FM0 + RSM_T_FM0 + 0 + 5 + read-write + + + RSM_T_FM1 + RSM_T_FM1 + 5 + 5 + read-write + + + RSM_T_FC + RSM_T_FC + 11 + 5 + read-write + + + RSM_T_IP1 + RSM_T_IP1 + 16 + 5 + read-write + + + RSM_T_IP2 + RSM_T_IP2 + 21 + 5 + read-write + + + RSM_T_S + RSM_T_S + 26 + 2 + read-write + + + + + RSM_CTRL2 + Ranging Sequence Manager Control + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + RSM_T_PM0 + RSM_T_PM0 + 0 + 6 + read-write + + + RSM_T_PM1 + RSM_T_PM1 + 6 + 6 + read-write + + + RSM_T_PM2 + RSM_T_PM2 + 12 + 6 + read-write + + + RSM_T_PM3 + RSM_T_PM3 + 18 + 6 + read-write + + + RSM_ACTIVE_OVRD_LCL + RSM_ACTIVE_OVRD_LCL + 26 + 1 + read-write + + + RSM_ACTIVE_OVRD_EN_LCL + RSM_ACTIVE_OVRD_EN_LCL + 27 + 1 + read-write + + + RSM_ACTIVE_OVRD_EN_LCL_0 + Disable override rsm_active of LCL_CTRL module. + 0 + + + RSM_ACTIVE_OVRD_EN_LCL_1 + Enable override rsm_active of LCL_CTRL module. + 0x1 + + + + + RSM_ACTIVE_OVRD_TXDIG + RSM_ACTIVE_OVRD_TXDIG + 28 + 1 + read-write + + + RSM_ACTIVE_OVRD_EN_TXDIG + RSM_ACTIVE_OVRD_EN_TXDIG + 29 + 1 + read-write + + + RSM_ACTIVE_OVRD_EN_TXDIG_0 + Disable override rsm_active of TXDIG module. + 0 + + + RSM_ACTIVE_OVRD_EN_TXDIG_1 + Enable override rsm_active of TXDIG module. + 0x1 + + + + + RSM_ACTIVE_OVRD_RXDIG + RSM_ACTIVE_OVRD_RXDIG + 30 + 1 + read-write + + + RSM_ACTIVE_OVRD_EN_RXDIG + RSM_ACTIVE_OVRD_EN_RXDIG + 31 + 1 + read-write + + + RSM_ACTIVE_OVRD_EN_RXDIG_0 + Disable override rsm_active of RXDIG module. + 0 + + + RSM_ACTIVE_OVRD_EN_RXDIG_1 + Enable override rsm_active of RXDIG module. + 0x1 + + + + + + + RSM_CTRL3 + Ranging Sequence Manager Control + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSM_DT_RX_SYNC_DLY + RSM_DT_RX_SYNC_DLY + 0 + 4 + read-write + + + RSM_DT_RX_SYNC_DIS + RSM_DT_RX_SYNC_DIS + 4 + 1 + read-write + + + RSM_AA_HAMM + RSM_AA_HAMM + 5 + 3 + read-write + + + RSM_HPM_CAL + RSM_HPM_CAL + 8 + 1 + read-write + + + RSM_CTUNE + RSM_CTUNE + 9 + 1 + read-write + + + RSM_DMA_RX_EN + RSM_DMA_RX_EN + 10 + 1 + read-write + + + RSM_RX_PHY_EN_MASK_DIS + RSM_RX_PHY_EN_MASK_DIS + 11 + 1 + read-write + + + RSM_RX_SIGNALS_MASK_DIS + RSM_RX_SIGNALS_MASK_DIS + 12 + 1 + read-write + + + RSM_SEQ_RCCAL_PUP_MASK_DIS + RSM_SEQ_RCCAL_PUP_MASK_DIS + 13 + 1 + read-write + + + RSM_DMA_DUR + DMA Duration + 16 + 10 + read-write + + + + + RSM_CTRL4 + Ranging Sequence Manager Control + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSM_DMA_DLY0 + DMA Delay 0 + 0 + 8 + read-write + + + RSM_DMA_DLY + DMA Delay + 8 + 8 + read-write + + + RSM_DMA_DUR0 + DMA Duration 0 + 16 + 10 + read-write + + + + + RF_DFT_CTRL + RF DFT CTRL + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + RADIO_DFT_MODE + Radio DFT mode control + 0 + 4 + read-write + + + RADIO_DFT_MODE_0 + Normal Mode + 0 + + + RADIO_DFT_MODE_1 + Carrier Only + 0x1 + + + RADIO_DFT_MODE_2 + Pattern Register + 0x2 + + + RADIO_DFT_MODE_3 + LFSR + 0x3 + + + RADIO_DFT_MODE_4 + RAM Modulation + 0x4 + + + RADIO_DFT_MODE_10 + Coarse Tune BIST, no modulation + 0xA + + + RADIO_DFT_MODE_11 + PLL Locking BIST, no modulation + 0xB + + + RADIO_DFT_MODE_12 + HPM DAC Cal BIST, no modulation + 0xC + + + + + + + 8 + 0x4 + IPS_FO_ADDR[%s] + IPS FAST OVERWRITE ADDRESS + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + 8 + 0x4 + IPS_FO_DRS0_DATA[%s] + IPS FAST OVERWRITE DRS0 DATA + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + 8 + 0x4 + IPS_FO_DRS1_DATA[%s] + IPS FAST OVERWRITE DRS1 DATA + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + + + TX_PACKET_RAM + RADIO_PACKET_RAM + TX_PACKET_RAM + 0x48A08000 + + 0 + 0x1000 + registers + + + + 1024 + 0x4 + PACKET_RAM_[%s] + Shared Packet RAM for multiple Link Layer usage. + 0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + + + RX_PACKET_RAM + RADIO_PACKET_RAM + RX_PACKET_RAM + 0x48A09000 + + 0 + 0x800 + registers + + + + 512 + 0x4 + PACKET_RAM_[%s] + Shared Packet RAM for multiple Link Layer usage. + 0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + + + ITM + Instrumentation Trace Macrocell Registers + ITM + ITM_ + 0xE0000000 + + 0 + 0x1000 + registers + + + + STIM0_READ + Stimulus Port Register 0 (for reading) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM0_WRITE + Stimulus Port Register 0 (for writing) + STIM0_READ_STIM0_WRITE + 0 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM1_READ + Stimulus Port Register 1 (for reading) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM1_WRITE + Stimulus Port Register 1 (for writing) + STIM1_READ_STIM1_WRITE + 0x4 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM2_READ + Stimulus Port Register 2 (for reading) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM2_WRITE + Stimulus Port Register 2 (for writing) + STIM2_READ_STIM2_WRITE + 0x8 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM3_READ + Stimulus Port Register 3 (for reading) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM3_WRITE + Stimulus Port Register 3 (for writing) + STIM3_READ_STIM3_WRITE + 0xC + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM4_READ + Stimulus Port Register 4 (for reading) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM4_WRITE + Stimulus Port Register 4 (for writing) + STIM4_READ_STIM4_WRITE + 0x10 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM5_READ + Stimulus Port Register 5 (for reading) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM5_WRITE + Stimulus Port Register 5 (for writing) + STIM5_READ_STIM5_WRITE + 0x14 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM6_READ + Stimulus Port Register 6 (for reading) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM6_WRITE + Stimulus Port Register 6 (for writing) + STIM6_READ_STIM6_WRITE + 0x18 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM7_READ + Stimulus Port Register 7 (for reading) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM7_WRITE + Stimulus Port Register 7 (for writing) + STIM7_READ_STIM7_WRITE + 0x1C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM8_READ + Stimulus Port Register 8 (for reading) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM8_WRITE + Stimulus Port Register 8 (for writing) + STIM8_READ_STIM8_WRITE + 0x20 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM9_READ + Stimulus Port Register 9 (for reading) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM9_WRITE + Stimulus Port Register 9 (for writing) + STIM9_READ_STIM9_WRITE + 0x24 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM10_READ + Stimulus Port Register 10 (for reading) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM10_WRITE + Stimulus Port Register 10 (for writing) + STIM10_READ_STIM10_WRITE + 0x28 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM11_READ + Stimulus Port Register 11 (for reading) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM11_WRITE + Stimulus Port Register 11 (for writing) + STIM11_READ_STIM11_WRITE + 0x2C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM12_READ + Stimulus Port Register 12 (for reading) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM12_WRITE + Stimulus Port Register 12 (for writing) + STIM12_READ_STIM12_WRITE + 0x30 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM13_READ + Stimulus Port Register 13 (for reading) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM13_WRITE + Stimulus Port Register 13 (for writing) + STIM13_READ_STIM13_WRITE + 0x34 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM14_READ + Stimulus Port Register 14 (for reading) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM14_WRITE + Stimulus Port Register 14 (for writing) + STIM14_READ_STIM14_WRITE + 0x38 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM15_READ + Stimulus Port Register 15 (for reading) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM15_WRITE + Stimulus Port Register 15 (for writing) + STIM15_READ_STIM15_WRITE + 0x3C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM16_READ + Stimulus Port Register 16 (for reading) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM16_WRITE + Stimulus Port Register 16 (for writing) + STIM16_READ_STIM16_WRITE + 0x40 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM17_READ + Stimulus Port Register 17 (for reading) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM17_WRITE + Stimulus Port Register 17 (for writing) + STIM17_READ_STIM17_WRITE + 0x44 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM18_READ + Stimulus Port Register 18 (for reading) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM18_WRITE + Stimulus Port Register 18 (for writing) + STIM18_READ_STIM18_WRITE + 0x48 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM19_READ + Stimulus Port Register 19 (for reading) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM19_WRITE + Stimulus Port Register 19 (for writing) + STIM19_READ_STIM19_WRITE + 0x4C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM20_READ + Stimulus Port Register 20 (for reading) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM20_WRITE + Stimulus Port Register 20 (for writing) + STIM20_READ_STIM20_WRITE + 0x50 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM21_READ + Stimulus Port Register 21 (for reading) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM21_WRITE + Stimulus Port Register 21 (for writing) + STIM21_READ_STIM21_WRITE + 0x54 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM22_READ + Stimulus Port Register 22 (for reading) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM22_WRITE + Stimulus Port Register 22 (for writing) + STIM22_READ_STIM22_WRITE + 0x58 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM23_READ + Stimulus Port Register 23 (for reading) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM23_WRITE + Stimulus Port Register 23 (for writing) + STIM23_READ_STIM23_WRITE + 0x5C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM24_READ + Stimulus Port Register 24 (for reading) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM24_WRITE + Stimulus Port Register 24 (for writing) + STIM24_READ_STIM24_WRITE + 0x60 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM25_READ + Stimulus Port Register 25 (for reading) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM25_WRITE + Stimulus Port Register 25 (for writing) + STIM25_READ_STIM25_WRITE + 0x64 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM26_READ + Stimulus Port Register 26 (for reading) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM26_WRITE + Stimulus Port Register 26 (for writing) + STIM26_READ_STIM26_WRITE + 0x68 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM27_READ + Stimulus Port Register 27 (for reading) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM27_WRITE + Stimulus Port Register 27 (for writing) + STIM27_READ_STIM27_WRITE + 0x6C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM28_READ + Stimulus Port Register 28 (for reading) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM28_WRITE + Stimulus Port Register 28 (for writing) + STIM28_READ_STIM28_WRITE + 0x70 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM29_READ + Stimulus Port Register 29 (for reading) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM29_WRITE + Stimulus Port Register 29 (for writing) + STIM29_READ_STIM29_WRITE + 0x74 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM30_READ + Stimulus Port Register 30 (for reading) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM30_WRITE + Stimulus Port Register 30 (for writing) + STIM30_READ_STIM30_WRITE + 0x78 + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + STIM31_READ + Stimulus Port Register 31 (for reading) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFE + + + FIFOREADY + no description available + 0 + 1 + read-write + + + + + STIM31_WRITE + Stimulus Port Register 31 (for writing) + STIM31_READ_STIM31_WRITE + 0x7C + 32 + read-write + 0 + 0 + + + STIMULUS + Data write to the stimulus port FIFO, for forwarding as a software event packet. + 0 + 32 + read-write + + + + + TER + Trace Enable Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + STIMENA + For bit STIMENA[n], in register ITM_TERx: 0 = Stimulus port (32x + n) disabled 1 = Stimulus port (32x + n) enabled + 0 + 32 + read-write + + + + + TPR + Trace Privilege Register + 0xE40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24] + 0 + 4 + read-write + + + + + TCR + Trace Control Register + 0xE80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITMENA + no description available + 0 + 1 + read-write + + + ITMENA_0 + Disabled. + 0 + + + ITMENA_1 + Enabled. + 0x1 + + + + + TSENA + no description available + 1 + 1 + read-write + + + TSENA_0 + Disabled. + 0 + + + TSENA_1 + Enabled. + 0x1 + + + + + SYNCENA + no description available + 2 + 1 + read-write + + + SYNCENA_0 + Disabled. + 0 + + + SYNCENA_1 + Enabled. + 0x1 + + + + + TXENA + no description available + 3 + 1 + read-write + + + TXENA_0 + Disabled. + 0 + + + TXENA_1 + Enabled. + 0x1 + + + + + SWOENA + no description available + 4 + 1 + read-write + + + SWOENA_0 + Timestamp counter uses the processor system clock. + 0 + + + SWOENA_1 + Timestamp counter uses asynchronous clock from the TPIU interface. + 0x1 + + + + + TSPrescale + Local timestamp prescaler, used with the trace packet reference clock. + 8 + 2 + read-write + + + TSPrescale_0 + No prescaling. + 0 + + + TSPrescale_1 + Divide by 4. + 0x1 + + + TSPrescale_2 + Divide by 16. + 0x2 + + + TSPrescale_3 + Divide by 64. + 0x3 + + + + + GTSFREQ + Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps. + 10 + 2 + read-write + + + GTSFREQ_0 + Disable generation of global timestamps. + 0 + + + GTSFREQ_1 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles. + 0x1 + + + GTSFREQ_2 + Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles. + 0x2 + + + GTSFREQ_3 + Generate a timestamp after every packet, if the output FIFO is empty. + 0x3 + + + + + TraceBusID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a non-zero value to this field. + 16 + 7 + read-write + + + BUSY + Indicates whether the ITM is currently processing events: 0: ITM is not processing any events. 1: ITM events present and being drained. + 23 + 1 + read-only + + + BUSY_0 + ITM is not processing any events. + 0 + + + BUSY_1 + ITM events present and beeing drained. + 0x1 + + + + + + + LAR + Lock Access Register + 0xFB0 + 32 + read-write + 0 + 0 + + + WriteAccessCode + Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. + 0 + 32 + read-write + + + + + LSR + Lock Status Register + 0xFB4 + 32 + read-only + 0x1 + 0xFFFFFFFD + + + IMP + Lock mechanism is implemented. This bit always reads 1. + 0 + 1 + read-only + + + STATUS + Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. + 1 + 1 + read-only + + + s8BIT + Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. + 2 + 1 + read-only + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x3B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + DWT + Data Watchpoint and Trace Unit Registers + DWT + DWT_ + 0xE0001000 + + 0 + 0x1000 + registers + + + + CTRL + Control Register + 0 + 32 + read-write + 0 + 0xFFF001 + + + CYCCNTENA + CYCCNTENA bit. Enables CYCCNT. This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + 0 + 1 + read-write + + + CYCCNTENA_0 + Disabled. + 0 + + + CYCCNTENA_1 + Enabled. + 0x1 + + + + + POSTPRESET + POSTPRESET bits. Reload value for the POSTCNT counter. This field is UNK/SBZP if the NOCYCCNT bit is RAO. + 1 + 4 + read-write + + + POSTINIT + POSTINIT bits. Initial value for the POSTCNT counter. This field is UNK/SBZP if the NOCYCCNT bit is RAO. + 5 + 4 + read-write + + + CYCTAP + CYCTAP bit. Selects the position of the POSTCNT tap on the CYCCNT counter. This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + 9 + 1 + read-write + + + CYCTAP_0 + POSTCNT tap at CYCCNT[6]. + 0 + + + CYCTAP_1 + POSTCNT tap at CYCCNT[10]. + 0x1 + + + + + SYNCTAP + SYNCTAP bits. Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate. + 10 + 2 + read-write + + + SYNCTAP_0 + Disabled. No Synchronization packets. + 0 + + + SYNCTAP_1 + Synchronization counter tap at CYCCNT[24]. + 0x1 + + + SYNCTAP_2 + Synchronization counter tap at CYCCNT[26]. + 0x2 + + + SYNCTAP_3 + Synchronization counter tap at CYCCNT[28]. + 0x3 + + + + + PCSAMPLENA + PCSAMPLENA bit. Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation. This bit is UNK/SBZP if the NOTRCPKT bit is RAO or the NOCYCCNT bit is RAO. + 12 + 1 + read-write + + + PCSAMPLENA_0 + No Periodic PC sample packets generated. + 0 + + + PCSAMPLENA_1 + Periodic PC sample packets generated. + 0x1 + + + + + EXCTRCENA + EXCTRCENA bit. Enables generation of exception trace. This bit is UNK/SBZP if the NOTRCPKT bit is RAO. + 16 + 1 + read-write + + + EXCTRCENA_0 + Disabled. + 0 + + + EXCTRCENA_1 + Enabled. + 0x1 + + + + + CPIEVTENA + CPIEVTENA bit. Enables generation of the CPI counter overflow event. This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 17 + 1 + read-write + + + CPIEVTENA_0 + Disabled. + 0 + + + CPIEVTENA_1 + Enabled. + 0x1 + + + + + EXCEVTENA + EXCEVTENA bit. Enables generation of the Exception overhead counter overflow event. This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 18 + 1 + read-write + + + EXCEVTENA_0 + Disabled. + 0 + + + EXCEVTENA_1 + Enabled. + 0x1 + + + + + SLEEPEVTENA + SLEEPEVTENA bit. Enables generation of the Sleep counter overflow event. This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 19 + 1 + read-write + + + SLEEPEVTENA_0 + Disabled. + 0 + + + SLEEPEVTENA_1 + Enabled. + 0x1 + + + + + LSUEVTENA + LSUEVTENA bit. Enables generation of the LSU counter overflow event. This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 20 + 1 + read-write + + + LSUEVTENA_0 + Disabled. + 0 + + + LSUEVTENA_1 + Enabled. + 0x1 + + + + + FOLDEVTENA + FOLDEVTENA bit. Enables generation of the Folded-instruction counter overflow event. This bit is UNK/SBZP if the NOPRFCNT bit is RAO. + 21 + 1 + read-write + + + FOLDEVTENA_0 + Disabled. + 0 + + + FOLDEVTENA_1 + Enabled. + 0x1 + + + + + CYCEVTENA + CYCEVTENA bit. Enables POSTCNT underflow Event counter packets generation. This bit is UNK/SBZP if the NOTRCPKT bit is RAO or the NOCYCCNT bit is RAO. + 22 + 1 + read-write + + + CYCEVTENA_0 + No POSTCNT underflow packets generated. + 0 + + + CYCEVTENA_1 + POSTCNT underflow packets generated, if PCSAMPLENA set to 0. + 0x1 + + + + + NOPFRCNT + NOPFRCNT bit. Shows whether the implementation supports the profiling counters. + 24 + 1 + read-only + + + NOPFRCNT_0 + Supported. + 0 + + + NOPFRCNT_1 + Not supported. + 0x1 + + + + + NOCYCCNT + NOCYCCNT bit. Shows whether the implementation supports a cycle counter. + 25 + 1 + read-only + + + NOCYCCNT_0 + Cycle counter supported. + 0 + + + NOCYCCNT_1 + Cycle counter not supported. + 0x1 + + + + + NOEXTTRIG + NOEXTRRIG bit. Shows whether the implementation includes external match signals, CMPMATCH[N]. + 26 + 1 + read-only + + + NOEXTTRIG_0 + CMPMATCH[N] supported. + 0 + + + NOEXTTRIG_1 + CMPMATCH[N] not supported. + 0x1 + + + + + NOTRCPKT + NOTRCPKT bit. Shows whether the implementation supports trace sampling and exception tracing. If this bit is RAZ, the NOCYCCNT bit must also RAZ. + 27 + 1 + read-only + + + NOTRCPKT_0 + Trace sampling and exception tracing supported. + 0 + + + NOTRCPKT_1 + Trace sampling and exception tracing not supported. + 0x1 + + + + + NUMCOMP + NUMCOMP bits. Number of comparators implemented. A value of zero indicates no comparator support. + 28 + 4 + read-only + + + + + CYCCNT + Cycle Count Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CYCCNT + CYCCNT[31:0]. Incrementing cycle counter value. When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero. + 0 + 32 + read-write + + + + + CPICNT + CPI Count Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPICNT + CPICNT[7:0]. The base CPI counter. Counts additional cycles required to execute multi-cycle instructions, except those recorded by DWT_LSUCNT, and counts any instruction fetch stalls. + 0 + 8 + read-write + + + + + EXCCNT + Exception Overhead Count Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXCCNT + EXCCNT[7:0]. The exception overhead counter. Counts the total cycles spent in exception processing. + 0 + 8 + read-write + + + + + SLEEPCNT + Sleep Count Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPCNT + SLEEPCNT[7:0]. Sleep counter. Counts the total number of cycles that the processor is sleeping. + 0 + 8 + read-write + + + + + LSUCNT + LSU Count Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + LSUCNT + LSUCNT[7:0]. Load-store counter. Increments on any additional cycles required to execute load or store instructions. + 0 + 8 + read-write + + + + + FOLDCNT + Folded-instruction Count Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FOLDCNT + FOLDCNT[7:0]. Folded-instruction counter. Increments on each instruction that takes 0 cycles. + 0 + 8 + read-write + + + + + PCSR + Program Counter Sample Register + 0x1C + 32 + read-only + 0 + 0 + + + EIASAMPLE + EIASAMPLE[31:0]. Executed Instruction Address sample value. + 0 + 32 + read-only + + + + + COMP0 + Comparator Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK0 + Mask Register 0 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching. The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION0 + Function Register 0 + 0x28 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match. This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0]. If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + CYCMATCH + CYCMATCH bit. If the implementation supports cycle counting, enable cycle count comparison for comparator 0. If DWT_CTRL.NOCYCCNT is RAZ then this bit is UNK/SBZP. + 7 + 1 + read-write + + + CYCMATCH_0 + No comparison is performed. + 0 + + + CYCMATCH_1 + Compare DWT_COMP0 with the cycle counter, DWT_CYCCNT. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported. For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison. See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information. If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator. When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1. If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + COMP1 + Comparator Register 1 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK1 + Mask Register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching. The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION1 + Function Register 1 + 0x38 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match. This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0]. If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported. For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison. See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information. If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator. When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1. If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + COMP2 + Comparator Register 2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK2 + Mask Register 2 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching. The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION2 + Function Register 2 + 0x48 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match. This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0]. If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported. For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison. See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information. If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator. When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1. If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + COMP3 + Comparator Register 3 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + COMP[31:0]. Reference value for comparison. + 0 + 32 + read-write + + + + + MASK3 + Mask Register 3 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK[4:0]. The size of the ignore mask, 0-31 bits, applied to address range matching. The maximum mask size is IMPLEMENTATION DEFINED. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. + 0 + 5 + read-write + + + + + FUNCTION3 + Function Register 3 + 0x58 + 32 + read-write + 0 + 0xFFFFFFDF + + + FUNCTION + FUNCTION[3:0]. Selects action taken on comparator match. This field resets to zero. + 0 + 4 + read-write + + + EMITRANGE + EMITRANGE bit. If the implementation supports trace sampling, enables generation of Data trace address offset packets, that hold Daddr[15:0]. If DWT_CTRL.NOTRCPKT is RAZ then this bit is UNK/SBZP. + 5 + 1 + read-write + + + EMITRANGE_0 + Data trace address offset packets disabled. + 0 + + + EMITRANGE_1 + Enable Data trace address offset packet generation. + 0x1 + + + + + DATAVMATCH + DATAVMATCH bit. Enables data value comparison, if supported. For comparator 0, when the CYCMATCH is set to 1, DATAVMATCH must be set to 0 for it to perform cycle count comparison. See LNK1ENA, DATAVSIZE, DATAVADDR0 and DATAVADDR1 for related information. If the implementation does not support data value comparison this bit is RAZ/WI. + 8 + 1 + read-write + + + DATAVMATCH_0 + Perform address comparison. + 0 + + + DATAVMATCH_1 + Perform data value comparison. + 0x1 + + + + + LNK1ENA + LNK1ENA bit. Indicates whether the implementation supports use of a second linked comparator. When LNK1ENA is RAO, the DATAVADDR1 field specifies the comparator to use as the second linked comparator. + 9 + 1 + read-only + + + LNK1ENA_0 + Second linked comparator not supported. + 0 + + + LNK1ENA_1 + Second linked comparator supported. + 0x1 + + + + + DATAVSIZE + DATAVSIZE[1:0]. For data value matching, specifies the size of the required data comparison. + 10 + 2 + read-write + + + DATAVSIZE_0 + Byte. + 0 + + + DATAVSIZE_1 + Halfword. + 0x1 + + + DATAVSIZE_2 + Word. + 0x2 + + + + + DATAVADDR0 + DATAVADDR0[3:0]. When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison. The DWT unit ignores the value of this field if the DATAVMATCH bit is set to 0. + 12 + 4 + read-write + + + DATAVADDR1 + DATAVADDR1[3:0]. When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. The DWT unit ignores the value of this field unless the LNK1ENA bit is RAO and the DATAVMATCH bit is set to 1. If LNK1ENA is RAZ, this field is RAZ/WI. + 16 + 4 + read-write + + + MATCHED + MATCHED bit. Comparator match. A value of 1 indicates that the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit to 0. + 24 + 1 + read-only + + + MATCHED_0 + No match. + 0 + + + MATCHED_1 + Match. + 0x1 + + + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x3B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + FPB + Flash Patch and Breakpoint Unit Registers + FPB + FP_ + 0xE0002000 + + 0 + 0x1000 + registers + + + + CTRL + FlashPatch Control Register + 0 + 32 + read-write + 0x130 + 0xFFFFFFFF + + + ENABLE + Enable bit for the FPB. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + FPB disabled. + 0 + + + ENABLE_1 + FPB enabled. + 0x1 + + + + + KEY + KEY bit. On any write to FP_CTRL, the FPB unit ignores the write unless this bit is 1. This bit is RAZ. + 1 + 1 + read-write + + + NUM_CODE_least + NUM_CODE[3:0]. The least significant bits of NUM_CODE, the number of instruction address comparators. If NUM_CODE[6:0] is zero, the implementation does not support any instruction address comparators. + 4 + 4 + read-only + + + NUM_LIT + NUM_LIT bits. The number of literal address comparators supported. If this field is zero, the implementation does not support literal comparators. + 8 + 4 + read-only + + + NUM_CODE_most + NUM_CODE[6:4]. The most significant bits of NUM_CODE, the number of instruction address comparators, see bits [7:4]. + 12 + 3 + read-only + + + + + REMAP + FlashPatch Remap Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + REMAP + REMAP bits. If the FPB supports flash patch remap, this field: - holds bits [28:5] of the base address in SRAM to which the FPB remaps the address - has an UNKNOWN value on reset. If the FPB only supports breakpoint functionality this field is UNK/SBZP. + 5 + 24 + read-write + + + RMPSPT + RMPSPT bit. Indicates whether the FPB unit supports flash patch remap. + 29 + 1 + read-only + + + RMPSPT_0 + Remapping not supported. The FPB only supports breakpoint functionality. + 0 + + + RMPSPT_1 + Hard-wired remap to SRAM region. + 0x1 + + + + + + + COMP0 + FlashPatch Comparator Register 0 + 0x8 + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP1 + FlashPatch Comparator Register 1 + 0xC + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP2 + FlashPatch Comparator Register 2 + 0x10 + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP3 + FlashPatch Comparator Register 3 + 0x14 + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP4 + FlashPatch Comparator Register 4 + 0x18 + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP5 + FlashPatch Comparator Register 5 + 0x1C + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP6 + FlashPatch Comparator Register 6 + 0x20 + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + COMP7 + FlashPatch Comparator Register 7 + 0x24 + 32 + read-write + 0 + 0xE0000007 + + + ENABLE + Enable bit for this comparator. A Power-on reset clears this bit to 0. + 0 + 1 + read-write + + + ENABLE_0 + Comparator disabled. + 0 + + + ENABLE_1 + Comparator enabled. + 0x1 + + + + + COMP + COMP bits. Bits [28:2] of the address to compare with addresses from the Code memory region. Bits [31:29] and [1:0] of the address for comparison are zero. If a match occurs: - for an instruction address comparator, the REPLACE field defines the required action - for a literal address comparator, the FPB remaps the access. The reset value of this field is UNKNOWN. + 2 + 27 + read-write + + + REPLACE + REPLACE[1:0]. For an instruction address comparator: - Defines the behavior when the COMP address is matched. - The reset value of this field is UNKNOWN. For a literal address comparator: - Field is UNK/SBZP. + 30 + 2 + read-write + + + REPLACE_0 + Remap to remap address. + 0 + + + REPLACE_1 + Breakpoint on lower halfword, upper is unaffected. + 0x1 + + + REPLACE_2 + Breakpoint on upper halfword, lower is unaffected. + 0x2 + + + REPLACE_3 + Breakpoint on both lower and upper halfwords. + 0x3 + + + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0x3 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB0 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0x2B + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0xE0 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + SCnSCB + System Control not in System Control Block + SCNSCB + 0xE000E000 + + 0 + 0x10 + registers + + + + CPPWR + Coprocessor Power Control Register + 0xC + 32 + read-write + 0 + 0 + + + SU0 + State UNKNOWN 0. + 0 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS0 + State UNKNOWN Secure only 0. + 1 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU0 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU0 field is only accessible from the Secure state. + 0x1 + + + + + SU1 + State UNKNOWN 1. + 2 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS1 + State UNKNOWN Secure only 1. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU2 + State UNKNOWN 2. + 4 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS2 + State UNKNOWN Secure only 2. + 5 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU2 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU2 field is only accessible from the Secure state. + 0x1 + + + + + SU3 + State UNKNOWN 3. + 6 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS3 + State UNKNOWN Secure only 3. + 7 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU3 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU3 field is only accessible from the Secure state. + 0x1 + + + + + SU4 + State UNKNOWN 4. + 8 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS4 + State UNKNOWN Secure only 4. + 9 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU4 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU4 field is only accessible from the Secure state. + 0x1 + + + + + SU5 + State UNKNOWN 5. + 10 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS5 + State UNKNOWN Secure only 5. + 11 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU5 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU5 field is only accessible from the Secure state. + 0x1 + + + + + SU6 + State UNKNOWN 6. + 12 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS6 + State UNKNOWN Secure only 6. + 13 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU6 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU6 field is only accessible from the Secure state. + 0x1 + + + + + SU7 + State UNKNOWN 7. + 14 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS7 + State UNKNOWN Secure only 7. + 15 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU10 + State UNKNOWN 10. + 20 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The floating-point state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The floating-point state is permitted to become UNKNOWN + 0x1 + + + + + SUS10 + State UNKNOWN Secure only 10. + 21 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU10 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU10 field is only accessible from the Secure state. + 0x1 + + + + + SU11 + State UNKNOWN 11. + 22 + 1 + read-write + + + SUS11 + State UNKNOWN Secure only 11. + 23 + 1 + read-write + + + + + + + SysTick + System timer + SYSTICK + SYST_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + ENABLE_0 + counter disabled + 0 + + + ENABLE_1 + counter enabled + 0x1 + + + + + TICKINT + no description available + 1 + 1 + read-write + + + TICKINT_0 + counting down to 0 does not assert the SysTick exception request + 0 + + + TICKINT_1 + counting down to 0 asserts the SysTick exception request + 0x1 + + + + + CLKSOURCE + no description available + 2 + 1 + read-write + + + CLKSOURCE_0 + external clock + 0 + + + CLKSOURCE_1 + processor clock + 0x1 + + + + + COUNTFLAG + no description available + 16 + 1 + read-write + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + read-write + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + read-write + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + read-only + + + SKEW + no description available + 30 + 1 + read-only + + + SKEW_0 + 10ms calibration value is exact + 0 + + + SKEW_1 + 10ms calibration value is inexact, because of the clock frequency + 0x1 + + + + + NOREF + no description available + 31 + 1 + read-only + + + NOREF_0 + The reference clock is provided + 0 + + + NOREF_1 + The reference clock is not provided + 0x1 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + 16 + 0x4 + ISER[%s] + Interrupt Set Enable Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA0 + Interrupt set-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA1 + Interrupt set-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA2 + Interrupt set-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA3 + Interrupt set-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA4 + Interrupt set-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA5 + Interrupt set-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA6 + Interrupt set-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA7 + Interrupt set-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA8 + Interrupt set-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA9 + Interrupt set-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA10 + Interrupt set-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA11 + Interrupt set-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA12 + Interrupt set-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA13 + Interrupt set-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA14 + Interrupt set-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA15 + Interrupt set-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA16 + Interrupt set-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA17 + Interrupt set-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA18 + Interrupt set-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA19 + Interrupt set-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA20 + Interrupt set-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA21 + Interrupt set-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA22 + Interrupt set-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA23 + Interrupt set-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA24 + Interrupt set-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA25 + Interrupt set-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA26 + Interrupt set-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA27 + Interrupt set-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA28 + Interrupt set-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA29 + Interrupt set-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA30 + Interrupt set-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA31 + Interrupt set-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ICER[%s] + Interrupt Clear Enable Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA0 + Interrupt clear-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA1 + Interrupt clear-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA2 + Interrupt clear-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA3 + Interrupt clear-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA4 + Interrupt clear-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA5 + Interrupt clear-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA6 + Interrupt clear-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA7 + Interrupt clear-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA8 + Interrupt clear-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA9 + Interrupt clear-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA10 + Interrupt clear-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA11 + Interrupt clear-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA12 + Interrupt clear-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA13 + Interrupt clear-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA14 + Interrupt clear-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA15 + Interrupt clear-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA16 + Interrupt clear-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA17 + Interrupt clear-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA18 + Interrupt clear-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA19 + Interrupt clear-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA20 + Interrupt clear-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA21 + Interrupt clear-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA22 + Interrupt clear-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA23 + Interrupt clear-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA24 + Interrupt clear-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA25 + Interrupt clear-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA26 + Interrupt clear-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA27 + Interrupt clear-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA28 + Interrupt clear-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA29 + Interrupt clear-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA30 + Interrupt clear-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA31 + Interrupt clear-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ISPR[%s] + Interrupt Set Pending Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND0 + Interrupt set-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND1 + Interrupt set-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND2 + Interrupt set-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND3 + Interrupt set-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND4 + Interrupt set-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND5 + Interrupt set-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND6 + Interrupt set-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND7 + Interrupt set-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND8 + Interrupt set-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND9 + Interrupt set-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND10 + Interrupt set-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND11 + Interrupt set-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND12 + Interrupt set-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND13 + Interrupt set-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND14 + Interrupt set-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND15 + Interrupt set-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND16 + Interrupt set-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND17 + Interrupt set-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND18 + Interrupt set-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND19 + Interrupt set-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND20 + Interrupt set-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND21 + Interrupt set-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND22 + Interrupt set-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND23 + Interrupt set-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND24 + Interrupt set-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND25 + Interrupt set-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND26 + Interrupt set-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND27 + Interrupt set-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND28 + Interrupt set-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND29 + Interrupt set-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND30 + Interrupt set-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND31 + Interrupt set-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + + + 16 + 0x4 + ICPR[%s] + Interrupt Clear Pending Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND0 + Interrupt clear-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND1 + Interrupt clear-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND2 + Interrupt clear-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND3 + Interrupt clear-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND4 + Interrupt clear-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND5 + Interrupt clear-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND6 + Interrupt clear-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND7 + Interrupt clear-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND8 + Interrupt clear-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND9 + Interrupt clear-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND10 + Interrupt clear-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND11 + Interrupt clear-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND12 + Interrupt clear-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND13 + Interrupt clear-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND14 + Interrupt clear-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND15 + Interrupt clear-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND16 + Interrupt clear-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND17 + Interrupt clear-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND18 + Interrupt clear-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND19 + Interrupt clear-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND20 + Interrupt clear-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND21 + Interrupt clear-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND22 + Interrupt clear-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND23 + Interrupt clear-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND24 + Interrupt clear-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND25 + Interrupt clear-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND26 + Interrupt clear-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND27 + Interrupt clear-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND28 + Interrupt clear-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND29 + Interrupt clear-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND30 + Interrupt clear-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND31 + Interrupt clear-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + + + 16 + 0x4 + IABR[%s] + Interrupt Active Bit Register + 0x200 + 32 + read-write + 0 + 0 + + + ACTIVE0 + Active state bits. + 0 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE1 + Active state bits. + 1 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE2 + Active state bits. + 2 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE3 + Active state bits. + 3 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE4 + Active state bits. + 4 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE5 + Active state bits. + 5 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE6 + Active state bits. + 6 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE7 + Active state bits. + 7 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE8 + Active state bits. + 8 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE9 + Active state bits. + 9 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE10 + Active state bits. + 10 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE11 + Active state bits. + 11 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE12 + Active state bits. + 12 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE13 + Active state bits. + 13 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE14 + Active state bits. + 14 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE15 + Active state bits. + 15 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE16 + Active state bits. + 16 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE17 + Active state bits. + 17 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE18 + Active state bits. + 18 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE19 + Active state bits. + 19 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE20 + Active state bits. + 20 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE21 + Active state bits. + 21 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE22 + Active state bits. + 22 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE23 + Active state bits. + 23 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE24 + Active state bits. + 24 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE25 + Active state bits. + 25 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE26 + Active state bits. + 26 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE27 + Active state bits. + 27 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE28 + Active state bits. + 28 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE29 + Active state bits. + 29 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE30 + Active state bits. + 30 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE31 + Active state bits. + 31 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + + + 16 + 0x4 + ITNS[%s] + Interrupt Target Non-secure Register + 0x280 + 32 + read-write + 0 + 0 + + + INTS0 + Interrupt Targets Non-secure bits. + 0 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS1 + Interrupt Targets Non-secure bits. + 1 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS2 + Interrupt Targets Non-secure bits. + 2 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS3 + Interrupt Targets Non-secure bits. + 3 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS4 + Interrupt Targets Non-secure bits. + 4 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS5 + Interrupt Targets Non-secure bits. + 5 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS6 + Interrupt Targets Non-secure bits. + 6 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS7 + Interrupt Targets Non-secure bits. + 7 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS8 + Interrupt Targets Non-secure bits. + 8 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS9 + Interrupt Targets Non-secure bits. + 9 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS10 + Interrupt Targets Non-secure bits. + 10 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS11 + Interrupt Targets Non-secure bits. + 11 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS12 + Interrupt Targets Non-secure bits. + 12 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS13 + Interrupt Targets Non-secure bits. + 13 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS14 + Interrupt Targets Non-secure bits. + 14 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS15 + Interrupt Targets Non-secure bits. + 15 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS16 + Interrupt Targets Non-secure bits. + 16 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS17 + Interrupt Targets Non-secure bits. + 17 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS18 + Interrupt Targets Non-secure bits. + 18 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS19 + Interrupt Targets Non-secure bits. + 19 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS20 + Interrupt Targets Non-secure bits. + 20 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS21 + Interrupt Targets Non-secure bits. + 21 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS22 + Interrupt Targets Non-secure bits. + 22 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS23 + Interrupt Targets Non-secure bits. + 23 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS24 + Interrupt Targets Non-secure bits. + 24 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS25 + Interrupt Targets Non-secure bits. + 25 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS26 + Interrupt Targets Non-secure bits. + 26 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS27 + Interrupt Targets Non-secure bits. + 27 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS28 + Interrupt Targets Non-secure bits. + 28 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS29 + Interrupt Targets Non-secure bits. + 29 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS30 + Interrupt Targets Non-secure bits. + 30 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS31 + Interrupt Targets Non-secure bits. + 31 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + + + 120 + 0x4 + IPR[%s] + Interrupt Priority Register + 0x300 + 32 + read-write + 0 + 0 + + + PRI_0 + no description available + 0 + 8 + read-write + + + PRI_1 + no description available + 8 + 8 + read-write + + + PRI_2 + no description available + 16 + 8 + read-write + + + PRI_3 + no description available + 24 + 8 + read-write + + + + + STIR + Software Trigger Interrupt Register + 0xE00 + 32 + write-only + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-479. + 0 + 9 + write-only + + + + + + + SAU + Security Attribution Unit + SAU + 0xE000EDD0 + + 0 + 0xEC + registers + + + + CTRL + Security Attribution Unit Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. + 0 + 1 + read-write + + + DISABLED + The SAU is disabled. + 0 + + + ENABLED + The SAU is enabled. + 0x1 + + + + + ALLNS + All Non-secure. + 1 + 1 + read-write + + + SECURED_MEMORY + Memory is marked as Secure and is not Non-secure callable. + 0 + + + NON_SECURED_MEMORY + Memory is marked as Non-secure. + 0x1 + + + + + + + TYPE + Security Attribution Unit Type Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SREGION + SAU regions. The number of implemented SAU regions. + 0 + 8 + read-write + + + + + RNR + Security Attribution Unit Region Number Register + 0xD8 + 32 + read-write + 0 + 0 + + + REGION + Region number. + 0 + 8 + read-write + + + + + RBAR + Security Attribution Unit Region Base Address Register + 0xDC + 32 + read-write + 0 + 0 + + + BADDR + Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. + 5 + 27 + read-write + + + + + RLAR + Security Attribution Unit Region Limit Address Register + 0xE0 + 32 + read-write + 0 + 0 + + + ENABLE + Enable. SAU region enable. + 0 + 1 + read-write + + + ENABLED + SAU region is enabled. + 0 + + + DISABLED + SAU region is disabled. + 0x1 + + + + + NSC + Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. + 1 + 1 + read-write + + + NOT_NON_SECURE_CALLABLE + Region is not Non-secure callable. + 0 + + + NON_SECURE_CALLABLE + Region is Non-secure callable. + 0x1 + + + + + LADDR + Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. + 5 + 27 + read-write + + + + + SFSR + Secure Fault Status Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INVEP + Invalid entry point. + 0 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVIS + Invalid integrity signature flag. + 1 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVER + Invalid exception return flag. + 2 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + AUVIOL + Attribution unit violation flag. + 3 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVTRAN + Invalid transition flag. + 4 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + LSPERR + Lazy state preservation error flag. + 5 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + SFARVALID + Secure fault address valid. + 6 + 1 + read-write + + + NOT_VALID + SFAR content not valid. + 0 + + + VALID + SFAR content valid. + 0x1 + + + + + LSERR + Lazy state error flag. + 7 + 1 + read-write + + + NO_ERROR + Error has not occurred + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + + + SFAR + Secure Fault Address Register + 0xE8 + 32 + read-write + 0 + 0 + + + ADDRESS + When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. + 0 + 32 + read-write + + + + + + + CoreDebug + Core Debug Registers + COREDEBUG + 0xE000EDF0 + + 0 + 0x10 + registers + + + + DHCSR_Read + Debug Halting Control and Status Register + DHCSR_Read_DHCSR_Write + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + C_DEBUGEN + Halting debug enable bit. If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE. This bit can only be set to 1 from the DAP, it cannot be set to 1 under software control. This bit is 0 after a Power-on reset. + 0 + 1 + read-write + + + C_DEBUGEN_0 + Disabled + 0 + + + C_DEBUGEN_1 + Enabled + 0x1 + + + + + C_HALT + Processor halt bit. This bit is UNKNOWN after a Power-on reset. + 1 + 1 + read-write + + + C_HALT_0 + No effect. + 0 + + + C_HALT_1 + Halt the processor. + 0x1 + + + + + C_STEP + Processor step bit. This bit is UNKNOWN after a Power-on reset. + 2 + 1 + read-write + + + C_STEP_0 + No effect. + 0 + + + C_STEP_1 + Step the processor. + 0x1 + + + + + C_MASKINTS + C_MASKINTS bit. When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both: - before the write to DHCSR, the value of the C_HALT bit is 1. - the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit. This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit. The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN. This bit is UNKNOWN after a Power-on reset. + 3 + 1 + read-write + + + C_MASKINTS_0 + Do not mask. + 0 + + + C_MASKINTS_1 + Mask PenSV, SysTick and external configurable interrupts. + 0x1 + + + + + S_REGRDY + S_REGRDY bit. A handshake flag for transfers through the DCRDR: - Writing to DCRSR clears the bit to 0. - Completion of the DCRDR transfer then sets the bit to 1. This bit is valid only when the processor is in Debug state, otherwise the bit is UNKNOWN. + 16 + 1 + read-only + + + S_REGRDY_0 + There has been a write to the DCRDR, but the transfer is not complete. + 0 + + + S_REGRDY_1 + The transfer to or from the DCRDR is complete. + 0x1 + + + + + S_HALT + S_HALT bit. Indicates whether the processor is in Debug state. + 17 + 1 + read-only + + + S_HALT_0 + Not in Debug state. + 0 + + + S_HALT_1 + In Debug state. + 0x1 + + + + + S_SLEEP + S_SLEEP bit. Indicates whether the processor is sleeping. The debugger must set the C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system. + 18 + 1 + read-only + + + S_SLEEP_0 + Not sleeping. + 0 + + + S_SLEEP_1 + Sleeping. + 0x1 + + + + + S_LOCKUP + S_LOCKUP bit. Indicates whether the processor is locked up because of an unrecoverable exception. This bit can only be read as 1 by a remote debugger, using the DAP. The value of 1 indicates that the processor is running but locked up. The bit clears to 0 when the processor enters Debug state. + 19 + 1 + read-only + + + S_LOCKUP_0 + Not locked up + 0 + + + S_LOCKUP_1 + Locked up + 0x1 + + + + + S_RETIRE_ST + S_RETIRE_ST bit. Indicates whether the processor has completed the execution of an instruction since the last read of DHCSR. This is a sticky bit, that clears to 0 on a read of DHCSR. A debugger can check this bit to determine if the processor is stalled on a load, store or fetch access. This bit is UNKNOWN after a Power-on or Local reset, but then is set to 1 as soon as the processor executes and retires an instruction. + 24 + 1 + read-only + + + S_RETIRE_ST_0 + No instruction retired since last DHCSR read. + 0 + + + S_RETIRE_ST_1 + At least one instruction retired since last DHCSR read. + 0x1 + + + + + S_RESET_ST + S_RESET_ST bit. Indicates whether the processor has been reset since the last read of DHCSR. This is a sticky bit, that clears to 0 on a read of DHCSR. + 25 + 1 + read-only + + + S_RESET_ST_0 + No reset since last DHCSR read. + 0 + + + S_RESET_ST_1 + At least one reset since last DHCSR read. + 0x1 + + + + + + + DHCSR_Write + Debug Halting Control and Status Register + DHCSR_Read_DHCSR_Write + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + C_DEBUGEN + Halting debug enable bit. If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE. This bit can only be set to 1 from the DAP, it cannot be set to 1 under software control. This bit is 0 after a Power-on reset. + 0 + 1 + read-write + + + C_DEBUGEN_0 + Disabled + 0 + + + C_DEBUGEN_1 + Enabled + 0x1 + + + + + C_HALT + Processor halt bit. This bit is UNKNOWN after a Power-on reset. + 1 + 1 + read-write + + + C_HALT_0 + No effect. + 0 + + + C_HALT_1 + Halt the processor. + 0x1 + + + + + C_STEP + Processor step bit. This bit is UNKNOWN after a Power-on reset. + 2 + 1 + read-write + + + C_STEP_0 + No effect. + 0 + + + C_STEP_1 + Step the processor. + 0x1 + + + + + C_MASKINTS + C_MASKINTS bit. When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both: - before the write to DHCSR, the value of the C_HALT bit is 1. - the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit. This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit. The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN. This bit is UNKNOWN after a Power-on reset. + 3 + 1 + read-write + + + C_MASKINTS_0 + Do not mask. + 0 + + + C_MASKINTS_1 + Mask PenSV, SysTick and external configurable interrupts. + 0x1 + + + + + DBGKEY + Debug key: Software must write 0xA05F to this field to enable write accesses to bits [15:0], otherwise the processor ignores the write access. + 16 + 16 + write-only + + + + + DCRSR + Debug Core Register Selector Register + 0x4 + 32 + write-only + 0 + 0 + + + REGSEL + REGSEL bits. Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer. + 0 + 5 + write-only + + + REGWnR + REGWnR bit. Specifies the access type for the transfer. + 16 + 1 + write-only + + + REGWnR_0 + Read + 0 + + + REGWnR_1 + Write + 0x1 + + + + + + + DCRDR + Debug Core Register Data Register + 0x8 + 32 + read-write + 0 + 0 + + + DBGTMP + DBGTMP bits. Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers. The value of this register is UNKNOWN: - on reset - if the processor is in Debug state, the debugger has written to DCRSR since entering Debug state and DHCSR.S_REGRDY is set to 0. + 0 + 32 + read-write + + + + + DEMCR + Debug Exception and Monitor Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + VC_CORERESET + VC_CORERESET bit. Enable Reset Vector Catch. This causes a Local reset to halt a running system. If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit. + 0 + 1 + read-write + + + VC_CORERESET_0 + Reset Vector Catch disabled. + 0 + + + VC_CORERESET_1 + Reset Vector Catch enabled. + 0x1 + + + + + VC_HARDERR + VC_HARDERR bit. Enable halting debug trap on a HardFault exception. If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit. + 10 + 1 + read-write + + + VC_HARDERR_0 + Halting debug trap disabled. + 0 + + + VC_HARDERR_1 + Halting debug trap enabled. + 0x1 + + + + + DWTENA + DWTENA bit. Global enable for all features configured and controlled by the DWT unit. + 24 + 1 + read-write + + + DWTENA_0 + DWT disabled. + 0 + + + DWTENA_1 + DWT enabled. + 0x1 + + + + + + + + + TPIU + Trace Port Interface Unit Registers + TPIU + TPIU_ + 0xE0040000 + + 0 + 0x1000 + registers + + + + SSPSR + Supported Parallel Port Size Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SWIDTH + SWIDTH[N] represents a trace port width of (N+1). The meaning of each bit is: 0 = Width (N+1) not supported. 1 = Width (N+1) supported. + 0 + 32 + read-only + + + + + CSPSR + Current Parallel Port Size Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CWIDTH + CWIDTH[N] represents a trace port width of (N+1). The meaning of each bit is: 0 = Width (N+1) is not the current trace port width. 1 = Width (N+1) is the current trace port width. + 0 + 32 + read-write + + + + + ACPR + Asynchronous Clock Prescaler Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Divisor for TRACECLKIN is Prescaler + 1 + 0 + 13 + read-write + + + + + SPPR + Selected Pin Protocol Register + 0xF0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TXMODE + Specified the protocol for trace output from the TPIU. + 0 + 2 + read-write + + + TXMODE_0 + Parallel trace port mode. + 0 + + + TXMODE_1 + Asynchronous SWO, using Manchester encoding. + 0x1 + + + TXMODE_2 + Asynchronous SWO, using NRZ encoding. + 0x2 + + + + + + + FFSR + Formatter and Flush Status Register + 0x300 + 32 + read-only + 0x8 + 0xFFFFFFFF + + + F1InProg + F1InProg. This bit always reads zero + 0 + 1 + read-only + + + FtStopped + FtStopped. This bit always reads zero + 1 + 1 + read-only + + + TCPresent + TCPresent. This bit always reads zero + 2 + 1 + read-only + + + FtNonStop + FtNonStop. Formatter cannot be stopped + 3 + 1 + read-only + + + + + FFCR + Formatter and Flush Control Register + 0x304 + 32 + read-write + 0x102 + 0xFFFFFFFF + + + EnFCont + Enable continuous formatting. + 1 + 1 + read-write + + + EnFCont_0 + Continuous formatting disabled. + 0 + + + EnFCont_1 + Continuous formatting enabled. + 0x1 + + + + + TrigIn + This bit Reads-As-One (RAO), specifying that triggers are inserted when a trigger pin is asserted. + 8 + 1 + read-write + + + + + FSCR + Formatter Synchronization Counter Register + 0x308 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + CycCount + CycCount[11:0]. 12-bit counter value to indicate the number of complete frames between full synchronization packets. Default value is 64 (0x40). + 0 + 12 + read-write + + + + + TRIGGER + Trigger Register + 0xEE8 + 32 + read-only + 0 + 0xFFFFFFFF + + + TRIGGER + TRIGGER input value. When read, this bit returns the TRIGGER input. + 0 + 1 + read-only + + + + + FIFODATA0 + FIFODATA0 Register + 0xEEC + 32 + read-only + 0 + 0xFFFFFFFF + + + ETMdata0 + ETM trace data. The TPIU discards this data when the registers is read. + 0 + 8 + read-only + + + ETMdata1 + ETM trace data. The TPIU discards this data when the registers is read. + 8 + 8 + read-only + + + ETMdata2 + ETM trace data. The TPIU discards this data when the registers is read. + 16 + 8 + read-only + + + ETMbytecount + Number of bytes of ETM trace data since last read of Integration ETM Data Register. + 24 + 2 + read-only + + + ETMATVALID + Returns the value of the ETM ATVALID signal. + 26 + 1 + read-only + + + ITMbytecount + Number of bytes of ITM trace data since last read of Integration ITM Data Register. + 27 + 2 + read-only + + + ITMATVALID + Returns the value of the ITM ATVALID signal. + 29 + 1 + read-only + + + + + ITATBCTR2 + Integration Test ATB Control 2 Register + 0xEF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ATREADY1_ATREADY2 + This bit sets the value of both the ETM and ITM ATREADY. + 0 + 1 + read-only + + + + + ITATBCTR0 + Integration Test ATB Control 0 Register + 0xEF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ATVALID1_ATVALID2 + A read of this bit returns the value of ATVALIDS1 OR-ed with ATVALIDS2. + 0 + 1 + read-only + + + + + FIFODATA1 + FIFODATA1 Register + 0xEFC + 32 + read-only + 0 + 0xFFFFFFFF + + + ITMdata0 + ITM trace data. The TPIU discards this data when the registers is read. + 0 + 8 + read-only + + + ITMdata1 + ITM trace data. The TPIU discards this data when the registers is read. + 8 + 8 + read-only + + + ITMdata2 + ITM trace data. The TPIU discards this data when the registers is read. + 16 + 8 + read-only + + + ETMbytecount + Number of bytes of ETM trace data since last read of Integration ETM Data Register. + 24 + 2 + read-only + + + ETMATVALID + Returns the value of the ETM ATVALID signal. + 26 + 1 + read-only + + + ITMbytecount + Number of bytes of ITM trace data since last read of Integration ITM Data Register. + 27 + 2 + read-only + + + ITMATVALID + Returns the value of the ITM ATVALID signal. + 29 + 1 + read-only + + + + + ITCTRL + Integration Mode Control Register + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + Mode + Specifies the current mode for the TPIU. + 0 + 2 + read-write + + + Mode_0 + normal mode + 0 + + + Mode_1 + integration test mode + 0x1 + + + Mode_2 + integration data test mode + 0x2 + + + + + + + CLAIMSET + Claim Tag Set Register + 0xFA0 + 32 + read-write + 0xF + 0xFFFFFFFF + + + CLAIMSET + A bit programmable register bank which sets the Claim Tag Value. Write 1 to set the bit in the claim tag. A read will return a logic 1 for all implemented locations. + 0 + 4 + read-write + + + + + CLAIMCLR + Claim Tag Clear Register + 0xFA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLAIMCLR + A bit programmable register bank that is zero at reset. Write 1 to clear the bit in the claim tag. On reads, returns the current setting of the claim tag. + 0 + 4 + read-write + + + + + DEVID + TPIU_DEVID Register + 0xFC8 + 32 + read-only + 0xC81 + 0xFFFFFFDF + + + NumberOfTraceInputs + Number of trace inputs. Specifies the number of trace inputs: b000000 = 1 input b000001 = 2 inputs If your implementation includes an ETM, the value of this field is b000001. + 0 + 5 + read-only + + + TRACECELKIN + Asynchronous TRACECLKIN. Specifies whether TRACECLKIN can be asynchronous to CLK. + 5 + 1 + read-only + + + TRACECELKIN_0 + b0 = TRACECLKIN must be synchronous to CLK + 0 + + + TRACECELKIN_1 + b1 = TRACECLKIN can be asynchronous to CLK + 0x1 + + + + + MinimumBufferSize + Minimum buffer size. Specifies the minimum TPIU buffer size: b010 = 4 bytes + 6 + 3 + read-only + + + TraceAndClockModes + Trace and clock modes. This bit Reads-As-Zero (RAZ), indicating that tracedata and clock modes are supported. + 9 + 1 + read-only + + + TraceAndClockModes_0 + Supported + 0 + + + TraceAndClockModes_1 + Not supported + 0x1 + + + + + Manchester + Asynchronous Serial Wire Output (Manchester). This bit Reads-As-One (RAO), indicating that the output is supported. + 10 + 1 + read-only + + + NRZ + Asynchronous Serial Wire Output (NRZ). This bit Reads-As-One (RAO), indicating that the output is supported. + 11 + 1 + read-only + + + + + PID4 + Peripheral Identification Register 4. + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification Register 5. + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID6 + Peripheral Identification Register 6. + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PID7 + Peripheral Identification Register 7. + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PID0 + Peripheral Identification Register 0. + 0xFE0 + 32 + read-only + 0xA1 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PID1 + Peripheral Identification Register 1. + 0xFE4 + 32 + read-only + 0xB9 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification Register 2. + 0xFE8 + 32 + read-only + 0xB + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification Register 3. + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CID0 + Component Identification Register 0. + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID1 + Component Identification Register 1. + 0xFF4 + 32 + read-only + 0x90 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CID2 + Component Identification Register 2. + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CID3 + Component Identification Register 3. + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + ETM + Embedded Trace Macrocell Registers + ETM + ETM + 0xE0041000 + + 0 + 0x1000 + registers + + + CTI + 0 + + + + CR + Main Control Register + 0 + 32 + read-write + 0x411 + 0xFFFFFFFF + + + ETMPD + ETM power down. This bit can be used by an implementation to control if the ETM is in a low power state. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, writes to some registers and fields might be ignored. + 0 + 1 + read-write + + + PS + Port size. The ETM-M4 has no influence over the external pins used for trace. These bits are implemented but not used. On an ETM reset these bits reset to 0b001. + 4 + 3 + read-write + + + SP + Stall processor. The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL output remains LOW at all times and the FIFO overflows if there are too many trace packets. Trace resumes without corruption once the FIFO has drained, if overflow does occur. An ETM reset sets this bit to 0. + 7 + 1 + read-write + + + BO + Branch output. When set to 1 all branch addresses are output, even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being executed. When this bit is set to 1, more trace data is generated, and this may affect the performance of the trace system. Information about the execution of a branch is traced regardless of the state of this bit. An ETM reset sets this bit to 0. + 8 + 1 + read-write + + + DRC + Debug request control. When set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the ARM processor to be forced into Debug state. An ETM reset sets this bit to 0. + 9 + 1 + read-write + + + ETMP + ETM programming. This bit must be set to 1 at the start of the ETM programming sequence. Tracing is prevented while this bit is set to 1. On an ETM reset this bit is set to b1. + 10 + 1 + read-write + + + ETMPS + ETM port selection. This bit can be used to control other trace components in an implementation. This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM. An ETM reset sets this bit to 0. + 11 + 1 + read-write + + + ETMPS_0 + ETMEN is LOW. + 0 + + + ETMPS_1 + ETMEN is HIGH. + 0x1 + + + + + PM2 + This bit is implemented but has no function. An ETM reset sets this bit to 0. + 13 + 1 + read-write + + + PM + These bits are implemented but have no function. An ETM reset sets these bits to 0. + 16 + 2 + read-write + + + PS3 + This bit is implemented but has no function. An ETM reset sets this bit to 0. + 21 + 1 + read-write + + + TE + When set, this bit enables timestamping. An ETM reset sets this bit to 0. + 28 + 1 + read-write + + + + + CCR + Configuration Code Register + 0x4 + 32 + read-only + 0x8C802000 + 0xFFFFFFFF + + + NumberOfAddressComparatorPairs + Number of address comparator pairs. The value of these bits is b0000, indicating that address comparator pairs are not implemented. + 0 + 4 + read-only + + + NDVC + Number of data value comparators. The value of these bits is b0000, indicating that data value comparators are not implemented. + 4 + 4 + read-only + + + NMMD + Number of memory map decoders. The value of these bits is b00000, indicating that memory map decoder inputs are not implemented. + 8 + 5 + read-only + + + NC + Number of counters. The value of these bits is b001, indicating that one counter is implemented. + 13 + 3 + read-only + + + SP + Sequencer present. The value of this bit is 0, indicating that the sequencer is not implemented. + 16 + 1 + read-only + + + NEI + Number of external inputs. The value of these bits is between b000 and b010, indicating the number of external inputs, from 0 to 2, implemented in the system. + 17 + 3 + read-only + + + NEO + Number of external outputs. The value of these bits is b000, indicating that no external outputs are supported. + 20 + 3 + read-only + + + FFLP + FIFOFULL logic present. The value of this bit is 1, indicating that FIFOFULL logic is present in the ETM. To use FIFOFULL the system must also support the function, as indicated by bit [8] of ETMSCR. + 23 + 1 + read-only + + + NCIDC + Number of Context ID comparators. The value of these bits is b00, indicating that Context ID comparators are not implemented. + 24 + 2 + read-only + + + TSSBP + Trace start/stop block present. The value of this bit is 1, indicating that the Trace start/stop block is present. + 26 + 1 + read-only + + + CMA + Coprocessor and memory access. The value of this bit is 1, indicating that memory-mapped access to registers is supported. + 27 + 1 + read-only + + + ETMIDRP + The value of this bit is 1, indicating that the ETMIDR, register 0x79, is present and defines the ETM architecture version in use. + 31 + 1 + read-only + + + + + TRIGGER + Trigger Event Register + 0x8 + 32 + read-write + 0 + 0xFFFE0000 + + + TriggerEvent + Trigger event + 0 + 17 + read-write + + + + + SR + ETM Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFF0 + + + UOF + Untraced overflow flag. If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either: - trace is restarted - the ETM Power Down bit, bit [0] of the ETM Control Register, 0x00, is set to 1. Note: Setting or clearing the ETM programming bit does not cause this bit to be cleared to 0. + 0 + 1 + read-only + + + Progbit + ETM programming bit value (Progbit). The current effective value of the ETM Programming bit (ETM Control Register bit [10]). Tou must wait for this bit to go to 1 before you start to program the ETM. + 1 + 1 + read-only + + + Status + Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match. + 2 + 1 + read-write + + + Trigger + Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the ETM is next programmed. + 3 + 1 + read-write + + + + + SCR + System Configuration Register + 0x14 + 32 + read-only + 0x20D09 + 0xFFFFFFFF + + + MaximumPortSize + Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value of these bits is b001. + 0 + 3 + read-only + + + FIFOFULLsupported + FIFOFULL supported. The value of this bit is 1, indicating that FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR. + 8 + 1 + read-only + + + MaximumPortSize3 + Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0. This has no effect on the TPIU trace port. + 9 + 1 + read-only + + + PortSizeSupported + Port size supported. This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port. + 10 + 1 + read-only + + + PortModeSupported + Port mode supported. This bit reads as 1 if the currently selected port mode is supported. This has no effect on the TPIU trace port. + 11 + 1 + read-only + + + N + These bits give the number of supported processors minus 1. The value of these bits is b000, indicating that there is only one processor connected. + 12 + 3 + read-only + + + NoFetchComparisons + No Fetch comparisons. The value of this bit is 1, indicating that fetch comparisons are not implemented. + 17 + 1 + read-only + + + + + EEVR + Trace Enable Event Register + 0x20 + 32 + read-write + 0 + 0 + + + TraceEnableEvent + Trace Enable event. + 0 + 17 + read-write + + + + + TECR1 + Trace Enable Control 1 Register + 0x24 + 32 + read-write + 0 + 0xFDFFFFFF + + + TraceControlEnable + Trace start/stop enable. The trace start/stop resource, resource 0x5F, is unaffected by the value of this bit. + 25 + 1 + read-write + + + TraceControlEnable_0 + Tracing is unaffected by the trace start/stop logic. + 0 + + + TraceControlEnable_1 + Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. + 0x1 + + + + + + + FFLR + FIFOFULL Level Register + 0x28 + 32 + read-write + 0 + 0 + + + FIFOFullLevel + FIFO full level. The number of bytes left in FIFO, below which the FIFOFULL or SupressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO. + 0 + 8 + read-write + + + + + CNTRLDVR1 + Free-running counter reload value + 0x140 + 32 + read-write + 0 + 0 + + + IntitialCount + Initial count. + 0 + 16 + read-write + + + + + SYNCFR + Synchronization Frequency Register + 0x1E0 + 32 + read-only + 0x400 + 0xFFFFFFFF + + + SyncFrequency + Synchronization frequency. Default value is 1024. + 0 + 12 + read-only + + + + + IDR + ID Register + 0x1E4 + 32 + read-only + 0x4114F250 + 0xFFFFFFFF + + + ImplementationRevision + Implementation revision. The value of these bits is b0000, indicating implementation revision, 0. + 0 + 4 + read-only + + + MinorETMarchitectureVersion + Minor ETM architecture version. The value of these bits is 0b0101, indicating minor architecture version number 5. + 4 + 4 + read-only + + + MajorETMarchitectureVersion + Major ETM architecture version. The value of these bits is 0b0010, indicating major architecture version number 3, ETMv3. + 8 + 4 + read-only + + + ProcessorFamily + Processor family. The value of these bits is 0b1111, indicating that the processor family is not identified in this register. + 12 + 4 + read-only + + + LoadPCfirst + Load PC first. The value of this bit is 0, indicating that data tracing is not supported. + 16 + 1 + read-only + + + ThumbInstructionTracing + 32-bit Thumb instruction tracing. The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction. + 18 + 1 + read-only + + + ThumbInstructionTracing_0 + A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions. + 0 + + + ThumbInstructionTracing_1 + A 32-bit Thimb instruction is traced as a single instruction. + 0x1 + + + + + SecurityExtensionSupport + Security Extensions support. The value of this bit is 0, indicating that the ETM behaves as if the processor is in Secure state at all times. + 19 + 1 + read-only + + + SecurityExtensionSupport_0 + The ETM behaves as if the processor is in Secure state at all times. + 0 + + + SecurityExtensionSupport_1 + The ARM architecture Security Extensions are implemented by the processor. + 0x1 + + + + + BranchPacketEncoding + Branch packet encoding. The value of this bit is 1, indicating that alternative branch packet encoding is implemented. + 20 + 1 + read-only + + + BranchPacketEncoding_0 + The ETM implements the original branch packet encoding. + 0 + + + BranchPacketEncoding_1 + The ETM implements the alternative branch packet encoding. + 0x1 + + + + + ImplementorCode + Implementor code. These bits identify ARM as the implementor of the processor. The value of these bits is 01000001. + 24 + 8 + read-only + + + + + CCER + Configuration Code Extension Register + 0x1E8 + 32 + read-only + 0x18541800 + 0xFFFFFFFF + + + ExtendedExternalInputSelectors + Extended external input selectors. The value of these bits is 0, indicating that extended external input selectors are not implemented. + 0 + 3 + read-only + + + ExtendedExternalInputBus + Extended external input bus. The value of these bits is 0, indicating that the extended external input bus is not implemented. + 3 + 8 + read-only + + + ReadableRegisters + Readable registers. The value of this bit is 1, indicating that all registers are readable. + 11 + 1 + read-only + + + DataAddressComparisons + Data address comparisons. The value of this bit is 1, indicating that data address comparisons are not supported. + 12 + 1 + read-only + + + InstrumentationResources + Instrumentation resources. The value of these bits is 0b000, indicating that no Instrumentation resources are supported. + 13 + 3 + read-only + + + EmbeddedICEwatchpointInputs + EmbeddedICE watchpoint inputs. The value of these bits is 0b0100, indicating that the number of EmbeddedICE watchpoint inputs implemented is four. These inputs come from the DWT. + 16 + 4 + read-only + + + TraceStartStopBlockUsesEmbeddedICEwatchpointInputs + Trace Start/Stop block uses EmbeddedICE watchpoint inputs. The value of this bit is 1, indicating that the Trace Start/Stop block uses the EmbeddedICE watchpoint inputs. + 20 + 1 + read-only + + + EmbeddedICEbehaviorControlImplemented + EmbeddedICE behavior control implemented. The value of this bit is 0, indicating that the ETMEIBCR is not implemented. + 21 + 1 + read-only + + + TimestampingImplemented + Timestamping implemented. This bit is set to 1, indicating that timestamping is implemented. + 22 + 1 + read-only + + + ReducedFunctionCounter + Reduced function counter. Set to 1 to indicate that Counter 1 is a reduced function counter. + 27 + 1 + read-only + + + TimestampEncoding + Timestamp encoding. Set to 1 to indicate that the timestamp is encoded as a natural binary number. + 28 + 1 + read-only + + + TimestampSize + Timestamp size. Set to 0 to indicate a size of 48 bits. + 29 + 1 + read-only + + + + + TESSEICR + TraceEnable Start/Stop EmbeddedICE Control Register + 0x1F0 + 32 + read-write + 0 + 0xFFF0FFF0 + + + StartResourceSelection + Start resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2] corresponds to input 3, and bit [3] corresponds to input 4. + 0 + 4 + read-write + + + StopResourceSelection + Stop resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2, bit [18] corresponds to input 3, and bit [19] corresponds to input 4. + 16 + 4 + read-write + + + + + TSEVR + Timestamp Event Register + 0x1F8 + 32 + read-write + 0 + 0 + + + TimestampEvent + Timestamp event. + 0 + 12 + read-write + + + + + TRACEIDR + CoreSight Trace ID Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TraceID + Trace ID to output onto the trace bus. On an ETM reset this field is cleared to 0x00. + 0 + 7 + read-write + + + + + IDR2 + ETM ID Register 2 + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDSR + Device Power-Down Status Register + 0x314 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + ETMpoweredup + The value of this bit indicates whether you can access the ETM Trace Registers. The value of this bit is always 1, indicating that the ETM Trace Registers can be accessed. + 0 + 1 + read-only + + + + + _ITMISCIN + Integration Test Miscelaneous Inputs Register + 0xEE0 + 32 + read-only + 0 + 0xFFFFFFE0 + + + EXTIN + A read of these bits returns the value of the EXTIN[1:0] input pins. + 0 + 2 + read-only + + + COREHALT + A read of this bit returns the value of the COREHALT input pin. + 4 + 1 + read-only + + + + + _ITTRIGOUT + Integration Test Trigger Out Register + 0xEE8 + 32 + write-only + 0 + 0xFFFFFFFE + + + TRIGGER + A write to this bit sets the TRIGGER output. + 0 + 1 + write-only + + + + + _ITATBCTR2 + ETM Integration Test ATB Control 2 Register + 0xEF0 + 32 + read-only + 0 + 0xFFFFFFFE + + + ATREADY + A read of this bit returns the value of the ETM ATREADY input. + 0 + 1 + read-only + + + + + _ITATBCTR0 + ETM Integration Test ATB Control 0 Register + 0xEF8 + 32 + write-only + 0 + 0xFFFFFFFE + + + ATVALID + A write to this bit sets the value of the ETM ATVALID output. + 0 + 1 + write-only + + + + + ITCTRL + Integration Mode Control Register + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + Mode + Enable integration mode. When this bit is set to 1, the device enters integration mode to enable Topology Detection or Integration Testing to be checked. On an ETM reset this bit is cleared to 0. + 0 + 1 + read-write + + + + + CLAIMSET + Claim Tag Set Register + 0xFA0 + 32 + read-write + 0 + 0 + + + CLAIMSET + A bit programmable register bank which sets the Claim Tag Value. Write 1 to set the bit in the claim tag. A read will return a logic 1 for all implemented locations. + 0 + 4 + read-write + + + + + CLAIMCLR + Claim Tag Clear Register + 0xFA4 + 32 + read-write + 0 + 0 + + + CLAIMCLR + A bit programmable register bank that is zero at reset. Write 1 to clear the bit in the claim tag. On reads, returns the current setting of the claim tag. + 0 + 4 + read-write + + + + + LAR + Lock Access Register + 0xFB0 + 32 + read-write + 0 + 0 + + + WriteAccessCode + Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access. + 0 + 32 + read-write + + + + + LSR + Lock Status Register + 0xFB4 + 32 + read-only + 0x1 + 0x5 + + + IMP + Lock mechanism is implemented. This bit always reads 1. + 0 + 1 + read-only + + + STATUS + Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked. + 1 + 1 + read-only + + + STATUS_0 + Access permitted. + 0 + + + STATUS_1 + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + s8BIT + Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present. + 2 + 1 + read-only + + + + + AUTHSTATUS + Authentication Status Register + 0xFB8 + 32 + read-only + 0 + 0xFFFFFF00 + + + NSID + Reads as b00, Non-secure invasive debug not supported by the ETM. + 0 + 2 + read-only + + + NSNID + Permission for Non-secure non-invasive debug. + 2 + 2 + read-only + + + NSNID_2 + Non-secure non-invasive debug disabled + 0x2 + + + NSNID_3 + Non-secure non-invasive debug enabled + 0x3 + + + + + SID + Reads as b00, Secure invasive debug not supported by the ETM. + 4 + 2 + read-only + + + SNID + Permission for Secure non-invasive debug. + 6 + 2 + read-only + + + + + DEVTYPE + CoreSight Device Type Register + 0xFCC + 32 + read-only + 0x13 + 0xFFFFFFFF + + + MajorType + Major Type and Class + 0 + 4 + read-only + + + MajorType_3 + Trace source + 0x3 + + + + + SubType + Sub Type + 4 + 4 + read-only + + + SubType_1 + Processor trace + 0x1 + + + + + + + PIDR4 + Peripheral Identification Register 4 + 0xFD0 + 32 + read-only + 0x4 + 0xFFFFFFFF + + + JEP106 + JEP106 continuation code. + 0 + 4 + read-only + + + c4KB + 4KB Count + 4 + 4 + read-only + + + + + PIDR5 + Peripheral Identification Register 5 + 0xFD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PIDR6 + Peripheral Identification Register 6 + 0xFD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PIDR7 + Peripheral Identification Register 7 + 0xFDC + 32 + read-only + 0 + 0xFFFFFFFF + + + PIDR0 + Peripheral Identification Register 0 + 0xFE0 + 32 + read-only + 0x25 + 0xFFFFFFFF + + + PartNumber + Part Number [7:0] + 0 + 8 + read-only + + + + + PIDR1 + Peripheral Identification Register 1 + 0xFE4 + 32 + read-only + 0xB9 + 0xFFFFFFFF + + + PartNumber + Part Number [11:8] + 0 + 4 + read-only + + + JEP106_identity_code + JEP106 identity code [3:0] + 4 + 4 + read-only + + + + + PIDR2 + Peripheral Identification Register 2 + 0xFE8 + 32 + read-only + 0xB + 0xFFFFFFFF + + + JEP106_identity_code + JEP106 identity code [6:4] + 0 + 3 + read-only + + + Revision + Revision + 4 + 4 + read-only + + + + + PIDR3 + Peripheral Identification Register 3 + 0xFEC + 32 + read-only + 0 + 0xFFFFFFFF + + + CustomerModified + Customer Modified. + 0 + 4 + read-only + + + RevAnd + RevAnd + 4 + 4 + read-only + + + + + CIDR0 + Component Identification Register 0 + 0xFF0 + 32 + read-only + 0xD + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CIDR1 + Component Identification Register 1 + 0xFF4 + 32 + read-only + 0x90 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 4 + read-only + + + ComponentClass + Component class + 4 + 4 + read-only + + + ComponentClass_1 + ROM table. + 0x1 + + + ComponentClass_9 + CoreSight component. + 0x9 + + + ComponentClass_15 + PrimeCell of system component with no standardized register layout, for backward compatibility. + 0xF + + + + + + + CIDR2 + Component Identification Register 2 + 0xFF8 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + CIDR3 + Component Identification Register 3 + 0xFFC + 32 + read-only + 0xB1 + 0xFFFFFFFF + + + Preamble + Preamble + 0 + 8 + read-only + + + + + + + MCM + MCM + MCM + 0xE0080000 + + 0 + 0x4A8 + registers + + + MCM0 + 19 + + + + CPCR + Core Platform Control + 0xC + 32 + read-write + 0 + 0xFFFFFE00 + + + CBRR + Crossbar Round-robin Arbitration Enable + 9 + 1 + read-write + + + cbrr0 + Fixed-priority arbitration + 0 + + + cbrr1 + Round-robin arbitration + 0x1 + + + + + PFLEXSTALL + Flash Stall Enable + 16 + 1 + read-write + + + pflexstall0 + Flash stall is disabled when flash is busy. + 0 + + + pflexstall1 + Flash stall is enabled when flash is busy. + 0x1 + + + + + + + ISCR + Interrupt Status and Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CWBER + Cache Write Buffer Error Status + 4 + 1 + read-write + oneToClear + + + cwber0 + No error + 0 + + + cwber1 + Error occurred + 0x1 + + + + + CPES + Cache Parity Error Status + 5 + 1 + read-only + + + cpes0 + A cache parity error is not detected. + 0 + + + cpes1 + A cache parity error is detected. + 0x1 + + + + + FIOC + FPU Invalid Operation Interrupt Status + 8 + 1 + read-only + + + fioc0 + No interrupt + 0 + + + fioc1 + Interrupt occurred + 0x1 + + + + + FDZC + FPU Divide-by-zero Interrupt Status + 9 + 1 + read-only + + + fdzc0 + No interrupt + 0 + + + fdzc1 + Interrupt occurred + 0x1 + + + + + FOFC + FPU Overflow Interrupt Status + 10 + 1 + read-only + + + fofc0 + No interrupt + 0 + + + fofc1 + Interrupt occurred + 0x1 + + + + + FUFC + FPU Underflow Interrupt status + 11 + 1 + read-only + + + fufc0 + No interrupt + 0 + + + fufc1 + Interrupt occurred + 0x1 + + + + + FIXC + FPU Inexact Interrupt Status + 12 + 1 + read-only + + + fixc0 + No interrupt + 0 + + + fixc1 + Interrupt occurred + 0x1 + + + + + FIDC + FPU Input Denormal Interrupt Status + 15 + 1 + read-only + + + fidc0 + No interrupt + 0 + + + fidc1 + Interrupt occurred + 0x1 + + + + + CWBEE + Cache Write Buffer Error Enable + 20 + 1 + read-write + + + cwbee0 + Disable error interrupt + 0 + + + cwbee1 + Enable error interrupt + 0x1 + + + + + CPEE + Cache Parity Error Enable + 21 + 1 + read-write + + + cpee0 + Disable error interrupt. + 0 + + + cpee1 + Enable error interrupt. + 0x1 + + + + + FIOCE + FPU Invalid Operation Interrupt Enable + 24 + 1 + read-write + + + fioce0 + Disable interrupt + 0 + + + fioce1 + Enable interrupt + 0x1 + + + + + FDZCE + FPU Divide-by-zero Interrupt Enable + 25 + 1 + read-write + + + fdzce0 + Disable interrupt + 0 + + + fdzce1 + Enable interrupt + 0x1 + + + + + FOFCE + FPU Overflow Interrupt Enable + 26 + 1 + read-write + + + fofce0 + Disable interrupt + 0 + + + fofce1 + Enable interrupt + 0x1 + + + + + FUFCE + FPU Underflow Interrupt Enable + 27 + 1 + read-write + + + fufce0 + Disable interrupt + 0 + + + fufce1 + Enable interrupt + 0x1 + + + + + FIXCE + FPU Inexact Interrupt Enable + 28 + 1 + read-write + + + fixce0 + Disable interrupt + 0 + + + fixce1 + Enable interrupt + 0x1 + + + + + FIDCE + FPU Input Denormal Interrupt Enable + 31 + 1 + read-write + + + fidce0 + Disable interrupt + 0 + + + fidce1 + Enable interrupt + 0x1 + + + + + + + FADR + Write Buffer Fault Address + 0x20 + 32 + read-only + 0 + 0 + + + ADDRESS + Fault address + 0 + 32 + read-only + + + + + FATR + Store Buffer Fault Attributes + 0x24 + 32 + read-only + 0 + 0 + + + BEDA + Bus Error Data Access Type + 0 + 1 + read-only + + + beda0 + Instruction + 0 + + + beda1 + Data + 0x1 + + + + + BEMD + Bus Error Privilege level + 1 + 1 + read-only + + + bemd0 + User mode + 0 + + + bemd1 + Supervisor/privileged mode + 0x1 + + + + + BESZ + Bus Error Size + 4 + 2 + read-only + + + besz00 + 8-bit access + 0 + + + besz01 + 16-bit access + 0x1 + + + besz10 + 32-bit access + 0x2 + + + + + BEWT + Bus Error Write + 7 + 1 + read-only + + + bewt0 + Read access + 0 + + + bewt1 + Write access + 0x1 + + + + + BEMN + Bus Error Master Number + 8 + 4 + read-only + + + BEOVR + Bus Error Overrun + 31 + 1 + read-only + + + beovr0 + No bus error overrun + 0 + + + beovr1 + Bus error overrun occurred. The FADR and FDR registers and the other FATR bits will not be updated to reflect this new bus error. + 0x1 + + + + + + + FDR + Store Buffer Fault Data + 0x28 + 32 + read-only + 0 + 0 + + + DATA + Fault Data + 0 + 32 + read-only + + + + + CPCR2 + Core Platform Control 2 + 0x34 + 32 + read-write + 0x10040 + 0xFFFFFFFF + + + CCBC + Clear Code Bus Cache + 0 + 1 + read-write + + + ccbc0 + No effect + 0 + + + ccbc1 + Clear code bus cache + 0x1 + + + + + DCCWB + Disable Code Cache Write Buffer + 1 + 1 + read-write + + + dccwb0 + Enable code cache write buffer + 0 + + + dccwb1 + Disable code cache write buffer + 0x1 + + + + + FCCNA + Force Code Cache to No Allocation + 2 + 1 + read-write + + + fccna0 + Force code cache to allocation + 0 + + + fccna1 + Force code cache to no allocation + 0x1 + + + + + DCBC + Disable Code Bus cache + 3 + 1 + read-write + + + dcbc0 + Enable code bus cache + 0 + + + dcbc1 + Disable code bus cache + 0x1 + + + + + CBCS + Code Bus Cache Size + 4 + 4 + read-only + + + cbcs0000 + 0 KB + 0 + + + cbcs0001 + 1 KB + 0x1 + + + cbcs0010 + 2 KB + 0x2 + + + cbcs0011 + 4 KB + 0x3 + + + cbcs0100 + 8 KB + 0x4 + + + cbcs0101 + 16 KB + 0x5 + + + cbcs0110 + 32 KB + 0x6 + + + + + PCCMCTRL + Bypass Fixed Code Cache Map + 16 + 1 + read-only + + + pccmctrl0 + The fixed code cache map is not bypassed + 0 + + + pccmctrl1 + The fixed code cache map is bypassed + 0x1 + + + + + LCCPWB + Limit Code Cache Peripheral Write Buffering + 17 + 1 + read-write + + + lccpwb0 + Code cache peripheral write buffering is not limited: if write buffer is enabled, bufferable write is buffered. + 0 + + + lccpwb1 + Code cache peripheral write buffering is limited: only bufferable and cachable write is buffered. + 0x1 + + + + + + + LMDR2 + Local Memory Descriptor 2 + 0x408 + 32 + read-write + 0x84844000 + 0xFFFFFFFF + + + PCPME + PC Parity Enable + 5 + 1 + read-write + + + pcpme0 + PC parity is disabled. + 0 + + + pcpme1 + PC parity is enabled. + 0x1 + + + + + PCPFE + PC Parity Fault Report Enable + 7 + 1 + read-write + + + pcpfe0 + PC parity fault report is disabled. + 0 + + + pcpfe1 + PC parity fault report is enabled. + 0x1 + + + + + MT + Memory Type + 13 + 3 + read-only + + + mt000 + SRAM_L + 0 + + + mt001 + SRAM_U + 0x1 + + + mt010 + PC Cache + 0x2 + + + mt011 + PS Cache + 0x3 + + + + + RO + Read-Only + 16 + 1 + read-write + + + ro0 + Writes to the corresponding LMDRn[7:0] are allowed. + 0 + + + ro1 + Writes to the corresponding LMDRn[7:0] are ignored. + 0x1 + + + + + DPW + LMEM Data Path Width + 17 + 3 + read-only + + + dpw010 + LMEMn 32-bit wide + 0x2 + + + dpw011 + LMEMn 64-bit wide + 0x3 + + + + + WY + Level 1 Cache Ways + 20 + 4 + read-only + + + wy0000 + No Cache + 0 + + + wy0010 + 2-Way Set Associative + 0x2 + + + wy0100 + 4-Way Set Associative + 0x4 + + + wy1000 + 8-Way Set Associative + 0x8 + + + + + LMSZ + LMEM Size + 24 + 4 + read-only + + + lmsz0000 + no LMEMn (0 KB) + 0 + + + lmsz0001 + 1 KB LMEMn + 0x1 + + + lmsz0010 + 2 KB LMEMn + 0x2 + + + lmsz0011 + 4 KB LMEMn + 0x3 + + + lmsz0100 + 8 KB LMEMn + 0x4 + + + lmsz0101 + 16 KB LMEMn + 0x5 + + + lmsz0110 + 32 KB LMEMn + 0x6 + + + lmsz0111 + 64 KB LMEMn + 0x7 + + + lmsz1000 + 128 KB LMEMn + 0x8 + + + lmsz1001 + 256 KB LMEMn + 0x9 + + + lmsz1010 + 512 KB LMEMn + 0xA + + + lmsz1011 + 1024 KB LMEMn + 0xB + + + lmsz1100 + 2048 KB LMEMn + 0xC + + + lmsz1101 + 4096 KB LMEMn + 0xD + + + lmsz1110 + 8192 KB LMEMn + 0xE + + + lmsz1111 + 16384 KB LMEMn + 0xF + + + + + LMSZH + LMEM Size Hole + 28 + 1 + read-only + + + lmszh0 + LMEMn is a power-of-2 capacity. + 0 + + + lmszh1 + LMEMn is a capacity of 0.75 * LMSZ. + 0x1 + + + + + V + Valid + 31 + 1 + read-only + + + v0 + LMEMn is not present. + 0 + + + v1 + LMEMn is present. + 0x1 + + + + + + + LMPECR + LMEM Parity Control + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + ECPR + Enable Cache Parity Reporting + 20 + 1 + read-write + + + ecpr0 + Cache parity reporting is disabled + 0 + + + ecpr1 + Cache parity reporting is enabled + 0x1 + + + + + + + LMPEIR + LMEM Parity Interrupt + 0x488 + 32 + read-write + 0 + 0xFFFFFFFF + + + PE + Parity Error + 16 + 8 + read-write + oneToClear + + + PEELOC + Error Location + 24 + 5 + read-only + + + V + Valid bit + 31 + 1 + read-only + + + + + LMFAR + LMEM Fault Address + 0x490 + 32 + read-only + 0 + 0xFFFFFFFF + + + EFADD + Fault Address + 0 + 32 + read-only + + + + + LMFATR + LMEM Fault Attribute + 0x494 + 32 + read-only + 0 + 0xFFFFFFFF + + + PEFPRT + Parity Fault Protection Signal + 0 + 4 + read-only + + + PEFSIZE + PEFSIZE + 4 + 3 + read-only + + + sbcs000 + 8-bit access + 0 + + + sbcs001 + 16-bit access + 0x1 + + + sbcs010 + 32-bit access + 0x2 + + + sbcs011 + 64-bit access + 0x3 + + + + + PEFW + Parity Fault Write + 7 + 1 + read-only + + + pefw0 + Read fault + 0 + + + pefw1 + Write fault + 0x1 + + + + + BKD + Backdoor Access + 15 + 1 + read-only + + + bkd0 + Core access + 0 + + + bkd1 + Backdoor access + 0x1 + + + + + PEFSYN + Parity Fault Syndrome + 16 + 8 + read-only + + + OVR + Overrun + 31 + 1 + read-only + + + ovr0 + There is sigle fault or no fault. + 0 + + + ovr1 + There are multiple faults + 0x1 + + + + + + + LMFDHR + LMEM Fault Data High + 0x4A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PEFDH + PEFDH + 0 + 32 + read-only + + + + + LMFDLR + LMEM Fault Data Low + 0x4A4 + 32 + read-only + 0 + 0xFFFFFFFF + + + PEFDL + PEFDL + 0 + 32 + read-only + + + + + + + \ No newline at end of file diff --git a/RW610/RW610.xml b/RW610/RW610.xml index b902613..bd2824b 100644 --- a/RW610/RW610.xml +++ b/RW610/RW610.xml @@ -3,9 +3,9 @@ nxp.com RW610 1.0 - RW610ETA1I,RW610HNA1I,RW610UKA1I + RW610ETA2I,RW610HNA2I,RW610UKA2I -Copyright 2016-2023 NXP +Copyright 2016-2024 NXP SPDX-License-Identifier: BSD-3-Clause @@ -31487,6 +31487,11 @@ SPDX-License-Identifier: BSD-3-Clause DMAC1_OTRIG_CH31 0x1F + + DMAC1_OTRIG_CH32 + DMAC1_OTRIG_CH32 + 0x20 + @@ -38423,7 +38428,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - MRT0 + MRT 9 @@ -38431,7 +38436,7 @@ SPDX-License-Identifier: BSD-3-Clause 4 0x10 CHANNEL[%s] - no description available + Array of registers: INTVAL, TIMER, CTRL, STAT 0 INTVAL @@ -43340,6 +43345,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x64 registers + + GAU_ADC0 + 112 + ADC_REG_CMD @@ -44309,6 +44318,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x64 registers + + GAU_ADC1 + 111 + GAU_DAC0 @@ -44320,6 +44333,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x38 registers + + GAU_DAC + 108 + CTRL @@ -45228,6 +45245,14 @@ SPDX-License-Identifier: BSD-3-Clause 0x50 registers + + GAU_ACOMP_WKUP + 109 + + + GAU_ACOMP + 110 + CTRL0 @@ -47137,7 +47162,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - MRT1 + GFMRT 23 @@ -47145,7 +47170,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x10 CHANNEL[%s] - no description available + Array of registers: INTVAL, TIMER, CTRL, STAT 0 INTVAL @@ -47481,7 +47506,7 @@ SPDX-License-Identifier: BSD-3-Clause 2 0x20 BYTE_PIN[%s] - no description available + Array of registers: B_[%s] 0 32 @@ -47508,7 +47533,7 @@ SPDX-License-Identifier: BSD-3-Clause 2 0x80 WORD_PIN[%s] - no description available + Array of registers: W_[%s] 0x1000 32 @@ -62771,7 +62796,7 @@ SPDX-License-Identifier: BSD-3-Clause 33 0x10 CHANNEL[%s] - no description available + Array of registers: CFG, CTLSTAT, XFERCFG 0x400 CFG @@ -72148,11 +72173,11 @@ SPDX-License-Identifier: BSD-3-Clause registers - DMIC0 + DMIC 25 - HWVAD0 + HWVAD 29 @@ -72160,7 +72185,7 @@ SPDX-License-Identifier: BSD-3-Clause 4 0x100 CHANNEL[%s] - no description available + Array of registers: OSR, DIVHFCLK, PREAC2FSCOEF, PREAC4FSCOEF, GAINSHIFT, FIFO_CTRL, FIFO_STATUS, FIFO_DATA, PHY_CTRL, DC_CTRL 0 OSR @@ -73091,7 +73116,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - LCDIC + LCD 61 @@ -82758,7 +82783,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - OS_EVENT + OS_EVENT_TIMER 41 @@ -83579,6 +83604,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x280 registers + + USB + 50 + ID @@ -96089,7 +96118,7 @@ SPDX-License-Identifier: BSD-3-Clause 16 0x8 EVENT[%s] - no description available + Array of registers: EV_STATE, EV_CTRL 0x300 EV_STATE @@ -96292,7 +96321,7 @@ SPDX-License-Identifier: BSD-3-Clause 10 0x8 OUT[%s] - no description available + Array of registers: OUT_SET, OUT_CLR 0x500 OUT_SET @@ -96343,14 +96372,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x1000 registers - - HYPERVISOR - 27 - - - SECUREVIOLATION - 28 - 4 @@ -100035,17 +100056,41 @@ SPDX-License-Identifier: BSD-3-Clause SEC_GP_REG0_LOCK - 2'b10: sec_reg_reg0 can be written. All other values: sec_reg_reg0 can't be written. + SEC_GPIO_MASK0 write-lock 0 2 read-write + + + CANNOT_BE_WRITTEN + SEC_GPIO_MASK0 cannot be written + 0x1 + + + CAN_BE_WRITTEN + SEC_GPIO_MASK0 can be written + 0x2 + + SEC_GP_REG1_LOCK - 2'b10: sec_reg_reg1 can be written. All other values: sec_reg_reg1 can't be written. + SEC_GPIO_MASK1 write-lock 2 2 read-write + + + CANNOT_BE_WRITTEN + SEC_GPIO_MASK1 cannot be written + 0x1 + + + CAN_BE_WRITTEN + SEC_GPIO_MASK1 can be written + 0x2 + + @@ -100123,10 +100168,22 @@ SPDX-License-Identifier: BSD-3-Clause MASTER_SEC_LEVEL_LOCK - master_sec_reg write-lock. When 2'b10, this register can be written. With any other value, this register can't be written. + MASTER_SEC_REG write-lock 30 2 read-write + + + CANNOT_BE_WRITTEN + MASTER_SEC_REG cannot be written + 0x1 + + + CAN_BE_WRITTEN + MASTER_SEC_REG can be written + 0x2 + + @@ -100204,10 +100261,22 @@ SPDX-License-Identifier: BSD-3-Clause MASTER_SEC_LEVEL_ANTIPOL_LOCK - master_sec_antipol_reg register write-lock. When 2'b10, this register can be written. With any other value, this register can't be written. + MASTER_SEC_ANTIPOL_REG write-lock 30 2 read-write + + + CANNOT_BE_WRITTEN + MASTER_SEC_ANTIPOL_REG cannot be written + 0x1 + + + CAN_BE_WRITTEN + MASTER_SEC_ANTIPOL_REG can be written + 0x2 + + @@ -100222,45 +100291,117 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_VTOR - 2'b10: m33 LOCKNSVTOR is 0. All other values: m33 LOCKNSVTOR is 1 + LOCK_NS_VTOR write-lock 0 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_NS_MPU - 2'b10:m33 LOCKNSMPU is 0. All other values: m33 LOCKNSMPU is 1 + LOCK_NS_MPU write-lock 2 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_S_VTAIRCR - 2'b10:m33 LOCKSVTAURCR is 0. All other values: m33 LOCKSVTAURCR is 1 + LOCK_S_VTAIRCR write-lock 4 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_S_MPU - 2'b10:m33 LOCKSMPU is 0. All other values: m33 LOCKSMPU is 1 + LOCK_S_MPU write-lock 6 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_SAU - 2'b10:m33 LOCKSAU is 0. All other values: m33 LOCKSAU is 1 + LOCK_SAU write-lock 8 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + M33_LOCK_REG_LOCK - 2'b10: this register can be written. All other values: this register can't be written + CM33_LOCK_REG write-lock 30 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + @@ -100275,10 +100416,22 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock + Write lock 0 2 read-write + + + LOCKED + Writes to secure_ctrl_group registers and this register itself are not allowed + 0x1 + + + NOT_LOCKED + Writes to secure_ctrl_group registers and this register itself are allowed + 0x2 + + ENABLE_SECURE_CHECKING @@ -100310,17 +100463,51 @@ SPDX-License-Identifier: BSD-3-Clause DISABLE_STRICT_MODE - 00, 11, 10 = Simple master in strict mode + Disable strict mode 10 2 read-write + + + AHBSM0 + Simple master in strict mode. Can read and write to memories at same level only. + 0 + + + AHBTM + Simple master in tier mode. Can read and write to memories at the same or below level. + 0x1 + + + AHBSM2 + Simple master in strict mode. Can read and write to memories at same level only. + 0x2 + + + AHBSM3 + Simple master in strict mode. Can read and write to memories at same level only. + 0x3 + + IDAU_ALL_NS - 00, 11, 10 : IDAU is enabled + Disable IDAU 14 2 read-write + + + DISABLED + IDAU is disabled, hence all memories are attributed as non-secure memory. + 0x1 + + + ENABLED + IDAU is enabled. (restrictive mode) + 0x2 + + @@ -100335,10 +100522,22 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock + Write lock 0 2 read-write + + + LOCKED + Writes to secure_ctrl_group registers and this register itself are not allowed + 0x1 + + + NOT_LOCKED + Writes to secure_ctrl_group registers and this register itself are allowed + 0x2 + + ENABLE_SECURE_CHECKING @@ -100370,17 +100569,51 @@ SPDX-License-Identifier: BSD-3-Clause DISABLE_STRICT_MODE - 00, 11, 10 = Simple master in strict mode + Disable strict mode 10 2 read-write + + + AHBSM0 + Simple master in strict mode. Can read and write to memories at same level only. + 0 + + + AHBTM + Simple master in tier mode. Can read and write to memories at the same or below level. + 0x1 + + + AHBSM2 + Simple master in strict mode. Can read and write to memories at same level only. + 0x2 + + + AHBSM3 + Simple master in strict mode. Can read and write to memories at same level only. + 0x3 + + IDAU_ALL_NS - 00, 11, 10 : IDAU is enabled + Disable IDAU 14 2 read-write + + + DISABLED + IDAU is disabled, hence all memories are attributed as non-secure memory. + 0x1 + + + ENABLED + IDAU is enabled. (restrictive mode) + 0x2 + + @@ -100397,7 +100630,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - CDOG + CDOG_INT 107 diff --git a/RW612/RW612.xml b/RW612/RW612.xml index c6aef60..dceeb5a 100644 --- a/RW612/RW612.xml +++ b/RW612/RW612.xml @@ -3,9 +3,9 @@ nxp.com RW612 1.0 - RW612ETA1I,RW612HNA1I,RW612UKA1I + RW612ETA2I,RW612HNA2I,RW612UKA2I -Copyright 2016-2023 NXP +Copyright 2016-2024 NXP SPDX-License-Identifier: BSD-3-Clause @@ -31487,6 +31487,11 @@ SPDX-License-Identifier: BSD-3-Clause DMAC1_OTRIG_CH31 0x1F + + DMAC1_OTRIG_CH32 + DMAC1_OTRIG_CH32 + 0x20 + @@ -38423,7 +38428,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - MRT0 + MRT 9 @@ -38431,7 +38436,7 @@ SPDX-License-Identifier: BSD-3-Clause 4 0x10 CHANNEL[%s] - no description available + Array of registers: INTVAL, TIMER, CTRL, STAT 0 INTVAL @@ -43340,6 +43345,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x64 registers + + GAU_ADC0 + 112 + ADC_REG_CMD @@ -44309,6 +44318,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x64 registers + + GAU_ADC1 + 111 + GAU_DAC0 @@ -44320,6 +44333,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x38 registers + + GAU_DAC + 108 + CTRL @@ -45228,6 +45245,14 @@ SPDX-License-Identifier: BSD-3-Clause 0x50 registers + + GAU_ACOMP_WKUP + 109 + + + GAU_ACOMP + 110 + CTRL0 @@ -47137,7 +47162,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - MRT1 + GFMRT 23 @@ -47145,7 +47170,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x10 CHANNEL[%s] - no description available + Array of registers: INTVAL, TIMER, CTRL, STAT 0 INTVAL @@ -47481,7 +47506,7 @@ SPDX-License-Identifier: BSD-3-Clause 2 0x20 BYTE_PIN[%s] - no description available + Array of registers: B_[%s] 0 32 @@ -47508,7 +47533,7 @@ SPDX-License-Identifier: BSD-3-Clause 2 0x80 WORD_PIN[%s] - no description available + Array of registers: W_[%s] 0x1000 32 @@ -62771,7 +62796,7 @@ SPDX-License-Identifier: BSD-3-Clause 33 0x10 CHANNEL[%s] - no description available + Array of registers: CFG, CTLSTAT, XFERCFG 0x400 CFG @@ -72148,11 +72173,11 @@ SPDX-License-Identifier: BSD-3-Clause registers - DMIC0 + DMIC 25 - HWVAD0 + HWVAD 29 @@ -72160,7 +72185,7 @@ SPDX-License-Identifier: BSD-3-Clause 4 0x100 CHANNEL[%s] - no description available + Array of registers: OSR, DIVHFCLK, PREAC2FSCOEF, PREAC4FSCOEF, GAINSHIFT, FIFO_CTRL, FIFO_STATUS, FIFO_DATA, PHY_CTRL, DC_CTRL 0 OSR @@ -73091,7 +73116,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - LCDIC + LCD 61 @@ -82758,7 +82783,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - OS_EVENT + OS_EVENT_TIMER 41 @@ -83579,6 +83604,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x280 registers + + USB + 50 + ID @@ -96089,7 +96118,7 @@ SPDX-License-Identifier: BSD-3-Clause 16 0x8 EVENT[%s] - no description available + Array of registers: EV_STATE, EV_CTRL 0x300 EV_STATE @@ -96292,7 +96321,7 @@ SPDX-License-Identifier: BSD-3-Clause 10 0x8 OUT[%s] - no description available + Array of registers: OUT_SET, OUT_CLR 0x500 OUT_SET @@ -96343,14 +96372,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x1000 registers - - HYPERVISOR - 27 - - - SECUREVIOLATION - 28 - 4 @@ -100035,17 +100056,41 @@ SPDX-License-Identifier: BSD-3-Clause SEC_GP_REG0_LOCK - 2'b10: sec_reg_reg0 can be written. All other values: sec_reg_reg0 can't be written. + SEC_GPIO_MASK0 write-lock 0 2 read-write + + + CANNOT_BE_WRITTEN + SEC_GPIO_MASK0 cannot be written + 0x1 + + + CAN_BE_WRITTEN + SEC_GPIO_MASK0 can be written + 0x2 + + SEC_GP_REG1_LOCK - 2'b10: sec_reg_reg1 can be written. All other values: sec_reg_reg1 can't be written. + SEC_GPIO_MASK1 write-lock 2 2 read-write + + + CANNOT_BE_WRITTEN + SEC_GPIO_MASK1 cannot be written + 0x1 + + + CAN_BE_WRITTEN + SEC_GPIO_MASK1 can be written + 0x2 + + @@ -100123,10 +100168,22 @@ SPDX-License-Identifier: BSD-3-Clause MASTER_SEC_LEVEL_LOCK - master_sec_reg write-lock. When 2'b10, this register can be written. With any other value, this register can't be written. + MASTER_SEC_REG write-lock 30 2 read-write + + + CANNOT_BE_WRITTEN + MASTER_SEC_REG cannot be written + 0x1 + + + CAN_BE_WRITTEN + MASTER_SEC_REG can be written + 0x2 + + @@ -100204,10 +100261,22 @@ SPDX-License-Identifier: BSD-3-Clause MASTER_SEC_LEVEL_ANTIPOL_LOCK - master_sec_antipol_reg register write-lock. When 2'b10, this register can be written. With any other value, this register can't be written. + MASTER_SEC_ANTIPOL_REG write-lock 30 2 read-write + + + CANNOT_BE_WRITTEN + MASTER_SEC_ANTIPOL_REG cannot be written + 0x1 + + + CAN_BE_WRITTEN + MASTER_SEC_ANTIPOL_REG can be written + 0x2 + + @@ -100222,45 +100291,117 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_VTOR - 2'b10: m33 LOCKNSVTOR is 0. All other values: m33 LOCKNSVTOR is 1 + LOCK_NS_VTOR write-lock 0 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_NS_MPU - 2'b10:m33 LOCKNSMPU is 0. All other values: m33 LOCKNSMPU is 1 + LOCK_NS_MPU write-lock 2 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_S_VTAIRCR - 2'b10:m33 LOCKSVTAURCR is 0. All other values: m33 LOCKSVTAURCR is 1 + LOCK_S_VTAIRCR write-lock 4 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_S_MPU - 2'b10:m33 LOCKSMPU is 0. All other values: m33 LOCKSMPU is 1 + LOCK_S_MPU write-lock 6 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + LOCK_SAU - 2'b10:m33 LOCKSAU is 0. All other values: m33 LOCKSAU is 1 + LOCK_SAU write-lock 8 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + M33_LOCK_REG_LOCK - 2'b10: this register can be written. All other values: this register can't be written + CM33_LOCK_REG write-lock 30 2 read-write + + + LOCKED + Writes to this register are not allowed + 0x1 + + + NOT_LOCKED + Writes to this register are allowed + 0x2 + + @@ -100275,10 +100416,22 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock + Write lock 0 2 read-write + + + LOCKED + Writes to secure_ctrl_group registers and this register itself are not allowed + 0x1 + + + NOT_LOCKED + Writes to secure_ctrl_group registers and this register itself are allowed + 0x2 + + ENABLE_SECURE_CHECKING @@ -100310,17 +100463,51 @@ SPDX-License-Identifier: BSD-3-Clause DISABLE_STRICT_MODE - 00, 11, 10 = Simple master in strict mode + Disable strict mode 10 2 read-write + + + AHBSM0 + Simple master in strict mode. Can read and write to memories at same level only. + 0 + + + AHBTM + Simple master in tier mode. Can read and write to memories at the same or below level. + 0x1 + + + AHBSM2 + Simple master in strict mode. Can read and write to memories at same level only. + 0x2 + + + AHBSM3 + Simple master in strict mode. Can read and write to memories at same level only. + 0x3 + + IDAU_ALL_NS - 00, 11, 10 : IDAU is enabled + Disable IDAU 14 2 read-write + + + DISABLED + IDAU is disabled, hence all memories are attributed as non-secure memory. + 0x1 + + + ENABLED + IDAU is enabled. (restrictive mode) + 0x2 + + @@ -100335,10 +100522,22 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock + Write lock 0 2 read-write + + + LOCKED + Writes to secure_ctrl_group registers and this register itself are not allowed + 0x1 + + + NOT_LOCKED + Writes to secure_ctrl_group registers and this register itself are allowed + 0x2 + + ENABLE_SECURE_CHECKING @@ -100370,17 +100569,51 @@ SPDX-License-Identifier: BSD-3-Clause DISABLE_STRICT_MODE - 00, 11, 10 = Simple master in strict mode + Disable strict mode 10 2 read-write + + + AHBSM0 + Simple master in strict mode. Can read and write to memories at same level only. + 0 + + + AHBTM + Simple master in tier mode. Can read and write to memories at the same or below level. + 0x1 + + + AHBSM2 + Simple master in strict mode. Can read and write to memories at same level only. + 0x2 + + + AHBSM3 + Simple master in strict mode. Can read and write to memories at same level only. + 0x3 + + IDAU_ALL_NS - 00, 11, 10 : IDAU is enabled + Disable IDAU 14 2 read-write + + + DISABLED + IDAU is disabled, hence all memories are attributed as non-secure memory. + 0x1 + + + ENABLED + IDAU is enabled. (restrictive mode) + 0x2 + + @@ -100397,7 +100630,7 @@ SPDX-License-Identifier: BSD-3-Clause registers - CDOG + CDOG_INT 107