diff --git a/deps/v8/src/execution/riscv64/simulator-riscv64.cc b/deps/v8/src/execution/riscv64/simulator-riscv64.cc index 3ec0c0e81179bb..92f2833a49c41a 100644 --- a/deps/v8/src/execution/riscv64/simulator-riscv64.cc +++ b/deps/v8/src/execution/riscv64/simulator-riscv64.cc @@ -60,6 +60,164 @@ #include "src/runtime/runtime-utils.h" #include "src/utils/ostreams.h" +// RVV +// The following code about RVV was based from: +// https://github.com/riscv/riscv-isa-sim +// Copyright (c) 2010-2017, The Regents of the University of California +// (Regents). All Rights Reserved. + +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// 3. Neither the name of the Regents nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. + +// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, +// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF +// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +template +struct type_usew_t; +template <> +struct type_usew_t<8> { + using type = uint8_t; +}; + +template <> +struct type_usew_t<16> { + using type = uint16_t; +}; + +template <> +struct type_usew_t<32> { + using type = uint32_t; +}; + +template <> +struct type_usew_t<64> { + using type = uint64_t; +}; + +template <> +struct type_usew_t<128> { + using type = __uint128_t; +}; +template +struct type_sew_t; + +template <> +struct type_sew_t<8> { + using type = int8_t; +}; + +template <> +struct type_sew_t<16> { + using type = int16_t; +}; + +template <> +struct type_sew_t<32> { + using type = int32_t; +}; + +template <> +struct type_sew_t<64> { + using type = int64_t; +}; + +template <> +struct type_sew_t<128> { + using type = __int128_t; +}; + +#define VV_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VV_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VX_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VX_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type rs1 = (type_usew_t::type)(get_register(rs1_reg())); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VN_PARAMS(x) \ + constexpr int half_x = x >> 1; \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type uimm5 = (type_sew_t::type)(instr_.RvvUimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VN_UPARAMS(x) \ + constexpr int half_x = x >> 1; \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VXI_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); \ + type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ + type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); + +#define VI_XI_SLIDEDOWN_PARAMS(x, off) \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i + off); + +#define VI_XI_SLIDEUP_PARAMS(x, offset) \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i - offset); + +/* Vector Integer Extension */ +#define VI_VIE_PARAMS(x, scale) \ + if ((x / scale) < 8) UNREACHABLE(); \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_VIE_UPARAMS(x, scale) \ + if ((x / scale) < 8) UNREACHABLE(); \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + namespace v8 { namespace internal {