- Ain Shams Faculty Of Engineering
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BETA-processor
BETA-processor PublicMIT 6.004x Beta RISC processor Implemented and synthesized on an FPGA. This is the Verilog version of the Beta with all the testbenches required.
C 3
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University-Projects
University-Projects PublicThis is where all the projects i did for Online courses, Student activites, self projects are posted
C# 1
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i2c_draft_gsoc
i2c_draft_gsoc PublicA simple low power I2c slave, this is just a prototype
Verilog 1
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pandoc_assignment_template
pandoc_assignment_template PublicA pandoc template for my assignments based on https://github.com/Wandmalfarbe/pandoc-latex-template
TeX 1
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OS_CLASS_PROJECTS
OS_CLASS_PROJECTS PublicAll the projects required in this year Operating systems class exist here
C
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