diff --git a/.scalafmt.conf b/.scalafmt.conf
new file mode 100644
index 0000000..f74e550
--- /dev/null
+++ b/.scalafmt.conf
@@ -0,0 +1,26 @@
+version = 2.6.4
+
+maxColumn = 120
+align = most
+continuationIndent.defnSite = 2
+assumeStandardLibraryStripMargin = true
+docstrings = ScalaDoc
+lineEndings = preserve
+includeCurlyBraceInSelectChains = false
+danglingParentheses = true
+
+align.tokens.add = [
+  {
+    code = ":"
+  }
+]
+
+newlines.alwaysBeforeCurlyBraceLambdaParams = false
+newlines.alwaysBeforeMultilineDef = false
+newlines.implicitParamListModifierForce = [before]
+
+verticalMultiline.atDefnSite = true
+
+optIn.annotationNewlines = true
+
+rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix]
diff --git a/tilelink/src/bundle/TLChannelParameter.scala b/tilelink/src/bundle/TLChannelParameter.scala
index 6c2d4ed..41081ad 100644
--- a/tilelink/src/bundle/TLChannelParameter.scala
+++ b/tilelink/src/bundle/TLChannelParameter.scala
@@ -8,7 +8,7 @@ import upickle.default.{macroRW, ReadWriter => RW}
 
 sealed trait TLChannelParameter
 
-object TLChannelParameter        {
+object TLChannelParameter {
   implicit val rw: RW[TLChannelParameter] = RW.merge(
     TileLinkChannelAParameter.rw,
     TileLinkChannelBParameter.rw,
diff --git a/tilelink/src/bundle/TLLinkParameter.scala b/tilelink/src/bundle/TLLinkParameter.scala
index aea6d54..d5c47d3 100644
--- a/tilelink/src/bundle/TLLinkParameter.scala
+++ b/tilelink/src/bundle/TLLinkParameter.scala
@@ -31,13 +31,13 @@ case class TLLinkParameter(
     "Width of data field in bytes must be power of 2"
   )
 
-  def channelAParameter: TileLinkChannelAParameter         =
+  def channelAParameter: TileLinkChannelAParameter =
     TileLinkChannelAParameter(addressWidth, sourceWidth, dataWidth, sizeWidth)
   def channelBParameter: Option[TileLinkChannelBParameter] =
     Option.when(hasBCEChannels)(TileLinkChannelBParameter(addressWidth, sourceWidth, dataWidth, sizeWidth))
   def channelCParameter: Option[TileLinkChannelCParameter] =
     Option.when(hasBCEChannels)(TileLinkChannelCParameter(addressWidth, sourceWidth, dataWidth, sizeWidth))
-  def channelDParameter: TileLinkChannelDParameter         =
+  def channelDParameter: TileLinkChannelDParameter =
     TileLinkChannelDParameter(sourceWidth, sinkWidth, dataWidth, sizeWidth)
   def channelEParameter: Option[TileLinkChannelEParameter] =
     Option.when(hasBCEChannels)(TileLinkChannelEParameter(sinkWidth))
diff --git a/tilelink/src/xbar/TLArbiter.scala b/tilelink/src/xbar/TLArbiter.scala
index e16c96d..00852f2 100644
--- a/tilelink/src/xbar/TLArbiter.scala
+++ b/tilelink/src/xbar/TLArbiter.scala
@@ -12,8 +12,8 @@ import utils.rightOR
 import upickle.default.{macroRW, ReadWriter => RW}
 
 sealed trait TLArbiterPolicy
-object TLArbiterPolicy    {
-  case object Priority   extends TLArbiterPolicy {
+object TLArbiterPolicy {
+  case object Priority extends TLArbiterPolicy {
     implicit val rw: RW[this.type] = macroRW
   }
   case object RoundRobin extends TLArbiterPolicy {
@@ -23,33 +23,33 @@ object TLArbiterPolicy    {
 }
 
 case class TLArbiterParameter(
-                               policy:              TLArbiterPolicy,
-                               inputLinkParameters: Seq[TLChannelParameter],
-                               outputLinkParameter: TLChannelParameter)
-  extends chisel3.experimental.SerializableModuleParameter
+  policy:              TLArbiterPolicy,
+  inputLinkParameters: Seq[TLChannelParameter],
+  outputLinkParameter: TLChannelParameter)
+    extends chisel3.experimental.SerializableModuleParameter
 object TLArbiterParameter {
   implicit val rw: RW[TLArbiterParameter] = macroRW
 }
 
 class TLArbiter(val parameter: TLArbiterParameter)
-  extends Module
+    extends Module
     with chisel3.experimental.SerializableModule[TLArbiterParameter] {
 
   // (width, valid_s, select) => ready_s
   val policyImpl: (Integer, UInt, Bool) => UInt = {
     parameter.policy match {
-      case TLArbiterPolicy.Priority   =>
+      case TLArbiterPolicy.Priority =>
         (width, valids, _) => (~(scanLeftOr(valids) << 1)(width - 1, 0)).asUInt
       case TLArbiterPolicy.RoundRobin =>
         (width, valids, select) =>
           if (width == 1) 1.U(1.W)
           else {
-            val valid   = valids(width - 1, 0)
+            val valid = valids(width - 1, 0)
             assert(valid === valids)
-            val mask    = RegInit(((BigInt(1) << width) - 1).U(width - 1, 0))
-            val filter  = Cat(scanRightOr(valid & ~mask), valid)
+            val mask = RegInit(((BigInt(1) << width) - 1).U(width - 1, 0))
+            val filter = Cat(scanRightOr(valid & ~mask), valid)
             val unready = (filter >> 1).asUInt | (mask << width).asUInt
-            val readys  = (~((unready >> width).asUInt & unready(width - 1, 0))).asUInt
+            val readys = (~((unready >> width).asUInt & unready(width - 1, 0))).asUInt
             when(select && valid.orR) {
               mask := scanLeftOr(readys & valid)
             }
@@ -58,7 +58,7 @@ class TLArbiter(val parameter: TLArbiterParameter)
     }
   }
 
-  val sink    = IO(
+  val sink = IO(
     Flipped(
       DecoupledIO(TLChannelParameter.bundle(parameter.outputLinkParameter))
     )
@@ -67,15 +67,15 @@ class TLArbiter(val parameter: TLArbiterParameter)
 
   if (parameter.inputLinkParameters.isEmpty) {
     sink.valid := false.B
-    sink.bits  := DontCare
+    sink.bits := DontCare
   } else if (parameter.inputLinkParameters.size == 1) {
     sink <> sources.head
   } else {
     val beatsIn = sources.map(s => TLLink.numBeatsMinus1(s.bits))
 
     val beatsLeft = RegInit(0.U)
-    val idle      = beatsLeft === 0.U
-    val latch     = idle && sink.ready // TODO: winner (if any) claims sink
+    val idle = beatsLeft === 0.U
+    val latch = idle && sink.ready // TODO: winner (if any) claims sink
 
     // Who wants access to the sink?
     val valids = sources.map(_.valid)
@@ -94,11 +94,11 @@ class TLArbiter(val parameter: TLArbiterParameter)
 
     // Track remaining beats
     val maskedBeats = winner.zip(beatsIn).map { case (w, b) => Mux(w, b, 0.U) }
-    val initBeats   = maskedBeats.reduce(_ | _) // no winner => 0 beats
+    val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
     beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
 
     // The one-hot source granted access in the previous cycle
-    val state    = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
+    val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
     val muxState = Mux(idle, winner, state)
     state := muxState
 
diff --git a/tilelink/src/xbar/TLCrossBar.scala b/tilelink/src/xbar/TLCrossBar.scala
index e14c482..fb698e1 100644
--- a/tilelink/src/xbar/TLCrossBar.scala
+++ b/tilelink/src/xbar/TLCrossBar.scala
@@ -16,9 +16,10 @@ object TLCrossBar {
     select: Seq[Bool]
   ): Seq[DecoupledIO[TLChannel]] = {
     val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
-    filtered.zip(select).foreach { case (chan, selected) =>
-      chan.bits  := input.bits
-      chan.valid := input.valid && (selected || (select.size == 1).B)
+    filtered.zip(select).foreach {
+      case (chan, selected) =>
+        chan.bits := input.bits
+        chan.valid := input.valid && (selected || (select.size == 1).B)
     }
     input.ready := Mux1H(select, filtered.map(_.ready))
     filtered
@@ -32,14 +33,14 @@ class TLCrossBar(val parameter: TLCrossBarParameter)
   val masterLinksIO = parameter.masters.map(_.linkParameter).map { link =>
     IO(Flipped(new TLLink(link)))
   }
-  val slaveLinksIO  = parameter.slaves.map(_.linkParameter).map { link =>
+  val slaveLinksIO = parameter.slaves.map(_.linkParameter).map { link =>
     IO(new TLLink(link))
   }
 
   val masterLinksRemapped = Wire(
     Vec(parameter.masters.size, new TLLink(parameter.commonLinkParameter))
   )
-  val slaveLinksRemapped  = Wire(
+  val slaveLinksRemapped = Wire(
     Vec(parameter.slaves.size, new TLLink(parameter.commonLinkParameter))
   )
 
@@ -50,109 +51,113 @@ class TLCrossBar(val parameter: TLCrossBarParameter)
     .lazyZip(masterLinksIO)
     .lazyZip(masterLinksRemapped)
     .lazyZip(parameter.srcIdRemapTable)
-    .foreach { case (connects, io, remapped, range) =>
-      if (connects.exists(x => x)) {
-        remapped.a :<>= io.a
-        remapped.a.bits.source := io.a.bits.source | range.start.U
+    .foreach {
+      case (connects, io, remapped, range) =>
+        if (connects.exists(x => x)) {
+          remapped.a :<>= io.a
+          remapped.a.bits.source := io.a.bits.source | range.start.U
 
-        io.d :<>= remapped.d
-        io.d.bits.source := trim(remapped.d.bits.source, range.size)
-      } else {
-        remapped.a.valid := false.B
-        remapped.a.bits  := DontCare
-        io.a.ready       := false.B
-        io.a.bits        := DontCare
+          io.d :<>= remapped.d
+          io.d.bits.source := trim(remapped.d.bits.source, range.size)
+        } else {
+          remapped.a.valid := false.B
+          remapped.a.bits := DontCare
+          io.a.ready := false.B
+          io.a.bits := DontCare
 
-        io.d.valid       := false.B
-        io.d.bits        := DontCare
-        remapped.d.ready := false.B
-        remapped.d.bits  := DontCare
-      }
+          io.d.valid := false.B
+          io.d.bits := DontCare
+          remapped.d.ready := false.B
+          remapped.d.bits := DontCare
+        }
     }
   parameter.bceReachableIO
     .lazyZip(masterLinksIO)
     .lazyZip(masterLinksRemapped)
     .lazyZip(parameter.srcIdRemapTable)
-    .foreach { case (connects, io, remapped, range) =>
-      if (connects.exists(x => x)) {
-        io.b :<>= remapped.b
-        io.b.bits.source := trim(remapped.b.bits.source, range.size)
+    .foreach {
+      case (connects, io, remapped, range) =>
+        if (connects.exists(x => x)) {
+          io.b :<>= remapped.b
+          io.b.bits.source := trim(remapped.b.bits.source, range.size)
 
-        remapped.c :<>= io.c
-        remapped.c.bits.source := io.c.bits.source | range.start.U
+          remapped.c :<>= io.c
+          remapped.c.bits.source := io.c.bits.source | range.start.U
 
-        remapped.e :<>= io.e
-      } else {
-        io.b.valid       := false.B
-        io.b.bits        := DontCare
-        remapped.b.ready := false.B
-        remapped.b.bits  := DontCare
+          remapped.e :<>= io.e
+        } else {
+          io.b.valid := false.B
+          io.b.bits := DontCare
+          remapped.b.ready := false.B
+          remapped.b.bits := DontCare
 
-        remapped.c.valid := false.B
-        remapped.c.bits  := DontCare
-        io.c.ready       := false.B
-        io.c.bits        := DontCare
+          remapped.c.valid := false.B
+          remapped.c.bits := DontCare
+          io.c.ready := false.B
+          io.c.bits := DontCare
 
-        remapped.e.valid := false.B
-        remapped.e.bits  := DontCare
-        io.e.ready       := false.B
-        io.e.bits        := DontCare
-      }
+          remapped.e.valid := false.B
+          remapped.e.bits := DontCare
+          io.e.ready := false.B
+          io.e.bits := DontCare
+        }
     }
 
   parameter.adReachableOI
     .lazyZip(slaveLinksIO)
     .lazyZip(slaveLinksRemapped)
     .lazyZip(parameter.sinkIdRemapTable)
-    .foreach { case (connects, io, remapped, range) =>
-      if (connects.exists(x => x)) {
-        remapped.a :<>= io.a
+    .foreach {
+      case (connects, io, remapped, range) =>
+        if (connects.exists(x => x)) {
+          remapped.a :<>= io.a
 
-        io.d :<>= remapped.d
-        io.d.bits.sink := trim(remapped.d.bits.sink, range.size)
-      } else {
-        remapped.a.valid := false.B
-        remapped.a.bits  := DontCare
-        io.a.ready       := false.B
-        io.a.bits        := DontCare
+          io.d :<>= remapped.d
+          io.d.bits.sink := trim(remapped.d.bits.sink, range.size)
+        } else {
+          remapped.a.valid := false.B
+          remapped.a.bits := DontCare
+          io.a.ready := false.B
+          io.a.bits := DontCare
 
-        io.d.valid       := false.B
-        io.d.bits        := DontCare
-        remapped.d.ready := false.B
-        remapped.d.bits  := DontCare
-      }
+          io.d.valid := false.B
+          io.d.bits := DontCare
+          remapped.d.ready := false.B
+          remapped.d.bits := DontCare
+        }
     }
 
   parameter.bceReachableOI
     .lazyZip(slaveLinksIO)
     .lazyZip(slaveLinksRemapped)
     .lazyZip(parameter.sinkIdRemapTable)
-    .foreach { case (connects, io, remapped, range) =>
-      if (connects.exists(x => x)) {
-        io.b :<>= remapped.b
-        remapped.c :<>= io.c
-        remapped.e :<>= io.e
+    .foreach {
+      case (connects, io, remapped, range) =>
+        if (connects.exists(x => x)) {
+          io.b :<>= remapped.b
+          remapped.c :<>= io.c
+          remapped.e :<>= io.e
 
-        remapped.e.bits.sink := io.e.bits.sink | range.start.U
-      } else {
-        io.b.valid       := false.B
-        io.b.bits        := DontCare
-        remapped.b.ready := false.B
-        remapped.b.bits  := DontCare
+          remapped.e.bits.sink := io.e.bits.sink | range.start.U
+        } else {
+          io.b.valid := false.B
+          io.b.bits := DontCare
+          remapped.b.ready := false.B
+          remapped.b.bits := DontCare
 
-        remapped.c.valid := false.B
-        remapped.c.bits  := DontCare
-        io.c.ready       := false.B
-        io.c.bits        := DontCare
+          remapped.c.valid := false.B
+          remapped.c.bits := DontCare
+          io.c.ready := false.B
+          io.c.bits := DontCare
 
-        remapped.e.valid := false.B
-        remapped.e.bits  := DontCare
-        io.e.ready       := false.B
-        io.e.bits        := DontCare
-      }
+          remapped.e.valid := false.B
+          remapped.e.bits := DontCare
+          io.e.ready := false.B
+          io.e.bits := DontCare
+        }
     }
 
-  private def unique(x: Vector[Boolean])                  = x.count(x => x) <= 1
+  private def unique(x:       Vector[Boolean]) = x.count(x => x) <= 1
   private def filter[T](data: Seq[T], mask: Seq[Boolean]) = data.zip(mask).filter(_._2).map(_._1)
 
   // Based on input=>output connectivity, create per-input minimal address decode circuits
@@ -162,8 +167,8 @@ class TLCrossBar(val parameter: TLCrossBarParameter)
       if (unique(addressable)) {
         (addressable, (_: UInt) => addressable.map(_.B))
       } else {
-        val ports       = parameter.slaves.map(_.addressRange)
-        val maxBits     = log2Ceil(1 + ports.map(_.getWidth).max)
+        val ports = parameter.slaves.map(_.addressRange)
+        val maxBits = log2Ceil(1 + ports.map(_.getWidth).max)
         val maskedPorts = ports.zip(addressable).map {
           case (port, true) => port.intersect(BitPat.dontCare(maxBits))
           case (_, false)   => BitSet.empty
@@ -188,74 +193,79 @@ class TLCrossBar(val parameter: TLCrossBarParameter)
   val portsDIO = slaveLinksRemapped.zip(requestDOI).map { case (o, r) => TLCrossBar.fanout(o.d, r) }.transpose
   val portsEOI = masterLinksRemapped.zip(requestEIO).map { case (i, r) => TLCrossBar.fanout(i.e, r) }.transpose
 
-  slaveLinksRemapped.lazyZip(portsAOI).lazyZip(parameter.adReachableOI).foreach { case (portO, portI, reachable) =>
-    val arbiter = Module(
-      new TLArbiter(
-        TLArbiterParameter(
-          policy = parameter.arbitrationPolicy,
-          inputLinkParameters = filter(portI.map(_.bits.parameter), reachable),
-          outputLinkParameter = portO.a.bits.parameter
+  slaveLinksRemapped.lazyZip(portsAOI).lazyZip(parameter.adReachableOI).foreach {
+    case (portO, portI, reachable) =>
+      val arbiter = Module(
+        new TLArbiter(
+          TLArbiterParameter(
+            policy = parameter.arbitrationPolicy,
+            inputLinkParameters = filter(portI.map(_.bits.parameter), reachable),
+            outputLinkParameter = portO.a.bits.parameter
+          )
         )
       )
-    )
-    arbiter.sources.zip(filter(portI, reachable)).foreach { case (o, i) => o :<>= i }
-    portO.a :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelA]]
-    filter(portI, reachable.map(!_)).foreach { i => i.ready := false.B }
+      arbiter.sources.zip(filter(portI, reachable)).foreach { case (o, i) => o :<>= i }
+      portO.a :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelA]]
+      filter(portI, reachable.map(!_)).foreach { i => i.ready := false.B }
   }
-  masterLinksRemapped.lazyZip(portsBIO).lazyZip(parameter.bceReachableIO).foreach { case (portI, portO, reachable) =>
-    val arbiter = Module(
-      new TLArbiter(
-        TLArbiterParameter(
-          policy = parameter.arbitrationPolicy,
-          inputLinkParameters = filter(portO.map(_.bits.parameter), reachable),
-          outputLinkParameter = portI.b.bits.parameter
+  masterLinksRemapped.lazyZip(portsBIO).lazyZip(parameter.bceReachableIO).foreach {
+    case (portI, portO, reachable) =>
+      val arbiter = Module(
+        new TLArbiter(
+          TLArbiterParameter(
+            policy = parameter.arbitrationPolicy,
+            inputLinkParameters = filter(portO.map(_.bits.parameter), reachable),
+            outputLinkParameter = portI.b.bits.parameter
+          )
         )
       )
-    )
-    arbiter.sources.zip(filter(portO, reachable)).foreach { case (i, o) => i :<>= o }
-    portI.b :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelB]]
-    filter(portO, reachable.map(!_)).foreach { o => o.ready := false.B }
+      arbiter.sources.zip(filter(portO, reachable)).foreach { case (i, o) => i :<>= o }
+      portI.b :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelB]]
+      filter(portO, reachable.map(!_)).foreach { o => o.ready := false.B }
   }
-  slaveLinksRemapped.lazyZip(portsCOI).lazyZip(parameter.bceReachableOI).foreach { case (portO, portI, reachable) =>
-    val arbiter = Module(
-      new TLArbiter(
-        TLArbiterParameter(
-          policy = parameter.arbitrationPolicy,
-          inputLinkParameters = filter(portI.map(_.bits.parameter), reachable),
-          outputLinkParameter = portO.c.bits.parameter
+  slaveLinksRemapped.lazyZip(portsCOI).lazyZip(parameter.bceReachableOI).foreach {
+    case (portO, portI, reachable) =>
+      val arbiter = Module(
+        new TLArbiter(
+          TLArbiterParameter(
+            policy = parameter.arbitrationPolicy,
+            inputLinkParameters = filter(portI.map(_.bits.parameter), reachable),
+            outputLinkParameter = portO.c.bits.parameter
+          )
         )
       )
-    )
-    arbiter.sources.zip(filter(portI, reachable)).foreach { case (o, i) => o :<>= i }
-    portO.c :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelC]]
-    filter(portI, reachable.map(!_)).foreach { i => i.ready := false.B }
+      arbiter.sources.zip(filter(portI, reachable)).foreach { case (o, i) => o :<>= i }
+      portO.c :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelC]]
+      filter(portI, reachable.map(!_)).foreach { i => i.ready := false.B }
   }
-  masterLinksRemapped.lazyZip(portsDIO).lazyZip(parameter.adReachableIO).foreach { case (portI, portO, reachable) =>
-    val arbiter = Module(
-      new TLArbiter(
-        TLArbiterParameter(
-          policy = parameter.arbitrationPolicy,
-          inputLinkParameters = filter(portO.map(_.bits.parameter), reachable),
-          outputLinkParameter = portI.d.bits.parameter
+  masterLinksRemapped.lazyZip(portsDIO).lazyZip(parameter.adReachableIO).foreach {
+    case (portI, portO, reachable) =>
+      val arbiter = Module(
+        new TLArbiter(
+          TLArbiterParameter(
+            policy = parameter.arbitrationPolicy,
+            inputLinkParameters = filter(portO.map(_.bits.parameter), reachable),
+            outputLinkParameter = portI.d.bits.parameter
+          )
         )
       )
-    )
-    arbiter.sources.zip(filter(portO, reachable)).foreach { case (i, o) => i :<>= o }
-    portI.d :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelD]]
-    filter(portO, reachable.map(!_)).foreach { o => o.ready := false.B }
+      arbiter.sources.zip(filter(portO, reachable)).foreach { case (i, o) => i :<>= o }
+      portI.d :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelD]]
+      filter(portO, reachable.map(!_)).foreach { o => o.ready := false.B }
   }
-  slaveLinksRemapped.lazyZip(portsEOI).lazyZip(parameter.bceReachableOI).foreach { case (portO, portI, reachable) =>
-    val arbiter = Module(
-      new TLArbiter(
-        TLArbiterParameter(
-          policy = parameter.arbitrationPolicy,
-          inputLinkParameters = filter(portI.map(_.bits.parameter), reachable),
-          outputLinkParameter = portO.e.bits.parameter
+  slaveLinksRemapped.lazyZip(portsEOI).lazyZip(parameter.bceReachableOI).foreach {
+    case (portO, portI, reachable) =>
+      val arbiter = Module(
+        new TLArbiter(
+          TLArbiterParameter(
+            policy = parameter.arbitrationPolicy,
+            inputLinkParameters = filter(portI.map(_.bits.parameter), reachable),
+            outputLinkParameter = portO.e.bits.parameter
+          )
         )
       )
-    )
-    arbiter.sources.zip(filter(portI, reachable)).foreach { case (o, i) => o :<>= i }
-    portO.e :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelE]]
-    filter(portI, reachable.map(!_)).foreach { i => i.ready := false.B }
+      arbiter.sources.zip(filter(portI, reachable)).foreach { case (o, i) => o :<>= i }
+      portO.e :<>= arbiter.sink.asInstanceOf[DecoupledIO[TLChannelE]]
+      filter(portI, reachable.map(!_)).foreach { i => i.ready := false.B }
   }
 }
diff --git a/tilelink/src/xbar/TLCrossBarParameters.scala b/tilelink/src/xbar/TLCrossBarParameters.scala
index 6e350fd..8dbc960 100644
--- a/tilelink/src/xbar/TLCrossBarParameters.scala
+++ b/tilelink/src/xbar/TLCrossBarParameters.scala
@@ -24,7 +24,7 @@ case class TLCrossBarSlaveLinkParameter(
   bceVisibility: chisel3.util.experimental.BitSet,
   sinkIdRange:   TLIdRange,
   addressRange:  chisel3.util.experimental.BitSet)
-object TLCrossBarSlaveLinkParameter  {
+object TLCrossBarSlaveLinkParameter {
   import utils.Serializers._
   implicit val rw: RW[TLCrossBarSlaveLinkParameter] = macroRW
 }
@@ -35,26 +35,31 @@ case class TLCrossBarParameter(
   slaves:            Seq[TLCrossBarSlaveLinkParameter])
     extends chisel3.experimental.SerializableModuleParameter {
 
-  slaves.map(_.addressRange).combinations(2).foreach { case Seq(a, b) =>
-    require(!a.overlap(b), s"Address ranges of different slaves cannot overlap: $a, $b.")
+  slaves.map(_.addressRange).combinations(2).foreach {
+    case Seq(a, b) =>
+      require(!a.overlap(b), s"Address ranges of different slaves cannot overlap: $a, $b.")
   }
 
-  private[tilelink] def adReachableIO  = masters.map { case TLCrossBarMasterLinkParameter(_, visibility, _, _) =>
-    slaves.map { case TLCrossBarSlaveLinkParameter(_, severability, _, _, _) =>
-      visibility.overlap(severability)
-    }.toVector
+  private[tilelink] def adReachableIO = masters.map {
+    case TLCrossBarMasterLinkParameter(_, visibility, _, _) =>
+      slaves.map {
+        case TLCrossBarSlaveLinkParameter(_, severability, _, _, _) =>
+          visibility.overlap(severability)
+      }.toVector
   }.toVector
-  private[tilelink] def bceReachableIO = masters.map { case TLCrossBarMasterLinkParameter(_, _, visibility, _) =>
-    slaves.map { case TLCrossBarSlaveLinkParameter(_, _, severability, _, _) =>
-      visibility.overlap(severability)
-    }.toVector
+  private[tilelink] def bceReachableIO = masters.map {
+    case TLCrossBarMasterLinkParameter(_, _, visibility, _) =>
+      slaves.map {
+        case TLCrossBarSlaveLinkParameter(_, _, severability, _, _) =>
+          visibility.overlap(severability)
+      }.toVector
   }.toVector
 
-  private[tilelink] def adReachableOI       = adReachableIO.transpose
-  private[tilelink] def bceReachableOI      = bceReachableIO.transpose
-  private[tilelink] def srcIdRemapTable     =
+  private[tilelink] def adReachableOI = adReachableIO.transpose
+  private[tilelink] def bceReachableOI = bceReachableIO.transpose
+  private[tilelink] def srcIdRemapTable =
     TLCrossBarParameter.assignIdRange(masters.map(_.srcIdRange.end))
-  private[tilelink] def sinkIdRemapTable    =
+  private[tilelink] def sinkIdRemapTable =
     TLCrossBarParameter.assignIdRange(slaves.map(_.sinkIdRange.end))
   private[tilelink] def commonLinkParameter = TLLinkParameter.union(
     masters.map(_.linkParameter) ++ slaves.map(_.linkParameter): _*
@@ -64,15 +69,16 @@ case class TLCrossBarParameter(
 object TLCrossBarParameter {
   private def assignIdRange(sizes: Seq[Int]) = {
     val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
-    val tuples    = pow2Sizes.zipWithIndex.sortBy(
+    val tuples = pow2Sizes.zipWithIndex.sortBy(
       _._1
     ) // record old index, then sort by increasing size
     val starts =
       tuples
         .scanRight(0)(_._1 + _)
         .tail // suffix-sum of the sizes = the start positions
-    val ranges = tuples.zip(starts).map { case ((sz, i), st) =>
-      (if (sz == 0) TLIdRange(0, 0) else TLIdRange(st, st + sz), i)
+    val ranges = tuples.zip(starts).map {
+      case ((sz, i), st) =>
+        (if (sz == 0) TLIdRange(0, 0) else TLIdRange(st, st + sz), i)
     }
     ranges.sortBy(_._2).map(_._1) // Restore original order
   }
diff --git a/tilelink/src/xbar/TLIdRange.scala b/tilelink/src/xbar/TLIdRange.scala
index 4fd919b..24baef1 100644
--- a/tilelink/src/xbar/TLIdRange.scala
+++ b/tilelink/src/xbar/TLIdRange.scala
@@ -15,7 +15,7 @@ case class TLIdRange(start: Int, end: Int) extends Ordered[TLIdRange] {
   require(start <= end, "Id ranges cannot be negative.")
 
   def compare(x: TLIdRange) = {
-    val primary   = (this.start - x.start).sign
+    val primary = (this.start - x.start).sign
     val secondary = (x.end - this.end).sign
     if (primary != 0) primary else secondary
   }
@@ -23,7 +23,7 @@ case class TLIdRange(start: Int, end: Int) extends Ordered[TLIdRange] {
   def overlaps(x: TLIdRange) = start < x.end && x.start < end
   def contains(x: TLIdRange) = start <= x.start && x.end <= end
 
-  def contains(x: Int)  = start <= x && x < end
+  def contains(x: Int) = start <= x && x < end
   def contains(x: UInt) =
     if (size == 0) {
       false.B
@@ -31,20 +31,20 @@ case class TLIdRange(start: Int, end: Int) extends Ordered[TLIdRange] {
       x === start.U
     } else {
       // find index of largest different bit
-      val largestDeltaBit   = log2Floor(start ^ (end - 1))
+      val largestDeltaBit = log2Floor(start ^ (end - 1))
       val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
-      val uncommonMask      = (1 << smallestCommonBit) - 1
-      val uncommonBits      = (x | 0.U(largestDeltaBit.W))(largestDeltaBit, 0)
+      val uncommonMask = (1 << smallestCommonBit) - 1
+      val uncommonBits = (x | 0.U(largestDeltaBit.W))(largestDeltaBit, 0)
       // the prefix must match exactly (note: may shift ALL bits away)
       (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
-        // firrtl constant prop range analysis can eliminate these two:
-        (start & uncommonMask).U <= uncommonBits &&
-        uncommonBits <= ((end - 1) & uncommonMask).U
+      // firrtl constant prop range analysis can eliminate these two:
+      (start & uncommonMask).U <= uncommonBits &&
+      uncommonBits <= ((end - 1) & uncommonMask).U
     }
 
   def shift(x: Int) = TLIdRange(start + x, end + x)
-  def size          = end - start
-  def isEmpty       = end == start
+  def size = end - start
+  def isEmpty = end == start
 
   def range = start until end
 }