what about raspberry pi 5 and the rp1 chip?

[fpgasdr]

hi,

i guess you are aware of the anouncement of the new raspberry pi 5 with the new rp1 chip for interface with peripherals.

RPF has release some documentation but don't know about the new chip and the smi interface

https://www.raspberrypi.com/news/rp1-the-silicon-controlling-raspberry-pi-5-i-o-designed-here-at-raspberry-pi/

any thoughts?.

regards.

[kevinmehall]

It was mentioned here: https://www.raspberrypi.com/news/introducing-raspberry-pi-5/#comment-1594074

Does RP1 emulate SMI(Secondary Memory Interface) that HATs like CaribouLite use for high-speed data transfer?

That should be possible in the future with a suitable PIO driver. There is a PIO implementation and we’re hoping to develop a nice Linux driver and some userland tools for it. But we’re not there yet!

[fpgasdr]

they also say this:

As Eben said in the post, at least at launch RP1 is going to be minimally documented. We’re looking at perhaps exposing some PIO capabilities eventually, but there isn’t going to be anything written down at launch, or for some time afterward. That said the PIO in RP1 is not quite the PIO you’re used to in RP2040, and doesn’t work in quite the same way...