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iio: adc: ad9361: Avoid clobbering MGC set gain when switching gain t…
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…ables

This fixes unintentional resets to MAX gain when moving RX LO between
gain table coverage boundaries.
When switching gain tables only enforce set gain below max gain.
Otherwise avoid clobbering the current gain index.

Signed-off-by: Michael Hennerich <[email protected]>
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mhennerich committed Jan 30, 2018
1 parent 03c32c8 commit f457f60
Showing 1 changed file with 14 additions and 5 deletions.
19 changes: 14 additions & 5 deletions drivers/iio/adc/ad9361.c
Original file line number Diff line number Diff line change
Expand Up @@ -1173,7 +1173,7 @@ static int ad9361_load_gt(struct ad9361_rf_phy *phy, u64 freq, u32 dest)
{
struct spi_device *spi = phy->spi;
u8 (*tab)[3];
u32 band, index_max, i, lna, lpf_tia_mask;
u32 band, index_max, i, lna, lpf_tia_mask, set_gain;

dev_dbg(&phy->spi->dev, "%s: frequency %llu", __func__, freq);

Expand All @@ -1192,10 +1192,19 @@ static int ad9361_load_gt(struct ad9361_rf_phy *phy, u64 freq, u32 dest)
ad9361_spi_writef(spi, REG_AGC_CONFIG_2,
AGC_USE_FULL_GAIN_TABLE, !phy->pdata->split_gt);

ad9361_spi_write(spi, REG_MAX_LMT_FULL_GAIN, index_max - 1); // Max Full/LMT Gain Table Index
ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
RX_FULL_TBL_IDX_MASK, index_max - 1); // Rx1 Full/LMT Gain Index
ad9361_spi_write(spi, REG_RX2_MANUAL_LMT_FULL_GAIN, index_max - 1); // Rx2 Full/LMT Gain Index
ad9361_spi_write(spi, REG_MAX_LMT_FULL_GAIN, index_max - 1); /* Max Full/LMT Gain Table Index */

set_gain = ad9361_spi_readf(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
RX_FULL_TBL_IDX_MASK);
if (set_gain > (index_max - 1))
ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
RX_FULL_TBL_IDX_MASK, index_max - 1); /* Rx1 Full/LMT Gain Index */

set_gain = ad9361_spi_readf(spi, REG_RX2_MANUAL_LMT_FULL_GAIN,
RX_FULL_TBL_IDX_MASK);
if (set_gain > (index_max - 1))
ad9361_spi_write(spi, REG_RX2_MANUAL_LMT_FULL_GAIN,
index_max - 1); /* Rx2 Full/LMT Gain Index */

lna = phy->pdata->elna_ctrl.elna_in_gaintable_all_index_en ?
EXT_LNA_CTRL : 0;
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