iio: adc: ad9361: Disable CP offset current, clear 0x23D[D4] 0x27D[D4]

Implement recommended setting: Disabling CP offset current improves PLL locking over temperature. Signed-off-by: Michael Hennerich <[email protected]>
analogdevicesinc · Mar 23, 2018 · 9513f72 · 9513f72
1 parent 1d6dc8f
commit 9513f72
Show file tree

Hide file tree

Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/drivers/iio/adc/ad9361.c b/drivers/iio/adc/ad9361.c
@@ -2421,7 +2421,7 @@ static int ad9361_txrx_synth_cp_calib(struct ad9361_rf_phy *phy,
 	ad9361_spi_write(phy->spi, REG_RX_VCO_LDO + offs, 0x0B);
 	ad9361_spi_write(phy->spi, REG_RX_VCO_PD_OVERRIDES + offs, 0x02);
 	ad9361_spi_write(phy->spi, REG_RX_CP_CURRENT + offs, 0x80);
-	ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, 0x00);
+	ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, CP_OFFSET_OFF);
 
 	/* see Table 70 Example Calibration Times for RF VCO Cal */
 	if (phy->pdata->fdd) {
@@ -2450,7 +2450,8 @@ static int ad9361_txrx_synth_cp_calib(struct ad9361_rf_phy *phy,
 			TO_ALERT);
 	ad9361_spi_write(phy->spi, REG_ENSM_MODE, FDD_MODE);
 
-	ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, CP_CAL_ENABLE);
+	ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs,
+			 CP_OFFSET_OFF | CP_CAL_ENABLE);
 
 	return ad9361_check_cal_done(phy, REG_RX_CAL_STATUS + offs,
 				    CP_CAL_VALID, 1);

diff --git a/drivers/iio/adc/ad9361.h b/drivers/iio/adc/ad9361.h
@@ -2227,6 +2227,7 @@
  *	REG_RX_CP_CONFIG
  */
 #define HALF_VCO_CAL_CLK		     (1 << 7) /* Half Vco Cal Clk */
+#define CP_OFFSET_OFF			     (1 << 4) /* CP Offset Off */
 #define F_CPCAL				     (1 << 3) /* F Cpcal */
 #define CP_CAL_ENABLE			     (1 << 2) /* Cp Cal Enable */