iio: ad9361: Reduce number of ALERT<->FDD transitions during interfac…

…e tuning

During digital interface tuning the relative delay between the clock and
data is sweep from the minimum to the maximum value and for each value it
is checked whether the interface works reliably or not.

Lets define the relative delay as clock delay - data delay.

Sweeping is done in two phases:
  1) Clock delay is set to zero and data delay is incremented from 0 to 15.
     This produces a relative delay from 0 to -15.
  2) Data delay is set to zero and clock delay is incremented from 0 to 15.
     This produces a relative delay of 0 to 15.

Changing the clock delay requires a transition to the ALERT state and back
to FDD state. This means during the second phase a lot of transitions are
required.

The same set of relative delay values can be produced by changing the
second phase so that clock delay is set to 15 and then data delay is
decremented from 15 to 0. This reduces the ALERT state transitions that are
necessary to 1.

Signed-off-by: Lars-Peter Clausen <[email protected]>

drivers/iio/adc/ad9361_conv.c

@@ -503,8 +503,12 @@ int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
 
 		for (i = 0; i < 2; i++) {
 			for (j = 0; j < 16; j++) {
-				ad9361_set_intf_delay(phy, t == 1, i ? j : 0,
-						      i ? 0 : j, i || j == 0);
+				/*
+				 * i == 0: clock delay = 0, data delay from 0 to 15
+				 * i == 1: clock delay = 15, data delay from 15 to 0
+				 */
+				ad9361_set_intf_delay(phy, t == 1, i ? 15 : 0,
+						      i ? 15 - j : j, j == 0);
 				for (chan = 0; chan < num_chan; chan++)
 					axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
 						ADI_PN_ERR | ADI_PN_OOS);