ad9361: ad9361_dig_interface_timing_analysis(): Properly setup and cl…

…eanup

Make sure that all timing analysis relevant configuration parameters have
the right value. E.g. currently bist timing analysis does not work in TDD
mode or when loopback mode is enabled.

Also make sure to restore all configuration parameters to their previous
value after the timing analysis has completed.

Signed-off-by: Lars-Peter Clausen <[email protected]>

drivers/iio/adc/ad9361_conv.c

@@ -77,19 +77,28 @@ ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
 						   char *buf, unsigned buflen)
 {
 	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
+	unsigned int loopback, bist, ensm_state;
 	int i, j, len = 0;
 	u8 field[16][16];
-	u8 ensm_state;
 	u8 rx;
 
 	if (!conv)
 		return -ENODEV;
 
 	dev_dbg(&phy->spi->dev, "%s:\n", __func__);
 
+	loopback = phy->bist_loopback_mode;
+	bist = phy->bist_config;
 	ensm_state = ad9361_ensm_get_state(phy);
 	rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
 
+	/* Mute TX, we don't want to transmit the PRBS */
+	ad9361_tx_mute(phy, 1);
+
+	if (!phy->pdata->fdd)
+		ad9361_set_ensm_mode(phy, true, false);
+
+	ad9361_bist_loopback(phy, 0);
 	ad9361_bist_prbs(phy, BIST_INJ_RX);
 
 	for (i = 0; i < 16; i++) {
@@ -101,9 +110,14 @@ ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
 
 	ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
 	ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx);
+	ad9361_bist_loopback(phy, loopback);
+	ad9361_spi_write(phy->spi, REG_BIST_CONFIG, bist);
+
+	if (!phy->pdata->fdd)
+		ad9361_set_ensm_mode(phy, phy->pdata->fdd, phy->pdata->ensm_pin_ctrl);
 	ad9361_ensm_restore_state(phy, ensm_state);
 
-	ad9361_bist_prbs(phy, BIST_DISABLE);
+	ad9361_tx_mute(phy, 0);
 
 	len += snprintf(buf + len, buflen, "CLK: %lu Hz 'o' = PASS\n",
 		       clk_get_rate(phy->clks[RX_SAMPL_CLK]));