axi_ad9144: Infer clock signal

analogdevicesinc · Apr 11, 2018 · d8916e6 · d8916e6
1 parent 7ae0167
commit d8916e6
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl
@@ -31,5 +31,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]