From d80175d89549c464b8c5248e568604eba3340496 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 18 May 2018 11:21:44 +0200 Subject: [PATCH] axi_dmac: Remove second destination side register slice The second destination side register slice was put in place to provide additional slack on some of the datapath control signals. It looks as if this is no longer required for the latest version of the DMA controller. All timing paths have sufficient margin. So remove this extra slice register which just takes up resources and adds pipeline latency. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_arb.v | 31 +++---------------------------- 1 file changed, 3 insertions(+), 28 deletions(-) diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 8e26dc18ef..4ade642bd3 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -756,15 +756,11 @@ axi_dmac_burst_memory #( .dest_data_response_id(dest_data_response_id) ); -wire _dest_valid; -wire _dest_ready; -wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data; -wire _dest_last; - axi_register_slice #( .DATA_WIDTH(DMA_DATA_WIDTH_DEST + 1), - .FORWARD_REGISTERED(AXI_SLICE_DEST) -) i_dest_slice2 ( + .FORWARD_REGISTERED(AXI_SLICE_DEST), + .BACKWARD_REGISTERED(AXI_SLICE_DEST) +) i_dest_slice ( .clk(dest_clk), .resetn(dest_resetn), .s_axi_valid(dest_fifo_valid), @@ -773,27 +769,6 @@ axi_register_slice #( dest_fifo_last, dest_fifo_data }), - .m_axi_valid(_dest_valid), - .m_axi_ready(_dest_ready), - .m_axi_data({ - _dest_last, - _dest_data - }) -); - -axi_register_slice #( - .DATA_WIDTH(DMA_DATA_WIDTH_DEST + 1), - .FORWARD_REGISTERED(AXI_SLICE_DEST), - .BACKWARD_REGISTERED(AXI_SLICE_DEST) -) i_dest_slice ( - .clk(dest_clk), - .resetn(dest_resetn), - .s_axi_valid(_dest_valid), - .s_axi_ready(_dest_ready), - .s_axi_data({ - _dest_last, - _dest_data - }), .m_axi_valid(dest_valid), .m_axi_ready(dest_ready), .m_axi_data({