axi_dmac: removed harmful SDC constraint

The set_false_path constraint targeted to the *ram* cells of the dmac
matched several intra clock domain paths where the timing analysis got
ignored resulting in intermitent data integrity issues.

library/axi_dmac/axi_dmac_constr.sdc

@@ -4,7 +4,6 @@ set_false_path -to    [get_registers *axi_dmac*cdc_sync_stage1*]
 set_false_path -from  [get_registers *axi_dmac*cdc_sync_fifo_ram*]
 set_false_path -from  [get_registers *axi_dmac*eot_mem*]
 set_false_path -to    [get_registers *axi_dmac*reset_shift*]
-set_false_path -to    [get_registers *axi_dmac*ram*]
 set_false_path -from  [get_registers *axi_dmac*cdc_sync_stage2*]      -to [get_registers *axi_dmac*up_rdata*]
 set_false_path -from  [get_registers *axi_dmac*id*]                   -to [get_registers *axi_dmac*up_rdata*]
 set_false_path -from  [get_registers *axi_dmac*address*]              -to [get_registers *axi_dmac*up_rdata*]