ad_dds: Add selectable phase width option.

analogdevicesinc · Jul 18, 2018 · a7f5746 · a7f5746
1 parent 7b55399
commit a7f5746
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Showing 3 changed files with 37 additions and 33 deletions.
diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v
@@ -54,16 +54,16 @@ module ad_dds #(
 
   // interface
 
-  input                                 clk,
-  input                                 rst,
-  input                                 dac_dds_format,
-  input                                 dac_data_sync,
-  input       [                  15:0]  tone_1_scale,
-  input       [                  15:0]  tone_2_scale,
-  input       [                  15:0]  tone_1_init_offset,
-  input       [                  15:0]  tone_2_init_offset,
-  input       [          PHASE_DW-1:0]  tone_1_freq_word,
-  input       [          PHASE_DW-1:0]  tone_2_freq_word,
+  input                               clk,
+  input                               rst,
+  input                               dac_dds_format,
+  input                               dac_data_sync,
+  input       [                15:0]  tone_1_scale,
+  input       [                15:0]  tone_2_scale,
+  input       [                15:0]  tone_1_init_offset,
+  input       [                15:0]  tone_2_init_offset,
+  input       [        PHASE_DW-1:0]  tone_1_freq_word,
+  input       [        PHASE_DW-1:0]  tone_2_freq_word,
   output  reg [DDS_DW*CLK_RATIO-1:0]  dac_dds_data
   );
 
@@ -122,6 +122,7 @@ module ad_dds #(
         // phase to amplitude convertor
          ad_dds_2 #(
            .DDS_DW (DDS_DW),
+           .PHASE_DW (PHASE_DW),
            .DDS_TYPE (DDS_TYPE),
            .CORDIC_DW (CORDIC_DW),
            .CORDIC_PHASE_DW (CORDIC_PHASE_DW))

diff --git a/library/common/ad_dds_1.v b/library/common/ad_dds_1.v
@@ -45,7 +45,7 @@ module ad_dds_1 #(
 
   // interface
 
-  input                        clk,
+  input                       clk,
   input       [DDS_P_DW-1:0]  angle,
   input       [        15:0]  scale,
   output  reg [DDS_D_DW-1:0]  dds_data);
@@ -65,23 +65,13 @@ module ad_dds_1 #(
   generate
     if (DDS_TYPE == DDS_CORDIC_TYPE) begin
 
-      // the cordic module input angle width must be equal with it's width
-      // at this point the phase is only generated on 16 bits
-      wire    [DDS_P_DW-1:0] angle_s;
-
-      if (DDS_P_DW >= 16) begin
-        assign angle_s = {angle,{DDS_P_DW-15{1'b0}}};
-      end else begin
-        assign angle_s = {angle[15:16-DDS_P_DW],1'b0};
-      end
-
       ad_dds_sine_cordic #(
         .CORDIC_DW(DDS_D_DW),
         .PHASE_DW(DDS_P_DW),
         .DELAY_DW(1))
       i_dds_sine (
         .clk (clk),
-        .angle (angle_s),
+        .angle (angle),
         .sine (sine_s),
         .cosine (),
         .ddata_in (1'b0),

diff --git a/library/common/ad_dds_2.v b/library/common/ad_dds_2.v
@@ -41,6 +41,8 @@ module ad_dds_2 #(
   parameter   DISABLE = 0,
   // Range = 8-24
   parameter   DDS_DW = 16,
+  // Range = 8-24
+  parameter   PHASE_DW = 16,
   // Set 1 for CORDIC or 2 for Polynomial
   parameter   DDS_TYPE = 1,
   // Range = 8-24
@@ -50,13 +52,13 @@ module ad_dds_2 #(
 
   // interface
 
-  input                 clk,
-  input                 dds_format,
-  input   [      15:0]  dds_phase_0,
-  input   [      15:0]  dds_scale_0,
-  input   [      15:0]  dds_phase_1,
-  input   [      15:0]  dds_scale_1,
-  output  [DDS_DW-1:0]  dds_data);
+  input                   clk,
+  input                   dds_format,
+  input   [PHASE_DW-1:0]  dds_phase_0,
+  input   [        15:0]  dds_scale_0,
+  input   [PHASE_DW-1:0]  dds_phase_1,
+  input   [        15:0]  dds_scale_1,
+  output  [  DDS_DW-1:0]  dds_data);
 
  // Local parameters
 
@@ -80,8 +82,10 @@ module ad_dds_2 #(
 
   // internal signals
 
-  wire    [15:0]  dds_data_0_s;
-  wire    [15:0]  dds_data_1_s;
+  wire    [DDS_D_DW-1:0]  dds_data_0_s;
+  wire    [DDS_D_DW-1:0]  dds_data_1_s;
+  wire    [DDS_P_DW-1:0]  dds_phase_0_s;
+  wire    [DDS_P_DW-1:0]  dds_phase_1_s;
 
   // disable DDS
   generate
@@ -120,6 +124,15 @@ module ad_dds_2 #(
          dds_scale_1_d <= dds_scale_1;
        end
 
+       // phase
+        if (DDS_P_DW >= PHASE_DW) begin
+          assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-(PHASE_DW-1){1'b0}}};
+          assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-(PHASE_DW-1){1'b0}}};
+        end else begin
+          assign dds_phase_0_s = {dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW],1'b0};
+          assign dds_phase_1_s = {dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW],1'b0};
+        end
+
        // dds-1
 
        ad_dds_1 #(
@@ -128,7 +141,7 @@ module ad_dds_2 #(
          .DDS_P_DW(CORDIC_PHASE_DW))
        i_dds_1_0 (
          .clk (clk),
-         .angle (dds_phase_0),
+         .angle (dds_phase_0_s),
          .scale (dds_scale_0_d),
          .dds_data (dds_data_0_s));
 
@@ -140,7 +153,7 @@ module ad_dds_2 #(
          .DDS_P_DW(DDS_P_DW))
        i_dds_1_1 (
          .clk (clk),
-         .angle (dds_phase_1),
+         .angle (dds_phase_1_s),
          .scale (dds_scale_1_d),
          .dds_data (dds_data_1_s));
     end