axi_dmac: Allow to disable FIFO interfaces immediately

For the AXI streaming interfaces we need to make sure that the handshaking
rules for the external interface are met. Hence we can't just disable the
DMA and have to wait for any pending beats to complete.

For the FIFO interfaces on the other hand no such requirements exist. All
handshaking is for the internal pipeline which will be reset as a whole so
it is OK to violate the handshaking without causing any undefined behavior.

Signed-off-by: Lars-Peter Clausen <[email protected]>

library/axi_dmac/dest_fifo_inf.v

@@ -72,12 +72,11 @@ module dmac_dest_fifo_inf #(
   output [1:0] response_resp
 );
 
-wire data_enabled;
-
 wire [DATA_WIDTH-1:0]  dout_s;
 wire data_ready;
 wire data_valid;
 
+assign enabled = enable;
 assign data_ready = en & (data_valid | ~enable);
 
 dmac_data_mover # (
@@ -90,7 +89,7 @@ dmac_data_mover # (
   .resetn(resetn),
 
   .enable(enable),
-  .enabled(data_enabled),
+  .enabled(),
   .xfer_req(xfer_req),
 
   .request_id(request_id),
@@ -127,8 +126,8 @@ dmac_response_generator # (
   .clk(clk),
   .resetn(resetn),
 
-  .enable(data_enabled),
-  .enabled(enabled),
+  .enable(enable),
+  .enabled(),
 
   .request_id(data_id),
   .response_id(response_id),

library/axi_dmac/src_fifo_inf.v

@@ -71,6 +71,8 @@ reg needs_sync = 1'b0;
 wire has_sync = ~needs_sync | sync;
 wire sync_valid = en & ready & has_sync;
 
+assign enabled = enable;
+
 always @(posedge clk)
 begin
   if (ready && en && sync) begin
@@ -99,7 +101,7 @@ dmac_data_mover # (
   .resetn(resetn),
 
   .enable(enable),
-  .enabled(enabled),
+  .enabled(),
 
   .xfer_req(xfer_req),