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library/axi_ad9361/intel: Update I/O format
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@IuliaCMoldovan
IuliaCMoldovan committed Apr 8, 2022
1 parent 7a5ecb5 commit 63089a7
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Showing 2 changed files with 31 additions and 76 deletions.
52 changes: 15 additions & 37 deletions library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,41 +39,22 @@ module axi_ad9361_alt_lvds_rx (

// physical interface (receive)

rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,

// data interface

clk,
rx_frame,
rx_data_0,
rx_data_1,
rx_data_2,
rx_data_3,
rx_locked);

// physical interface (receive)

input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;

// data interface

output clk;
output [ 3:0] rx_frame;
output [ 5:0] rx_data_0;
output [ 5:0] rx_data_1;
output [ 5:0] rx_data_2;
output [ 5:0] rx_data_3;
output rx_locked;
output clk,
output [ 3:0] rx_frame,
output [ 5:0] rx_data_0,
output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3,
output rx_locked);

// internal signals

Expand Down Expand Up @@ -157,8 +138,8 @@ module axi_ad9361_alt_lvds_rx (
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off"))
i_altlvds_rx (
.clk_src_is_pll ("off")
) i_altlvds_rx (
.rx_inclock (rx_clk_in_p),
.rx_in ({rx_frame_in_p, rx_data_in_p}),
.rx_outclock (clk),
Expand Down Expand Up @@ -195,6 +176,3 @@ module axi_ad9361_alt_lvds_rx (
.rx_syncclock (1'b0));

endmodule

// ***************************************************************************
// ***************************************************************************
55 changes: 16 additions & 39 deletions library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,43 +39,23 @@ module axi_ad9361_alt_lvds_tx (

// physical interface (transmit)

tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,

// data interface

tx_clk,
clk,
tx_frame,
tx_data_0,
tx_data_1,
tx_data_2,
tx_data_3,
tx_locked);

// physical interface (transmit)

output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;

// data interface

input tx_clk;
input clk;
input [ 3:0] tx_frame;
input [ 5:0] tx_data_0;
input [ 5:0] tx_data_1;
input [ 5:0] tx_data_2;
input [ 5:0] tx_data_3;
output tx_locked;
input tx_clk,
input clk,
input [ 3:0] tx_frame,
input [ 5:0] tx_data_0,
input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3,
output tx_locked);

// internal registers

Expand Down Expand Up @@ -163,8 +143,8 @@ module axi_ad9361_alt_lvds_tx (
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off"))
i_altlvds_tx (
.clk_src_is_pll ("off")
) i_altlvds_tx (
.tx_inclock (tx_clk),
.tx_coreclock (core_clk),
.tx_in (tx_data_p),
Expand All @@ -179,6 +159,3 @@ module axi_ad9361_alt_lvds_tx (
.tx_syncclock (1'b0));

endmodule

// ***************************************************************************
// ***************************************************************************

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