Deploying to main from @ amaranth-lang/amaranth@3857822 🚀

docs/amaranth/v0.5.3/.gitignore

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+_build/
+_linkcheck/

docs/amaranth/v0.5.3/_code/led_blinker.py

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+from amaranth import *
+
+
+class LEDBlinker(Elaboratable):
+    def elaborate(self, platform):
+        m = Module()
+
+        led = platform.request("led")
+
+        half_freq = int(platform.default_clk_frequency // 2)
+        timer = Signal(range(half_freq + 1))
+
+        with m.If(timer == half_freq):
+            m.d.sync += led.o.eq(~led.o)
+            m.d.sync += timer.eq(0)
+        with m.Else():
+            m.d.sync += timer.eq(timer + 1)
+
+        return m
+# --- BUILD ---
+from amaranth_boards.icestick import ICEStickPlatform
+
+
+ICEStickPlatform().build(LEDBlinker(), do_program=True)

docs/amaranth/v0.5.3/_code/up_counter.py

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+from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
+
+
+class UpCounter(wiring.Component):
+    """
+    A 16-bit up counter with a fixed limit.
+
+    Parameters
+    ----------
+    limit : int
+        The value at which the counter overflows.
+
+    Attributes
+    ----------
+    en : Signal, in
+        The counter is incremented if ``en`` is asserted, and retains
+        its value otherwise.
+    ovf : Signal, out
+        ``ovf`` is asserted when the counter reaches its limit.
+    """
+
+    en: In(1)
+    ovf: Out(1)
+
+    def __init__(self, limit):
+        self.limit = limit
+        self.count = Signal(16)
+
+        super().__init__()
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.comb += self.ovf.eq(self.count == self.limit)
+
+        with m.If(self.en):
+            with m.If(self.ovf):
+                m.d.sync += self.count.eq(0)
+            with m.Else():
+                m.d.sync += self.count.eq(self.count + 1)
+
+        return m
+# --- TEST ---
+from amaranth.sim import Simulator
+
+
+dut = UpCounter(25)
+async def bench(ctx):
+    # Disabled counter should not overflow.
+    ctx.set(dut.en, 0)
+    for _ in range(30):
+        await ctx.tick()
+        assert not ctx.get(dut.ovf)
+
+    # Once enabled, the counter should overflow in 25 cycles.
+    ctx.set(dut.en, 1)
+    for _ in range(24):
+        await ctx.tick()
+        assert not ctx.get(dut.ovf)
+    await ctx.tick()
+    assert ctx.get(dut.ovf)
+
+    # The overflow should clear in one cycle.
+    await ctx.tick()
+    assert not ctx.get(dut.ovf)
+
+
+sim = Simulator(dut)
+sim.add_clock(1e-6) # 1 MHz
+sim.add_testbench(bench)
+with sim.write_vcd("up_counter.vcd"):
+    sim.run()
+# --- CONVERT ---
+from amaranth.back import verilog
+
+
+top = UpCounter(25)
+with open("up_counter.v", "w") as f:
+    f.write(verilog.convert(top))

docs/amaranth/v0.5.3/_code/up_counter.v

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+(* generator = "Amaranth" *)
+module top(ovf, clk, rst, en);
+  reg \$auto$verilog_backend.cc:2255:dump_module$1  = 0;
+  (* src = "up_counter.py:36" *)
+  wire \$1 ;
+  (* src = "up_counter.py:42" *)
+  wire [16:0] \$3 ;
+  (* src = "up_counter.py:42" *)
+  wire [16:0] \$4 ;
+  (* src = "<site-packages>/amaranth/hdl/ir.py:509" *)
+  input clk;
+  wire clk;
+  (* src = "up_counter.py:29" *)
+  reg [15:0] count = 16'h0000;
+  (* src = "up_counter.py:29" *)
+  reg [15:0] \count$next ;
+  (* src = "<site-packages>/amaranth/lib/wiring.py:1647" *)
+  input en;
+  wire en;
+  (* src = "<site-packages>/amaranth/lib/wiring.py:1647" *)
+  output ovf;
+  wire ovf;
+  (* src = "<site-packages>/amaranth/hdl/ir.py:509" *)
+  input rst;
+  wire rst;
+  assign \$1  = count == (* src = "up_counter.py:36" *) 5'h19;
+  assign \$4  = count + (* src = "up_counter.py:42" *) 1'h1;
+  always @(posedge clk)
+    count <= \count$next ;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2255:dump_module$1 ) begin end
+    \count$next  = count;
+    (* src = "up_counter.py:38" *)
+    if (en) begin
+      (* full_case = 32'd1 *)
+      (* src = "up_counter.py:39" *)
+      if (ovf) begin
+        \count$next  = 16'h0000;
+      end else begin
+        \count$next  = \$4 [15:0];
+      end
+    end
+    (* src = "<site-packages>/amaranth/hdl/xfrm.py:534" *)
+    if (rst) begin
+      \count$next  = 16'h0000;
+    end
+  end
+  assign \$3  = \$4 ;
+  assign ovf = \$1 ;
+endmodule

docs/amaranth/v0.5.3/_downloads/9916e1f0618daa91d3860f1bdac16820/up_counter.py

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+from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
+
+
+class UpCounter(wiring.Component):
+    """
+    A 16-bit up counter with a fixed limit.
+
+    Parameters
+    ----------
+    limit : int
+        The value at which the counter overflows.
+
+    Attributes
+    ----------
+    en : Signal, in
+        The counter is incremented if ``en`` is asserted, and retains
+        its value otherwise.
+    ovf : Signal, out
+        ``ovf`` is asserted when the counter reaches its limit.
+    """
+
+    en: In(1)
+    ovf: Out(1)
+
+    def __init__(self, limit):
+        self.limit = limit
+        self.count = Signal(16)
+
+        super().__init__()
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.comb += self.ovf.eq(self.count == self.limit)
+
+        with m.If(self.en):
+            with m.If(self.ovf):
+                m.d.sync += self.count.eq(0)
+            with m.Else():
+                m.d.sync += self.count.eq(self.count + 1)
+
+        return m
+# --- TEST ---
+from amaranth.sim import Simulator
+
+
+dut = UpCounter(25)
+async def bench(ctx):
+    # Disabled counter should not overflow.
+    ctx.set(dut.en, 0)
+    for _ in range(30):
+        await ctx.tick()
+        assert not ctx.get(dut.ovf)
+
+    # Once enabled, the counter should overflow in 25 cycles.
+    ctx.set(dut.en, 1)
+    for _ in range(24):
+        await ctx.tick()
+        assert not ctx.get(dut.ovf)
+    await ctx.tick()
+    assert ctx.get(dut.ovf)
+
+    # The overflow should clear in one cycle.
+    await ctx.tick()
+    assert not ctx.get(dut.ovf)
+
+
+sim = Simulator(dut)
+sim.add_clock(1e-6) # 1 MHz
+sim.add_testbench(bench)
+with sim.write_vcd("up_counter.vcd"):
+    sim.run()
+# --- CONVERT ---
+from amaranth.back import verilog
+
+
+top = UpCounter(25)
+with open("up_counter.v", "w") as f:
+    f.write(verilog.convert(top))