A simple project of a circuit for adding 3 numbers in VHDL.
Implement a circuit in VHDL capable of adding 3 n-bit numbers (parametric circuit) coded in 2's complements format. The inputs and output need to be synchronized and masked using registers.
- Descrive the circuit using VHDL;
- Create a test bench for the logical simulation;
- Synthesize the circuit;
- Run a test bench for the post-synthesis simulation;
- Circuit implementation;
- Run a test bench for the post-implementation simulation;
- Create a documentation for the circuit;
- Version 1 - Ripple carry adder;
- Version 2 - Carry save adder;