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x86.csv
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Instruction,Opcode,Valid 64-bit,Valid 32-bit,Valid 16-bit,Feature Flags,Operand 1,Operand 2,Operand 3,Operand 4,Tuple Type,Description
"AAA","37","Invalid","Valid","Valid","","NA","NA","NA","NA","","ASCII adjust AL after addition."
"AAD","D5 0A","Invalid","Valid","Valid","","NA","NA","NA","NA","","ASCII adjust AX before division."
"AAD imm8","D5 ib","Invalid","Valid","Valid","","NA","NA","NA","NA","","Adjust AX before division to number base imm8."
"AAM","D4 0A","Invalid","Valid","Valid","","NA","NA","NA","NA","","ASCII adjust AX after multiply."
"AAM imm8","D4 ib","Invalid","Valid","Valid","","NA","NA","NA","NA","","Adjust AX after multiply to number base imm8."
"AAS","3F","Invalid","Valid","Valid","","NA","NA","NA","NA","","ASCII adjust AL after subtraction."
"ADC AL, imm8","14 ib","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add with carry imm8 to AL."
"ADC AX, imm16","15 iw","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add with carry imm16 to AX."
"ADC EAX, imm32","15 id","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add with carry imm32 to EAX."
"ADC RAX, imm32","REX.W + 15 id","Valid","Invalid","Invalid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add with carry imm32 sign extended to 64- bits to RAX."
"ADC r/m8, imm8","80 /2 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with carry imm8 to r/m8."
"ADC r/m8 , imm8","REX + 80 /2 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with carry imm8 to r/m8."
"ADC r/m16, imm16","81 /2 iw","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with carry imm16 to r/m16."
"ADC r/m32, imm32","81 /2 id","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with CF imm32 to r/m32."
"ADC r/m64, imm32","REX.W + 81 /2 id","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with CF imm32 sign extended to 64-bits to r/m64."
"ADC r/m16, imm8","83 /2 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with CF sign-extended imm8 to r/m16."
"ADC r/m32, imm8","83 /2 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with CF sign-extended imm8 into r/m32."
"ADC r/m64, imm8","REX.W + 83 /2 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add with CF sign-extended imm8 into r/m64."
"ADC r/m8, r8","10 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add with carry byte register to r/m8."
"ADC r/m8 , r8","REX + 10 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add with carry byte register to r/m64."
"ADC r/m16, r16","11 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add with carry r16 to r/m16."
"ADC r/m32, r32","11 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add with CF r32 to r/m32."
"ADC r/m64, r64","REX.W + 11 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add with CF r64 to r/m64."
"ADC r8, r/m8","12 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add with carry r/m8 to byte register."
"ADC r8 , r/m8","REX + 12 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add with carry r/m64 to byte register."
"ADC r16, r/m16","13 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add with carry r/m16 to r16."
"ADC r32, r/m32","13 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add with CF r/m32 to r32."
"ADC r64, r/m64","REX.W + 13 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add with CF r/m64 to r64."
"ADCX r32, r/m32","66 0F 38 F6 /r","Valid","Valid","Invalid","ADX","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Unsigned addition of r32 with CF, r/m32 to r32, writes CF."
"ADCX r64, r/m64","66 REX.w 0F 38 F6 /r","Valid","Invalid","Invalid","ADX","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Unsigned addition of r64 with CF, r/m64 to r64, writes CF."
"ADD AL, imm8","04 ib","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add imm8 to AL."
"ADD AX, imm16","05 iw","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add imm16 to AX."
"ADD EAX, imm32","05 id","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add imm32 to EAX."
"ADD RAX, imm32","REX.W + 05 id","Valid","Invalid","Invalid","","AL/AX/EAX/RAX","imm8","NA","NA","","Add imm32 sign-extended to 64-bits to RAX."
"ADD r/m8, imm8","80 /0 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add imm8 to r/m8."
"ADD r/m8 , imm8","REX + 80 /0 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add sign-extended imm8 to r/m8."
"ADD r/m16, imm16","81 /0 iw","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add imm16 to r/m16."
"ADD r/m32, imm32","81 /0 id","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add imm32 to r/m32."
"ADD r/m64, imm32","REX.W + 81 /0 id","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add imm32 sign-extended to 64-bits to r/m64."
"ADD r/m16, imm8","83 /0 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add sign-extended imm8 to r/m16."
"ADD r/m32, imm8","83 /0 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add sign-extended imm8 to r/m32."
"ADD r/m64, imm8","REX.W + 83 /0 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Add sign-extended imm8 to r/m64."
"ADD r/m8, r8","00 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add r8 to r/m8."
"ADD r/m8 , r8","REX + 00 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add r8 to r/m8."
"ADD r/m16, r16","01 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add r16 to r/m16."
"ADD r/m32, r32","01 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add r32 to r/m32."
"ADD r/m64, r64","REX.W + 01 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Add r64 to r/m64."
"ADD r8, r/m8","02 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add r/m8 to r8."
"ADD r8 , r/m8","REX + 02 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add r/m8 to r8."
"ADD r16, r/m16","03 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add r/m16 to r16."
"ADD r32, r/m32","03 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add r/m32 to r32."
"ADD r64, r/m64","REX.W + 03 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add r/m64 to r64."
"ADDPD xmm1, xmm2/m128","66 0F 58 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Add packed double-precision floating-point values from xmm2/mem to xmm1 and store result in xmm1."
"VADDPD xmm1,xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG 58 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Add packed double-precision floating-point values from xmm3/mem to xmm2 and store result in xmm1."
"VADDPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG 58 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Add packed double-precision floating-point values from ymm3/mem to ymm2 and store result in ymm1."
"VADDPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst","EVEX.NDS.128.66.0F.W1 58 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Add packed double-precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1 with writemask k1."
"VADDPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst","EVEX.NDS.256.66.0F.W1 58 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Add packed double-precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1 with writemask k1."
"VADDPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}","EVEX.NDS.512.66.0F.W1 58 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Add packed double-precision floating-point values from zmm3/m512/m64bcst to zmm2 and store result in zmm1 with writemask k1."
"ADDPS xmm1, xmm2/m128","NP 0F 58 /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Add packed single-precision floating-point values from xmm2/m128 to xmm1 and store result in xmm1."
"VADDPS xmm1,xmm2, xmm3/m128","VEX.NDS.128.0F.WIG 58 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Add packed single-precision floating-point values from xmm3/m128 to xmm2 and store result in xmm1."
"VADDPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.0F.WIG 58 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Add packed single-precision floating-point values from ymm3/m256 to ymm2 and store result in ymm1."
"VADDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst","EVEX.NDS.128.0F.W0 58 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Add packed single-precision floating-point values from xmm3/m128/m32bcst to xmm2 and store result in xmm1 with writemask k1."
"VADDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst","EVEX.NDS.256.0F.W0 58 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Add packed single-precision floating-point values from ymm3/m256/m32bcst to ymm2 and store result in ymm1 with writemask k1."
"VADDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {er}","EVEX.NDS.512.0F.W0 58 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Add packed single-precision floating-point values from zmm3/m512/m32bcst to zmm2 and store result in zmm1 with writemask k1."
"ADDSD xmm1, xmm2/m64","F2 0F 58 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Add the low double-precision floating-point value from xmm2/mem to xmm1 and store the result in xmm1."
"VADDSD xmm1, xmm2, xmm3/m64","VEX.NDS.LIG.F2.0F.WIG 58 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Add the low double-precision floating-point value from xmm3/mem to xmm2 and store the result in xmm1."
"VADDSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}","EVEX.NDS.LIG.F2.0F.W1 58 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Add the low double-precision floating-point value from xmm3/m64 to xmm2 and store the result in xmm1 with writemask k1."
"ADDSS xmm1, xmm2/m32","F3 0F 58 /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Add the low single-precision floating-point value from xmm2/mem to xmm1 and store the result in xmm1."
"VADDSS xmm1,xmm2, xmm3/m32","VEX.NDS.LIG.F3.0F.WIG 58 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Add the low single-precision floating-point value from xmm3/mem to xmm2 and store the result in xmm1."
"VADDSS xmm1{k1}{z}, xmm2, xmm3/m32{er}","EVEX.NDS.LIG.F3.0F.W0 58 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Add the low single-precision floating-point value from xmm3/m32 to xmm2 and store the result in xmm1with writemask k1."
"ADDSUBPD xmm1, xmm2/m128","66 0F D0 /r","Valid","Valid","Invalid","SSE3","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add/subtract double-precision floating-point values from xmm2/m128 to xmm1."
"VADDSUBPD xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG D0 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Add/subtract packed double-precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1."
"VADDSUBPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG D0 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Add / subtract packed double-precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1."
"ADDSUBPS xmm1, xmm2/m128","F2 0F D0 /r","Valid","Valid","Invalid","SSE3","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Add/subtract single-precision floating-point values from xmm2/m128 to xmm1."
"VADDSUBPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.F2.0F.WIG D0 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Add/subtract single-precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1."
"VADDSUBPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.F2.0F.WIG D0 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Add / subtract single-precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1."
"ADOX r32, r/m32","F3 0F 38 F6 /r","Valid","Valid","Invalid","ADX","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Unsigned addition of r32 with OF, r/m32 to r32, writes OF."
"ADOX r64, r/m64","F3 REX.w 0F 38 F6 /r","Valid","Invalid","Invalid","ADX","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Unsigned addition of r64 with OF, r/m64 to r64, writes OF."
"AESDEC xmm1, xmm2/m128","66 0F 38 DE /r","Valid","Valid","Invalid","AES","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Perform one round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128."
"VAESDEC xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F38.WIG DE /r","Valid","Valid","Invalid","AES AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Perform one round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from xmm3/m128; store the result in xmm1."
"AESDECLAST xmm1, xmm2/m128","66 0F 38 DF /r","Valid","Valid","Invalid","AES","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Perform the last round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128."
"VAESDECLAST xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F38.WIG DF /r","Valid","Valid","Invalid","AES AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Perform the last round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from xmm3/m128; store the result in xmm1."
"AESENC xmm1, xmm2/m128","66 0F 38 DC /r","Valid","Valid","Invalid","AES","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Perform one round of an AES encryption flow, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128."
"VAESENC xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F38.WIG DC /r","Valid","Valid","Invalid","AES AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Perform one round of an AES encryption flow, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from the xmm3/m128; store the result in xmm1."
"AESENCLAST xmm1, xmm2/m128","66 0F 38 DD /r","Valid","Valid","Invalid","AES","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Perform the last round of an AES encryption flow, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128."
"VAESENCLAST xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F38.WIG DD /r","Valid","Valid","Invalid","AES AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Perform the last round of an AES encryption flow, operating on a 128-bit data (state) from xmm2 with a 128 bit round key from xmm3/m128; store the result in xmm1."
"AESIMC xmm1, xmm2/m128","66 0F 38 DB /r","Valid","Valid","Invalid","AES","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Perform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1."
"VAESIMC xmm1, xmm2/m128","VEX.128.66.0F38.WIG DB /r","Valid","Valid","Invalid","AES AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Perform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1."
"AESKEYGENASSIST xmm1, xmm2/m128, imm8","66 0F 3A DF /r ib","Valid","Valid","Invalid","AES","ModRM:reg (w)","ModRM:r/m (r)","imm8","NA","","Assist in AES round key generation using an 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1."
"VAESKEYGENASSIST xmm1, xmm2/m128, imm8","VEX.128.66.0F3A.WIG DF /r ib","Valid","Valid","Invalid","AES AVX","ModRM:reg (w)","ModRM:r/m (r)","imm8","NA","","Assist in AES round key generation using 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1."
"AND AL, imm8","24 ib","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","AL AND imm8."
"AND AX, imm16","25 iw","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","AX AND imm16."
"AND EAX, imm32","25 id","Valid","Valid","Valid","","AL/AX/EAX/RAX","imm8","NA","NA","","EAX AND imm32."
"AND RAX, imm32","REX.W + 25 id","Valid","Invalid","Invalid","","AL/AX/EAX/RAX","imm8","NA","NA","","RAX AND imm32 sign-extended to 64-bits."
"AND r/m8, imm8","80 /4 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m8 AND imm8."
"AND r/m8 , imm8","REX + 80 /4 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m8 AND imm8."
"AND r/m16, imm16","81 /4 iw","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m16 AND imm16."
"AND r/m32, imm32","81 /4 id","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m32 AND imm32."
"AND r/m64, imm32","REX.W + 81 /4 id","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m64 AND imm32 sign extended to 64-bits."
"AND r/m16, imm8","83 /4 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m16 AND imm8 (sign-extended)."
"AND r/m32, imm8","83 /4 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m32 AND imm8 (sign-extended)."
"AND r/m64, imm8","REX.W + 83 /4 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","r/m64 AND imm8 (sign-extended)."
"AND r/m8, r8","20 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","r/m8 AND r8."
"AND r/m8 , r8","REX + 20 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","r/m64 AND r8 (sign-extended)."
"AND r/m16, r16","21 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","r/m16 AND r16."
"AND r/m32, r32","21 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","r/m32 AND r32."
"AND r/m64, r64","REX.W + 21 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","r/m64 AND r32."
"AND r8, r/m8","22 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","r8 AND r/m8."
"AND r8 , r/m8","REX + 22 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","r/m64 AND r8 (sign-extended)."
"AND r16, r/m16","23 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","r16 AND r/m16."
"AND r32, r/m32","23 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","r32 AND r/m32."
"AND r64, r/m64","REX.W + 23 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","r64 AND r/m64."
"ANDN r32a, r32b, r/m32","VEX.NDS.LZ.0F38.W0 F2 /r","Valid","Valid","Invalid","BMI1","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Bitwise AND of inverted r32b with r/m32, store result in r32a."
"ANDN r64a, r64b, r/m64","VEX.NDS.LZ.0F38.W1 F2 /r","Valid","Invalid","Invalid","BMI1","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Bitwise AND of inverted r64b with r/m64, store result in r64a."
"ANDNPD xmm1, xmm2/m128","66 0F 55 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the bitwise logical AND NOT of packed double-precision floating-point values in xmm1 and xmm2/mem."
"VANDNPD xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F 55 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND NOT of packed double-precision floating-point values in xmm2 and xmm3/mem."
"VANDNPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F 55/r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND NOT of packed double-precision floating-point values in ymm2 and ymm3/mem."
"VANDNPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst","EVEX.NDS.128.66.0F.W1 55 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND NOT of packed double-precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1."
"VANDNPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst","EVEX.NDS.256.66.0F.W1 55 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND NOT of packed double-precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1."
"VANDNPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst","EVEX.NDS.512.66.0F.W1 55 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND NOT of packed double-precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1."
"ANDNPS xmm1, xmm2/m128","NP 0F 55 /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the bitwise logical AND NOT of packed single-precision floating-point values in xmm1 and xmm2/mem."
"VANDNPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.0F 55 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND NOT of packed single-precision floating-point values in xmm2 and xmm3/mem."
"VANDNPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.0F 55 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND NOT of packed single-precision floating-point values in ymm2 and ymm3/mem."
"VANDNPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst","EVEX.NDS.128.0F.W0 55 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1."
"VANDNPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst","EVEX.NDS.256.0F.W0 55 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1."
"VANDNPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst","EVEX.NDS.512.0F.W0 55 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1."
"ANDPD xmm1, xmm2/m128","66 0F 54 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the bitwise logical AND of packed double-precision floating-point values in xmm1 and xmm2/mem."
"VANDPD xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F 54 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND of packed double-precision floating-point values in xmm2 and xmm3/mem."
"VANDPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F 54 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND of packed double-precision floating-point values in ymm2 and ymm3/mem."
"VANDPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst","EVEX.NDS.128.66.0F.W1 54 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed double-precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1."
"VANDPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst","EVEX.NDS.256.66.0F.W1 54 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed double-precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1."
"VANDPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst","EVEX.NDS.512.66.0F.W1 54 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed double-precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1."
"ANDPS xmm1, xmm2/m128","NP 0F 54 /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the bitwise logical AND of packed single-precision floating-point values in xmm1 and xmm2/mem."
"VANDPS xmm1,xmm2, xmm3/m128","VEX.NDS.128.0F 54 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/mem."
"VANDPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.0F 54 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/mem."
"VANDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst","EVEX.NDS.128.0F.W0 54 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1."
"VANDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst","EVEX.NDS.256.0F.W0 54 /r","Valid","Valid","Invalid","AVX512VL AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1."
"VANDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst","EVEX.NDS.512.0F.W0 54 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the bitwise logical AND of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1."
"ARPL r/m16, r16","63 /r","Invalid","Invalid","Invalid","","ModRM:r/m (w)","ModRM:reg (r)","NA","NA","","Valid Adjust RPL of r/m16 to not less than RPL of r16."
"BEXTR r32a, r/m32, r32b","VEX.NDS.LZ.0F38.W0 F7 /r","Valid","Valid","Invalid","BMI1","ModRM:reg (w)","ModRM:r/m (r)","VEX.vvvv (r)","NA","","Contiguous bitwise extract from r/m32 using r32b as control; store result in r32a."
"BEXTR r64a, r/m64, r64b","VEX.NDS.LZ.0F38.W1 F7 /r","Valid","Invalid","Invalid","BMI1","ModRM:reg (w)","ModRM:r/m (r)","VEX.vvvv (r)","NA","","Contiguous bitwise extract from r/m64 using r64b as control; store result in r64a"
"BLENDPD xmm1, xmm2/m128, imm8","66 0F 3A 0D /r ib","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","imm8","NA","","Select packed DP-FP values from xmm1 and xmm2/m128 from mask specified in imm8 and store the values into xmm1."
"VBLENDPD xmm1, xmm2, xmm3/m128, imm8","VEX.NDS.128.66.0F3A.WIG 0D /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8[3:0]","","Select packed double-precision floating-point Values from xmm2 and xmm3/m128 from mask in imm8 and store the values in xmm1."
"VBLENDPD ymm1, ymm2, ymm3/m256, imm8","VEX.NDS.256.66.0F3A.WIG 0D /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8[3:0]","","Select packed double-precision floating-point Values from ymm2 and ymm3/m256 from mask in imm8 and store the values in ymm1."
"BLENDPS xmm1, xmm2/m128, imm8","66 0F 3A 0C /r ib","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","imm8","NA","","Select packed single precision floating-point values from xmm1 and xmm2/m128 from mask specified in imm8 and store the values into xmm1."
"VBLENDPS xmm1, xmm2, xmm3/m128, imm8","VEX.NDS.128.66.0F3A.WIG 0C /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8","","Select packed single-precision floating-point values from xmm2 and xmm3/m128 from mask in imm8 and store the values in xmm1."
"VBLENDPS ymm1, ymm2, ymm3/m256, imm8","VEX.NDS.256.66.0F3A.WIG 0C /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8","","Select packed single-precision floating-point values from ymm2 and ymm3/m256 from mask in imm8 and store the values in ymm1."
"BLENDVPD xmm1, xmm2/m128 , <XMM0>","66 0F 38 15 /r","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","implicit XMM0","NA","","Select packed DP FP values from xmm1 and xmm2 from mask specified in XMM0 and store the values in xmm1."
"VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4","VEX.NDS.128.66.0F3A.W0 4B /r /is4","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8[7:4]","","Conditionally copy double-precision floating-point values from xmm2 or xmm3/m128 to xmm1, based on mask bits in the mask operand, xmm4."
"VBLENDVPD ymm1, ymm2, ymm3/m256, ymm4","VEX.NDS.256.66.0F3A.W0 4B /r /is4","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8[7:4]","","Conditionally copy double-precision floating-point values from ymm2 or ymm3/m256 to ymm1, based on mask bits in the mask operand, ymm4."
"BLENDVPS xmm1, xmm2/m128, <XMM0>","66 0F 38 14 /r","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","implicit XMM0","NA","","Select packed single precision floating-point values from xmm1 and xmm2/m128 from mask specified in XMM0 and store the values into xmm1."
"VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4","VEX.NDS.128.66.0F3A.W0 4A /r /is4","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8[7:4]","","Conditionally copy single-precision floating-point values from xmm2 or xmm3/m128 to xmm1, based on mask bits in the specified mask operand, xmm4."
"VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4","VEX.NDS.256.66.0F3A.W0 4A /r /is4","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8[7:4]","","Conditionally copy single-precision floating-point values from ymm2 or ymm3/m256 to ymm1, based on mask bits in the specified mask register, ymm4."
"BLSI r32, r/m32","VEX.NDD.LZ.0F38.W0 F3 /3","Valid","Valid","Invalid","BMI1","VEX.vvvv (w)","ModRM:r/m (r)","NA","NA","","Extract lowest set bit from r/m32 and set that bit in r32."
"BLSI r64, r/m64","VEX.NDD.LZ.0F38.W1 F3 /3","Valid","Invalid","Invalid","BMI1","VEX.vvvv (w)","ModRM:r/m (r)","NA","NA","","Extract lowest set bit from r/m64, and set that bit in r64."
"BLSMSK r32, r/m32","VEX.NDD.LZ.0F38.W0 F3 /2","Valid","Valid","Invalid","BMI1","VEX.vvvv (w)","ModRM:r/m (r)","NA","NA","","Set all lower bits in r32 to “1†starting from bit 0 to lowest set bit in r/m32."
"BLSMSK r64, r/m64","VEX.NDD.LZ.0F38.W1 F3 /2","Valid","Invalid","Invalid","BMI1","VEX.vvvv (w)","ModRM:r/m (r)","NA","NA","","Set all lower bits in r64 to “1†starting from bit 0 to lowest set bit in r/m64."
"BLSR r32, r/m32","VEX.NDD.LZ.0F38.W0 F3 /1","Valid","Valid","Invalid","BMI1","VEX.vvvv (w)","ModRM:r/m (r)","NA","NA","","Reset lowest set bit of r/m32, keep all other bits of r/m32 and write result to r32."
"BLSR r64, r/m64","VEX.NDD.LZ.0F38.W1 F3 /1","Valid","Invalid","Invalid","BMI1","VEX.vvvv (w)","ModRM:r/m (r)","NA","NA","","Reset lowest set bit of r/m64, keep all other bits of r/m64 and write result to r64."
"BNDCL bnd, r/m32","F3 0F 1A /r","Invalid","Valid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Generate a #BR if the address in r/m32 is lower than the lower bound in bnd.LB."
"BNDCL bnd, r/m64","F3 0F 1A /r","Valid","Invalid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Generate a #BR if the address in r/m64 is lower than the lower bound in bnd.LB."
"BNDCU bnd, r/m32","F2 0F 1A /r","Invalid","Valid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Generate a #BR if the address in r/m32 is higher than the upper bound in bnd.UB (bnb.UB in 1's complement form)."
"BNDCU bnd, r/m64","F2 0F 1A /r","Valid","Invalid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Generate a #BR if the address in r/m64 is higher than the upper bound in bnd.UB (bnb.UB in 1's complement form)."
"BNDCN bnd, r/m32","F2 0F 1B /r","Invalid","Valid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Generate a #BR if the address in r/m32 is higher than the upper bound in bnd.UB (bnb.UB not in 1's complement form)."
"BNDCN bnd, r/m64","F2 0F 1B /r","Valid","Invalid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Generate a #BR if the address in r/m64 is higher than the upper bound in bnd.UB (bnb.UB not in 1's complement form)."
"BNDLDX bnd, mib","NP 0F 1A /r","Valid","Valid","Invalid","MPX","ModRM:reg (w)","SIB.base (r): Address of pointer SIB.index (r)","NA","","","Load the bounds stored in a bound table entry (BTE) into bnd with address translation using the base of mib and conditional on the index of mib matching the pointer value in the BTE."
"BNDMK bnd, m32","F3 0F 1B /r","Invalid","Valid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Make lower and upper bounds from m32 and store them in bnd."
"BNDMK bnd, m64","F3 0F 1B /r","Valid","Invalid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Make lower and upper bounds from m64 and store them in bnd."
"BNDMOV bnd1, bnd2/m64","66 0F 1A /r","Invalid","Valid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Move lower and upper bound from bnd2/m64 to bound register bnd1."
"BNDMOV bnd1, bnd2/m128","66 0F 1A /r","Valid","Invalid","Invalid","MPX","ModRM:reg (w)","ModRM:r/m (r)","NA","","","Move lower and upper bound from bnd2/m128 to bound register bnd1."
"BNDMOV bnd1/m64, bnd2","66 0F 1B /r","Invalid","Valid","Invalid","MPX","ModRM:r/m (w)","ModRM:reg (r)","NA","","","Move lower and upper bound from bnd2 to bnd1/m64."
"BNDMOV bnd1/m128, bnd2","66 0F 1B /r","Valid","Invalid","Invalid","MPX","ModRM:r/m (w)","ModRM:reg (r)","NA","","","Move lower and upper bound from bnd2 to bound register bnd1/m128."
"BNDSTX mib, bnd","NP 0F 1B /r","Valid","Valid","Invalid","MPX","SIB.base (r): Address of pointer SIB.index (r)","ModRM:reg (r)","NA","","","Store the bounds in bnd and the pointer value in the index regis-ter of mib to a bound table entry (BTE) with address translation using the base of mib."
"BOUND r16, m16&16","62 /r","Invalid","Valid","Valid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Check if r16 (array index) is within bounds specified by m16&16."
"BOUND r32, m32&32","62 /r","Invalid","Valid","Valid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Check if r32 (array index) is within bounds specified by m32&32."
"BSF r16, r/m16","0F BC /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Bit scan forward on r/m16."
"BSF r32, r/m32","0F BC /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Bit scan forward on r/m32."
"BSF r64, r/m64","REX.W + 0F BC /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Bit scan forward on r/m64."
"BSR r16, r/m16","0F BD /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Bit scan reverse on r/m16."
"BSR r32, r/m32","0F BD /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Bit scan reverse on r/m32."
"BSR r64, r/m64","REX.W + 0F BD /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Bit scan reverse on r/m64."
"BSWAP r32","0F C8+rd","Valid","Valid","Valid","","opcode +rd (r, w)","NA","NA","NA","","Reverses the byte order of a 32-bit register."
"BSWAP r64","REX.W + 0F C8+rd","Valid","Invalid","Invalid","","opcode +rd (r, w)","NA","NA","NA","","Reverses the byte order of a 64-bit register."
"BT r/m16, r16","0F A3 /r","Valid","Valid","Valid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag."
"BT r/m32, r32","0F A3 /r","Valid","Valid","Valid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag."
"BT r/m64, r64","REX.W + 0F A3 /r","Valid","Invalid","Invalid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag."
"BT r/m16, imm8","0F BA /4 ib","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Store selected bit in CF flag."
"BT r/m32, imm8","0F BA /4 ib","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Store selected bit in CF flag."
"BT r/m64, imm8","REX.W + 0F BA /4 ib","Valid","Invalid","Invalid","","ModRM:r/m (r)","imm8","NA","NA","","Store selected bit in CF flag."
"BTC r/m16, r16","0F BB /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and complement."
"BTC r/m32, r32","0F BB /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and complement."
"BTC r/m64, r64","REX.W + 0F BB /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and complement."
"BTC r/m16, imm8","0F BA /7 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and complement."
"BTC r/m32, imm8","0F BA /7 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and complement."
"BTC r/m64, imm8","REX.W + 0F BA /7 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and complement."
"BTR r/m16, r16","0F B3 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and clear."
"BTR r/m32, r32","0F B3 /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and clear."
"BTR r/m64, r64","REX.W + 0F B3 /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and clear."
"BTR r/m16, imm8","0F BA /6 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and clear."
"BTR r/m32, imm8","0F BA /6 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and clear."
"BTR r/m64, imm8","REX.W + 0F BA /6 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and clear."
"BTS r/m16, r16","0F AB /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and set."
"BTS r/m32, r32","0F AB /r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and set."
"BTS r/m64, r64","REX.W + 0F AB /r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Store selected bit in CF flag and set."
"BTS r/m16, imm8","0F BA /5 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and set."
"BTS r/m32, imm8","0F BA /5 ib","Valid","Valid","Valid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and set."
"BTS r/m64, imm8","REX.W + 0F BA /5 ib","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","imm8","NA","NA","","Store selected bit in CF flag and set."
"BZHI r32a, r/m32, r32b","VEX.NDS.LZ.0F38.W0 F5 /r","Valid","Valid","Invalid","BMI2","ModRM:reg (w)","ModRM:r/m (r)","VEX.vvvv (r)","NA","","Zero bits in r/m32 starting with the position in r32b, write result to r32a."
"BZHI r64a, r/m64, r64b","VEX.NDS.LZ.0F38.W1 F5 /r","Valid","Invalid","Invalid","BMI2","ModRM:reg (w)","ModRM:r/m (r)","VEX.vvvv (r)","NA","","Zero bits in r/m64 starting with the position in r64b, write result to r64a."
"CALL rel16","E8 cw","Invalid","Valid","Valid","","","","","","","Call near, relative, displacement relative to next instruction."
"CALL rel32","E8 cd","Valid","Valid","Invalid","","","","","","","Call near, relative, displacement relative to next instruction. 32-bit displacement sign extended to 64-bits in 64-bit mode."
"CALL r/m16","FF /2","Invalid","Valid","Valid","","","","","","","Call near, absolute indirect, address given in r/m16."
"CALL r/m32","FF /2","Invalid","Valid","Invalid","","","","","","","Call near, absolute indirect, address given in r/m32."
"CALL r/m64","FF /2","Valid","Invalid","Invalid","","","","","","","Call near, absolute indirect, address given in r/m64."
"CALL ptr16:16","9A cd","Invalid","Valid","Valid","","","","","","","Call far, absolute, address given in operand."
"CALL ptr16:32","9A cp","Invalid","Valid","Invalid","","","","","","","Call far, absolute, address given in operand."
"CALL m16:16","FF /3","Valid","Valid","Valid","","","","","","","Call far, absolute indirect address given in m16:16. In 32-bit mode: if selector points to a gate, then RIP = 32-bit zero extended displacement taken from gate; else RIP = zero extended 16-bit offset from far pointer referenced in the instruction."
"CALL m16:32","FF /3","Valid","Valid","Invalid","","","","","","","In 64-bit mode: If selector points to a gate, then RIP = 64-bit displacement taken from gate; else RIP = zero extended 32-bit offset from far pointer referenced in the instruction."
"CALL m16:64","REX.W + FF /3","Valid","Invalid","Invalid","","","","","","","In 64-bit mode: If selector points to a gate, then RIP = 64-bit displacement taken from gate; else RIP = 64-bit offset from far pointer referenced in the instruction."
"CBW","98","Valid","Valid","Valid","","NA","NA","NA","NA","","AX ↠sign-extend of AL."
"CWDE","98","Valid","Valid","Valid","","NA","NA","NA","NA","","EAX ↠sign-extend of AX."
"CDQE","REX.W + 98","Valid","Invalid","Invalid","","NA","NA","NA","NA","","RAX ↠sign-extend of EAX."
"CLAC","NP 0F 01 CA","Valid","Valid","Invalid","SMAP","NA","NA","NA","NA","","Clear the AC flag in the EFLAGS register."
"CLC","F8","Valid","Valid","Valid","","NA","NA","NA","NA","","Clear CF flag."
"CLD","FC","Valid","Valid","Valid","","NA","NA","NA","NA","","Clear DF flag."
"CLFLUSH m8","NP 0F AE /7","Valid","Valid","Valid","","ModRM:r/m (w)","NA","NA","NA","","Flushes cache line containing m8."
"CLFLUSHOPT m8","66 0F AE /7","Valid","Valid","Valid","","ModRM:r/m (w)","NA","NA","NA","","Flushes cache line containing m8."
"CLI","FA","Valid","Valid","Valid","","NA","NA","NA","NA","","Clear interrupt flag; interrupts disabled when interrupt flag cleared."
"CLTS","0F 06","Valid","Valid","Valid","","NA","NA","NA","NA","","Clears TS flag in CR0."
"CLWB m8","66 0F AE /6","Valid","Valid","Invalid","CLWB","","","","","","Writes back modified cache line containing m8, and may retain the line in cache hierarchy in non-modified state."
"CMC","F5","Valid","Valid","Valid","","NA","NA","NA","NA","","Complement CF flag."
"CMOVA r16, r/m16","0F 47 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if above (CF=0 and ZF=0)."
"CMOVA r32, r/m32","0F 47 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if above (CF=0 and ZF=0)."
"CMOVA r64, r/m64","REX.W + 0F 47 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if above (CF=0 and ZF=0)."
"CMOVAE r16, r/m16","0F 43 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if above or equal (CF=0)."
"CMOVAE r32, r/m32","0F 43 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if above or equal (CF=0)."
"CMOVAE r64, r/m64","REX.W + 0F 43 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if above or equal (CF=0)."
"CMOVB r16, r/m16","0F 42 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if below (CF=1)."
"CMOVB r32, r/m32","0F 42 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if below (CF=1)."
"CMOVB r64, r/m64","REX.W + 0F 42 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if below (CF=1)."
"CMOVBE r16, r/m16","0F 46 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if below or equal (CF=1 or ZF=1)."
"CMOVBE r32, r/m32","0F 46 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if below or equal (CF=1 or ZF=1)."
"CMOVBE r64, r/m64","REX.W + 0F 46 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if below or equal (CF=1 or ZF=1)."
"CMOVC r16, r/m16","0F 42 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if carry (CF=1)."
"CMOVC r32, r/m32","0F 42 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if carry (CF=1)."
"CMOVC r64, r/m64","REX.W + 0F 42 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if carry (CF=1)."
"CMOVE r16, r/m16","0F 44 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if equal (ZF=1)."
"CMOVE r32, r/m32","0F 44 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if equal (ZF=1)."
"CMOVE r64, r/m64","REX.W + 0F 44 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if equal (ZF=1)."
"CMOVG r16, r/m16","0F 4F /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if greater (ZF=0 and SF=OF)."
"CMOVG r32, r/m32","0F 4F /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if greater (ZF=0 and SF=OF)."
"CMOVG r64, r/m64","REX.W + 0F 4F /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if greater (ZF=0 and SF=OF)."
"CMOVGE r16, r/m16","0F 4D /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if greater or equal (SF=OF)."
"CMOVGE r32, r/m32","0F 4D /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if greater or equal (SF=OF)."
"CMOVGE r64, r/m64","REX.W + 0F 4D /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if greater or equal (SF=OF)."
"CMOVL r16, r/m16","0F 4C /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if less (SF≠OF)."
"CMOVL r32, r/m32","0F 4C /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if less (SF≠OF)."
"CMOVL r64, r/m64","REX.W + 0F 4C /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if less (SF≠OF)."
"CMOVLE r16, r/m16","0F 4E /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if less or equal (ZF=1 or SF≠OF)."
"CMOVLE r32, r/m32","0F 4E /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if less or equal (ZF=1 or SF≠OF)."
"CMOVLE r64, r/m64","REX.W + 0F 4E /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if less or equal (ZF=1 or SF≠OF)."
"CMOVNA r16, r/m16","0F 46 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not above (CF=1 or ZF=1)."
"CMOVNA r32, r/m32","0F 46 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not above (CF=1 or ZF=1)."
"CMOVNA r64, r/m64","REX.W + 0F 46 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not above (CF=1 or ZF=1)."
"CMOVNAE r16, r/m16","0F 42 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not above or equal (CF=1)."
"CMOVNAE r32, r/m32","0F 42 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not above or equal (CF=1)."
"CMOVNAE r64, r/m64","REX.W + 0F 42 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not above or equal (CF=1)."
"CMOVNB r16, r/m16","0F 43 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not below (CF=0)."
"CMOVNB r32, r/m32","0F 43 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not below (CF=0)."
"CMOVNB r64, r/m64","REX.W + 0F 43 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not below (CF=0)."
"CMOVNBE r16, r/m16","0F 47 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not below or equal (CF=0 and ZF=0).CMOVcc—Conditional Move"
"CMOVNBE r32, r/m32","0F 47 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not below or equal (CF=0 and ZF=0)."
"CMOVNBE r64, r/m64","REX.W + 0F 47 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not below or equal (CF=0 and ZF=0)."
"CMOVNC r16, r/m16","0F 43 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not carry (CF=0)."
"CMOVNC r32, r/m32","0F 43 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not carry (CF=0)."
"CMOVNC r64, r/m64","REX.W + 0F 43 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not carry (CF=0)."
"CMOVNE r16, r/m16","0F 45 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not equal (ZF=0)."
"CMOVNE r32, r/m32","0F 45 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not equal (ZF=0)."
"CMOVNE r64, r/m64","REX.W + 0F 45 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not equal (ZF=0)."
"CMOVNG r16, r/m16","0F 4E /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not greater (ZF=1 or SF≠OF)."
"CMOVNG r32, r/m32","0F 4E /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not greater (ZF=1 or SF≠OF)."
"CMOVNG r64, r/m64","REX.W + 0F 4E /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not greater (ZF=1 or SF≠OF)."
"CMOVNGE r16, r/m16","0F 4C /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not greater or equal (SF≠OF)."
"CMOVNGE r32, r/m32","0F 4C /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not greater or equal (SF≠OF)."
"CMOVNGE r64, r/m64","REX.W + 0F 4C /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not greater or equal (SF≠OF)."
"CMOVNL r16, r/m16","0F 4D /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not less (SF=OF)."
"CMOVNL r32, r/m32","0F 4D /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not less (SF=OF)."
"CMOVNL r64, r/m64","REX.W + 0F 4D /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not less (SF=OF)."
"CMOVNLE r16, r/m16","0F 4F /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not less or equal (ZF=0 and SF=OF)."
"CMOVNLE r32, r/m32","0F 4F /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not less or equal (ZF=0 and SF=OF)."
"CMOVNLE r64, r/m64","REX.W + 0F 4F /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not less or equal (ZF=0 and SF=OF)."
"CMOVNO r16, r/m16","0F 41 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not overflow (OF=0)."
"CMOVNO r32, r/m32","0F 41 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not overflow (OF=0)."
"CMOVNO r64, r/m64","REX.W + 0F 41 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not overflow (OF=0)."
"CMOVNP r16, r/m16","0F 4B /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not parity (PF=0)."
"CMOVNP r32, r/m32","0F 4B /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not parity (PF=0)."
"CMOVNP r64, r/m64","REX.W + 0F 4B /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not parity (PF=0)."
"CMOVNS r16, r/m16","0F 49 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not sign (SF=0)."
"CMOVNS r32, r/m32","0F 49 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not sign (SF=0)."
"CMOVNS r64, r/m64","REX.W + 0F 49 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not sign (SF=0)."
"CMOVNZ r16, r/m16","0F 45 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not zero (ZF=0)."
"CMOVNZ r32, r/m32","0F 45 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not zero (ZF=0)."
"CMOVNZ r64, r/m64","REX.W + 0F 45 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if not zero (ZF=0)."
"CMOVO r16, r/m16","0F 40 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if overflow (OF=1)."
"CMOVO r32, r/m32","0F 40 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if overflow (OF=1)."
"CMOVO r64, r/m64","REX.W + 0F 40 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if overflow (OF=1)."
"CMOVP r16, r/m16","0F 4A /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if parity (PF=1)."
"CMOVP r32, r/m32","0F 4A /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if parity (PF=1)."
"CMOVP r64, r/m64","REX.W + 0F 4A /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if parity (PF=1)."
"CMOVPE r16, r/m16","0F 4A /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if parity even (PF=1)."
"CMOVPE r32, r/m32","0F 4A /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if parity even (PF=1)."
"CMOVPE r64, r/m64","REX.W + 0F 4A /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Move if parity even (PF=1).CMOVcc—Conditional Move"
"CMP AL, imm8","3C ib","Valid","Valid","Valid","","AL/AX/EAX/RAX (r)","imm8","NA","NA","","Compare imm8 with AL."
"CMP AX, imm16","3D iw","Valid","Valid","Valid","","AL/AX/EAX/RAX (r)","imm8","NA","NA","","Compare imm16 with AX."
"CMP EAX, imm32","3D id","Valid","Valid","Valid","","AL/AX/EAX/RAX (r)","imm8","NA","NA","","Compare imm32 with EAX."
"CMP RAX, imm32","REX.W + 3D id","Valid","Invalid","Invalid","","AL/AX/EAX/RAX (r)","imm8","NA","NA","","Compare imm32 sign-extended to 64-bits with RAX."
"CMP r/m8, imm8","80 /7 ib","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm8 with r/m8."
"CMP r/m8 , imm8","REX + 80 /7 ib","Valid","Invalid","Invalid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm8 with r/m8."
"CMP r/m16, imm16","81 /7 iw","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm16 with r/m16."
"CMP r/m32, imm32","81 /7 id","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm32 with r/m32."
"CMP r/m64, imm32","REX.W + 81 /7 id","Valid","Invalid","Invalid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm32 sign-extended to 64-bits with r/m64."
"CMP r/m16, imm8","83 /7 ib","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm8 with r/m16."
"CMP r/m32, imm8","83 /7 ib","Valid","Valid","Valid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm8 with r/m32."
"CMP r/m64, imm8","REX.W + 83 /7 ib","Valid","Invalid","Invalid","","ModRM:r/m (r)","imm8","NA","NA","","Compare imm8 with r/m64."
"CMP r/m8, r8","38 /r","Valid","Valid","Valid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Compare r8 with r/m8."
"CMP r/m8 , r8","REX + 38 /r","Valid","Invalid","Invalid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Compare r8 with r/m8."
"CMP r/m16, r16","39 /r","Valid","Valid","Valid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Compare r16 with r/m16."
"CMP r/m32, r32","39 /r","Valid","Valid","Valid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Compare r32 with r/m32."
"CMP r/m64,r64","REX.W + 39 /r","Valid","Invalid","Invalid","","ModRM:r/m (r)","ModRM:reg (r)","NA","NA","","Compare r64 with r/m64."
"CMP r8, r/m8","3A /r","Valid","Valid","Valid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Compare r/m8 with r8."
"CMP r8 , r/m8","REX + 3A /r","Valid","Invalid","Invalid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Compare r/m8 with r8."
"CMP r16, r/m16","3B /r","Valid","Valid","Valid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Compare r/m16 with r16."
"CMP r32, r/m32","3B /r","Valid","Valid","Valid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Compare r/m32 with r32."
"CMP r64, r/m64","REX.W + 3B /r","Valid","Invalid","Invalid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Compare r/m64 with r64."
"CMPPD xmm1, xmm2/m128, imm8","66 0F C2 /r ib","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","Imm8","NA","NA","Compare packed double-precision floating-point values in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a comparison predicate."
"VCMPPD xmm1, xmm2, xmm3/m128, imm8","VEX.NDS.128.66.0F.WIG C2 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Compare packed double-precision floating-point values in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate."
"VCMPPD ymm1, ymm2, ymm3/m256, imm8","VEX.NDS.256.66.0F.WIG C2 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Compare packed double-precision floating-point values in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a comparison predicate."
"VCMPPD k1 {k2}, xmm2, xmm3/m128/m64bcst, imm8","EVEX.NDS.128.66.0F.W1 C2 /r ib","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Full Vector","Compare packed double-precision floating-point values in xmm3/m128/m64bcst and xmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1."
"VCMPPD k1 {k2}, ymm2, ymm3/m256/m64bcst, imm8","EVEX.NDS.256.66.0F.W1 C2 /r ib","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Full Vector","Compare packed double-precision floating-point values in ymm3/m256/m64bcst and ymm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1."
"VCMPPD k1 {k2}, zmm2, zmm3/m512/m64bcst{sae}, imm8","EVEX.NDS.512.66.0F.W1 C2 /r ib","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Full Vector","Compare packed double-precision floating-point values in zmm3/m512/m64bcst and zmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1."
"CMPPS xmm1, xmm2/m128, imm8","NP 0F C2 /r ib","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","Imm8","NA","NA","Compare packed single-precision floating-point values in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a comparison predicate."
"VCMPPS xmm1, xmm2, xmm3/m128, imm8","VEX.NDS.128.0F.WIG C2 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Compare packed single-precision floating-point values in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate."
"VCMPPS ymm1, ymm2, ymm3/m256, imm8","VEX.NDS.256.0F.WIG C2 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Compare packed single-precision floating-point values in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a comparison predicate."
"VCMPPS k1 {k2}, xmm2, xmm3/m128/m32bcst, imm8","EVEX.NDS.128.0F.W0 C2 /r ib","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Full Vector","Compare packed single-precision floating-point values in xmm3/m128/m32bcst and xmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1."
"VCMPPS k1 {k2}, ymm2, ymm3/m256/m32bcst, imm8","EVEX.NDS.256.0F.W0 C2 /r ib","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Full Vector","Compare packed single-precision floating-point values in ymm3/m256/m32bcst and ymm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1."
"VCMPPS k1 {k2}, zmm2, zmm3/m512/m32bcst{sae}, imm8","EVEX.NDS.512.0F.W0 C2 /r ib","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Full Vector","Compare packed single-precision floating-point values in zmm3/m512/m32bcst and zmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1."
"CMPS m8, m8","A6","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, compare byte at address DS:(E)SI with byte at address ES:(E)DI; For 64-bit mode compare byte at address (R|E)SI to byte at address (R|E)DI. The status flags are set accordingly."
"CMPS m16, m16","A7","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, compare word at address DS:(E)SI with word at address ES:(E)DI; For 64-bit mode compare word at address (R|E)SI with word at address (R|E)DI. The status flags are set accordingly."
"CMPS m32, m32","A7","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, compare dword at address DS:(E)SI at dword at address ES:(E)DI; For 64-bit mode compare dword at address (R|E)SI at dword at address (R|E)DI. The status flags are set accordingly."
"CMPS m64, m64","REX.W + A7","Valid","Invalid","Invalid","","NA","NA","NA","NA","","Compares quadword at address (R|E)SI with quadword at address (R|E)DI and sets the status flags accordingly."
"CMPSB","A6","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, compare byte at address DS:(E)SI with byte at address ES:(E)DI; For 64-bit mode compare byte at address (R|E)SI with byte at address (R|E)DI. The status flags are set accordingly."
"CMPSW","A7","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, compare word at address DS:(E)SI with word at address ES:(E)DI; For 64-bit mode compare word at address (R|E)SI with word at address (R|E)DI. The status flags are set accordingly."
"CMPSD","A7","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, compare dword at address DS:(E)SI with dword at address ES:(E)DI; For 64-bit mode compare dword at address (R|E)SI with dword at address (R|E)DI. The status flags are set accordingly."
"CMPSQ","REX.W + A7","Valid","Invalid","Invalid","","NA","NA","NA","NA","","Compares quadword at address (R|E)SI with quadword at address (R|E)DI and sets the status flags accordingly."
"CMPSD xmm1, xmm2/m64, imm8","F2 0F C2 /r ib","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","Imm8","NA","NA","Compare low double-precision floating-point value in xmm2/m64 and xmm1 using bits 2:0 of imm8 as comparison predicate."
"VCMPSD xmm1, xmm2, xmm3/m64, imm8","VEX.NDS.LIG.F2.0F.WIG C2 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Compare low double-precision floating-point value in xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison predicate."
"VCMPSD k1 {k2}, xmm2, xmm3/m64{sae}, imm8","EVEX.NDS.LIG.F2.0F.W1 C2 /r ib","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Tuple1 Scalar","Compare low double-precision floating-point value in xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison predicate with writemask k2 and leave the result in mask register k1."
"CMPSS xmm1, xmm2/m32, imm8","F3 0F C2 /r ib","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","Imm8","NA","NA","Compare low single-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of imm8 as comparison predicate."
"VCMPSS xmm1, xmm2, xmm3/m32, imm8","VEX.NDS.LIG.F3.0F.WIG C2 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Compare low single-precision floating-point value in xmm3/m32 and xmm2 using bits 4:0 of imm8 as comparison predicate."
"VCMPSS k1 {k2}, xmm2, xmm3/m32{sae}, imm8","EVEX.NDS.LIG.F3.0F.W0 C2 /r ib","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Tuple1 Scalar","Compare low single-precision floating-point value in xmm3/m32 and xmm2 using bits 4:0 of imm8 as comparison predicate with writemask k2 and leave the result in mask register k1."
"CMPXCHG r/m8, r8","0F B0/r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL."
"CMPXCHG r/m8,r8","REX + 0F B0/r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL."
"CMPXCHG r/m16, r16","0F B1/r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Compare AX with r/m16. If equal, ZF is set and r16 is loaded into r/m16. Else, clear ZF and load r/m16 into AX."
"CMPXCHG r/m32, r32","0F B1/r","Valid","Valid","Valid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Compare EAX with r/m32. If equal, ZF is set and r32 is loaded into r/m32. Else, clear ZF and load r/m32 into EAX."
"CMPXCHG r/m64, r64","REX.W + 0F B1/r","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","ModRM:reg (r)","NA","NA","","Compare RAX with r/m64. If equal, ZF is set and r64 is loaded into r/m64. Else, clear ZF and load r/m64 into RAX."
"CMPXCHG8B m64","0F C7 /1 m64","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX."
"CMPXCHG16B m128","REX.W + 0F C7 /1","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","NA","NA","NA","","Compare RDX:RAX with m128. If equal, set ZF and load RCX:RBX into m128. Else, clear ZF and load m128 into RDX:RAX."
"COMISD xmm1, xmm2/m64","66 0F 2F /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly."
"VCOMISD xmm1, xmm2/m64","VEX.LIG.66.0F.WIG 2F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly."
"VCOMISD xmm1, xmm2/m64{sae}","EVEX.LIG.66.0F.W1 2F /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Tuple1 Scalar","Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly."
"COMISS xmm1, xmm2/m32","NP 0F 2F /r","Valid","Valid","Invalid","SSE","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly."
"VCOMISS xmm1, xmm2/m32","VEX.LIG.0F.WIG 2F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly."
"VCOMISS xmm1, xmm2/m32{sae}","EVEX.LIG.0F.W0 2F /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Tuple1 Scalar","Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly."
"CPUID","0F A2","Valid","Valid","Valid","","NA","NA","NA","NA","","Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (in some cases, ECX as well)."
"CRC32 r32, r/m8","F2 0F 38 F0 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Accumulate CRC32 on r/m8."
"CRC32 r32, r/m8","F2 REX 0F 38 F0 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Accumulate CRC32 on r/m8."
"CRC32 r32, r/m16","F2 0F 38 F1 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Accumulate CRC32 on r/m16."
"CRC32 r32, r/m32","F2 0F 38 F1 /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Accumulate CRC32 on r/m32."
"CRC32 r64, r/m8","F2 REX.W 0F 38 F0 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Accumulate CRC32 on r/m8."
"CRC32 r64, r/m64","F2 REX.W 0F 38 F1 /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Accumulate CRC32 on r/m64."
"CVTDQ2PD xmm1, xmm2/m64","F3 0F E6 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floating-point values in xmm1."
"VCVTDQ2PD xmm1, xmm2/m64","VEX.128.F3.0F.WIG E6 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floating-point values in xmm1."
"VCVTDQ2PD ymm1, xmm2/m128","VEX.256.F3.0F.WIG E6 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed signed doubleword integers from xmm2/mem to four packed double-precision floating-point values in ymm1."
"VCVTDQ2PD xmm1 {k1}{z}, xmm2/m128/m32bcst","EVEX.128.F3.0F.W0 E6 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Half Vector","Convert 2 packed signed doubleword integers from xmm2/m128/m32bcst to eight packed double-precision floating-point values in xmm1 with writemask k1."
"VCVTDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst","EVEX.256.F3.0F.W0 E6 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Half Vector","Convert 4 packed signed doubleword integers from xmm2/m128/m32bcst to 4 packed double-precision floating-point values in ymm1 with writemask k1."
"VCVTDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst","EVEX.512.F3.0F.W0 E6 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Half Vector","Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1."
"CVTDQ2PS xmm1, xmm2/m128","NP 0F 5B /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1."
"VCVTDQ2PS xmm1, xmm2/m128","VEX.128.0F.WIG 5B /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1."
"VCVTDQ2PS ymm1, ymm2/m256","VEX.256.0F.WIG 5B /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert eight packed signed doubleword integers from ymm2/mem to eight packed single-precision floating-point values in ymm1."
"VCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst","EVEX.128.0F.W0 5B /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert four packed signed doubleword integers from xmm2/m128/m32bcst to four packed single-precision floating-point values in xmm1with writemask k1."
"VCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst","EVEX.256.0F.W0 5B /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed single-precision floating-point values in ymm1with writemask k1."
"VCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}","EVEX.512.0F.W0 5B /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert sixteen packed signed doubleword integers from zmm2/m512/m32bcst to sixteen packed single-precision floating-point values in zmm1with writemask k1."
"CVTPD2DQ xmm1, xmm2/m128","F2 0F E6 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1."
"VCVTPD2DQ xmm1, xmm2/m128","VEX.128.F2.0F.WIG E6 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1."
"VCVTPD2DQ xmm1, ymm2/m256","VEX.256.F2.0F.WIG E6 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1."
"VCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst","EVEX.128.F2.0F.W1 E6 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 subject to writemask k1."
"VCVTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcst","EVEX.256.F2.0F.W1 E6 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 subject to writemask k1."
"VCVTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er}","EVEX.512.F2.0F.W1 E6 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 subject to writemask k1."
"CVTPD2PI mm, xmm/m128","66 0F 2D /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Convert two packed double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm."
"CVTPD2PS xmm1, xmm2/m128","66 0F 5A /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed double-precision floating-point values in xmm2/mem to two single-precision floating-point values in xmm1."
"VCVTPD2PS xmm1, xmm2/m128","VEX.128.66.0F.WIG 5A /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed double-precision floating-point values in xmm2/mem to two single-precision floating-point values in xmm1."
"VCVTPD2PS xmm1, ymm2/m256","VEX.256.66.0F.WIG 5A /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed double-precision floating-point values in ymm2/mem to four single-precision floating-point values in xmm1."
"VCVTPD2PS xmm1 {k1}{z}, xmm2/m128/m64bcst","EVEX.128.66.0F.W1 5A /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two single-precision floating-point values in xmm1with writemask k1."
"VCVTPD2PS xmm1 {k1}{z}, ymm2/m256/m64bcst","EVEX.256.66.0F.W1 5A /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four single-precision floating-point values in xmm1with writemask k1."
"VCVTPD2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er}","EVEX.512.66.0F.W1 5A /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight single-precision floating-point values in ymm1with writemask k1."
"CVTPI2PD xmm, mm/m64","66 0F 2A /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Convert two packed signed doubleword integers from mm/mem64 to two packed double-precision floating-point values in xmm."
"CVTPI2PS xmm, mm/m64","NP 0F 2A /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Convert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm."
"CVTPS2DQ xmm1, xmm2/m128","66 0F 5B /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1."
"VCVTPS2DQ xmm1, xmm2/m128","VEX.128.66.0F.WIG 5B /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1."
"VCVTPS2DQ ymm1, ymm2/m256","VEX.256.66.0F.WIG 5B /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert eight packed single-precision floating-point values from ymm2/mem to eight packed signed doubleword values in ymm1."
"VCVTPS2DQ xmm1 {k1}{z}, xmm2/m128/m32bcst","EVEX.128.66.0F.W0 5B /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed doubleword values in xmm1 subject to writemask k1."
"VCVTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcst","EVEX.256.66.0F.W0 5B /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed doubleword values in ymm1 subject to writemask k1."
"VCVTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er}","EVEX.512.66.0F.W0 5B /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed signed doubleword values in zmm1 subject to writemask k1."
"CVTPS2PD xmm1, xmm2/m64","NP 0F 5A /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1."
"VCVTPS2PD xmm1, xmm2/m64","VEX.128.0F.WIG 5A /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1."
"VCVTPS2PD ymm1, xmm2/m128","VEX.256.0F.WIG 5A /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed single-precision floating-point values in xmm2/m128 to four packed double-precision floating-point values in ymm1."
"VCVTPS2PD xmm1 {k1}{z}, xmm2/m64/m32bcst","EVEX.128.0F.W0 5A /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Half Vector","Convert two packed single-precision floating-point values in xmm2/m64/m32bcst to packed double-precision floating-point values in xmm1 with writemask k1."
"VCVTPS2PD ymm1 {k1}{z}, xmm2/m128/m32bcst","EVEX.256.0F.W0 5A /r","Valid","Valid","Invalid","AVX512VL","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Half Vector","Convert four packed single-precision floating-point values in xmm2/m128/m32bcst to packed double-precision floating-point values in ymm1 with writemask k1."
"VCVTPS2PD zmm1 {k1}{z}, ymm2/m256/m32bcst{sae}","EVEX.512.0F.W0 5A /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Half Vector","Convert eight packed single-precision floating-point values in ymm2/m256/b32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1."
"CVTPS2PI mm, xmm/m64","NP 0F 2D /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Convert two packed single-precision floating-point values from xmm/m64 to two packed signed doubleword integers in mm."
"CVTSD2SI r32,xmm1/m64",F2 0F 2D /r,Valid,Valid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer r32.
"CVTSD2SI r64,xmm1/m64",F2 REX.W 0F 2D /r,Valid,Invalid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer signextended into r64.
"VCVTSD2SI r32,xmm1/m64",VEX.LIG.F2.0F.W0 2D /r,Valid,Valid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer r32.
"VCVTSD2SI r64,xmm1/m64",VEX.LIG.F2.0F.W1 2D /r,Valid,Invalid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer signextended into r64.
"VCVTSD2SI r32,xmm1/m64{er}",EVEX.LIG.F2.0F.W0 2D /r,Valid,Valid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer r32.
"VCVTSD2SI r64,xmm1/m64{er}",EVEX.LIG.F2.0F.W1 2D /r,Valid,Invalid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer signextended into r64.
"CVTSD2SS xmm1, xmm2/m64","F2 0F 5A /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert one double-precision floating-point value in xmm2/m64 to one single-precision floating-point value in xmm1."
"VCVTSD2SS xmm1,xmm2, xmm3/m64","VEX.NDS.LIG.F2.0F.WIG 5A /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Convert one double-precision floating-point value in xmm3/m64 to one single-precision floating-point value and merge with high bits in xmm2."
"VCVTSD2SS xmm1 {k1}{z}, xmm2, xmm3/m64{er}","EVEX.NDS.LIG.F2.0F.W1 5A /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Convert one double-precision floating-point value in xmm3/m64 to one single-precision floating-point value and merge with high bits in xmm2 under writemask k1."
"CVTSI2SD xmm1,r32/m32",F2 0F 2A /r,Valid,Valid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,SSE2,Convert one signed doubleword integer from r32/m32 to one double-precision floating-point value in xmm1.
"CVTSI2SD xmm1,r/m64",F2 REX.W 0F 2A /r,Valid,Invalid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,SSE2,Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1.
"VCVTSI2SD xmm1,xmm2,r/m32",VEX.NDS.LIG.F2.0F.W0 2A /r,Valid,Valid,Invalid,AVX,ModRM:reg (w),VEX.vvvv,ModRM:r/m (r),NA,AVX,Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm1.
"VCVTSI2SD xmm1,xmm2,r/m64",VEX.NDS.LIG.F2.0F.W1 2A /r,Valid,Invalid,Invalid,AVX,ModRM:reg (w),VEX.vvvv,ModRM:r/m (r),NA,AVX,Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1.
"VCVTSI2SD xmm1,xmm2,r/m32",EVEX.NDS.LIG.F2.0F.W0 2A /r,Valid,Valid,Invalid,AVX512F,ModRM:reg (w),EVEX.vvvv,ModRM:r/m (r),NA,AVX512F,Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm1.
"VCVTSI2SD xmm1,xmm2,r/m64{er}",EVEX.NDS.LIG.F2.0F.W1 2A /r,Valid,Invalid,Invalid,AVX512F,ModRM:reg (w),EVEX.vvvv,ModRM:r/m (r),NA,AVX512F,Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1.
"CVTSI2SS xmm1,r/m32",F3 0F 2A /r,Valid,Valid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1.
"CVTSI2SS xmm1,r/m64",F3 REX.W 0F 2A /r,Valid,Invalid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1.
"VCVTSI2SS xmm1,xmm2,r/m32",VEX.NDS.LIG.F3.0F.W0 2A /r,Valid,Valid,Invalid,AVX,ModRM:reg (w),VEX.vvvv,ModRM:r/m (r),NA,,Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1.
"VCVTSI2SS xmm1,xmm2,r/m64",VEX.NDS.LIG.F3.0F.W1 2A /r,Valid,Invalid,Invalid,AVX,ModRM:reg (w),VEX.vvvv,ModRM:r/m (r),NA,,Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1.
"VCVTSI2SS xmm1,xmm2,r/m32{er}",EVEX.NDS.LIG.F3.0F.W0 2A /r,Valid,Valid,Invalid,AVX512F,ModRM:reg (w),EVEX.vvvv,ModRM:r/m (r),NA,,Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1.
"VCVTSI2SS xmm1,xmm2,r/m64{er}",EVEX.NDS.LIG.F3.0F.W1 2A /r,Valid,Invalid,Invalid,AVX512F,ModRM:reg (w),EVEX.vvvv,ModRM:r/m (r),NA,Tuple1 Scalar,Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1.
"CVTSS2SD xmm1, xmm2/m32","F3 0F 5A /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1."
"VCVTSS2SD xmm1, xmm2, xmm3/m32","VEX.NDS.LIG.F3.0F.WIG 5A /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2."
"VCVTSS2SD xmm1 {k1}{z}, xmm2, xmm3/m32{sae}","EVEX.NDS.LIG.F3.0F.W0 5A /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2 under writemask k1."
"CVTSS2SI r32,xmm1/m32",F3 0F 2D /r,Valid,Valid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.
"CVTSS2SI r64,xmm1/m32",F3 REX.W 0F 2D /r,Valid,Invalid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64.
"VCVTSS2SI r32,xmm1/m32",VEX.LIG.F3.0F.W0 2D /r,Valid,Valid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.
"VCVTSS2SI r64,xmm1/m32",VEX.LIG.F3.0F.W1 2D /r,Valid,Invalid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64.
"VCVTSS2SI r32,xmm1/m32{er}",EVEX.LIG.F3.0F.W0 2D /r,Valid,Valid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.
"VCVTSS2SI r64,xmm1/m32{er}",EVEX.LIG.F3.0F.W1 2D /r,Valid,Invalid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64.
"CVTTPD2DQ xmm1, xmm2/m128","66 0F E6 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1 using truncation."
"VCVTTPD2DQ xmm1, xmm2/m128","VEX.128.66.0F.WIG E6 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1 using truncation."
"VCVTTPD2DQ xmm1, ymm2/m256","VEX.256.66.0F.WIG E6 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1 using truncation."
"VCVTTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst","EVEX.128.66.0F.W1 E6 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 using truncation subject to writemask k1."
"VCVTTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcst","EVEX.256.66.0F.W1 E6 /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 using truncation subject to writemask k1."
"VCVTTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{sae}","EVEX.512.66.0F.W1 E6 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 using truncation subject to writemask k1."
"CVTTPD2PI mm, xmm/m128","66 0F 2C /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Convert two packer double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm using truncation."
"CVTTPS2DQ xmm1, xmm2/m128","F3 0F 5B /r","Valid","Valid","Invalid","SSE2","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1 using truncation."
"VCVTTPS2DQ xmm1, xmm2/m128","VEX.128.F3.0F.WIG 5B /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1 using truncation."
"VCVTTPS2DQ ymm1, ymm2/m256","VEX.256.F3.0F.WIG 5B /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","NA","Convert eight packed single-precision floating-point values from ymm2/mem to eight packed signed doubleword values in ymm1 using truncation."
"VCVTTPS2DQ xmm1 {k1}{z}, xmm2/m128/m32bcst","EVEX.128.F3.0F.W0 5B /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed doubleword values in xmm1 using truncation subject to writemask k1."
"VCVTTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcst","EVEX.256.F3.0F.W0 5B /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed doubleword values in ymm1 using truncation subject to writemask k1."
"VCVTTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst {sae}","EVEX.512.F3.0F.W0 5B /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","Full Vector","Convert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed signed doubleword values in zmm1 using truncation subject to writemask k1."
"CVTTPS2PI mm, xmm/m64","NP 0F 2C /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Convert two single-precision floating-point values from xmm/m64 to two signed doubleword signed integers in mm using truncation."
"CVTTSD2SI r32,xmm1/m64",F2 0F 2C /r,Valid,Valid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation.
"CVTTSD2SI r64,xmm1/m64",F2 REX.W 0F 2C /r,Valid,Invalid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation.
"VCVTTSD2SI r32,xmm1/m64",VEX.LIG.F2.0F.W0 2C /r,Valid,Valid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation.
"VCVTTSD2SI r64,xmm1/m64",VEX.LIG.F2.0F.W1 2C /r,Valid,Invalid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation.
"VCVTTSD2SI r32,xmm1/m64{sae}",EVEX.LIG.F2.0F.W0 2C,Valid,Valid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation.
"VCVTTSD2SI r64,xmm1/m64{sae}",EVEX.LIG.F2.0F.W1 2C,Valid,Invalid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation.
"CVTTSS2SI r32,xmm1/m32",F3 0F 2C /r,Valid,Valid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation.
"CVTTSS2SI r64,xmm1/m32",F3 REX.W 0F 2C /r,Valid,Invalid,Invalid,SSE2,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation.
"VCVTTSS2SI r32,xmm1/m32",VEX.LIG.F3.0F.W0 2C /r,Valid,Valid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation.
"VCVTTSS2SI r64,xmm1/m32",VEX.LIG.F3.0F.W1 2C /r,Valid,Invalid,Invalid,AVX,ModRM:reg (w),ModRM:r/m (r),NA,NA,,Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation.
"VCVTTSS2SI r32,xmm1/m32{sae}",EVEX.LIG.F3.0F.W0 2C,Valid,Valid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation.
"VCVTTSS2SI r64,xmm1/m32{sae}",EVEX.LIG.F3.0F.W1 2C,Valid,Invalid,Invalid,AVX512F,ModRM:reg (w),ModRM:r/m (r),NA,NA,Tuple1 Fixed,Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation.
"CWD","99","Valid","Valid","Valid","","NA","NA","NA","NA","","DX:AX ↠sign-extend of AX."
"CDQ","99","Valid","Valid","Valid","","NA","NA","NA","NA","","EDX:EAX ↠sign-extend of EAX."
"CQO","REX.W + 99","Valid","Invalid","Invalid","","NA","NA","NA","NA","","RDX:RAX↠sign-extend of RAX."
"DAA","27","Invalid","Valid","Valid","","NA","NA","NA","NA","","Decimal adjust AL after addition."
"DAS","2F","Invalid","Valid","Valid","","NA","NA","NA","NA","","Decimal adjust AL after subtraction."
"DEC r/m8","FE /1","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Decrement r/m8 by 1."
"DEC r/m8","REX + FE /1","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","NA","NA","NA","","Decrement r/m8 by 1."
"DEC r/m16","FF /1","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Decrement r/m16 by 1."
"DEC r/m32","FF /1","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Decrement r/m32 by 1."
"DEC r/m64","REX.W + FF /1","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","NA","NA","NA","","Decrement r/m64 by 1."
"DEC r16","48+rw","Invalid","Valid","Valid","","opcode +rd (r, w)","NA","NA","NA","","Decrement r16 by 1."
"DEC r32","48+rd","Invalid","Valid","Valid","","opcode +rd (r, w)","NA","NA","NA","","Decrement r32 by 1."
"DIV r/m8","F6 /6","Valid","Valid","Valid","","ModRM:r/m (w)","NA","NA","NA","","Unsigned divide AX by r/m8, with result stored in AL ↠Quotient, AH ↠Remainder."
"DIV r/m8","REX + F6 /6","Valid","Invalid","Invalid","","ModRM:r/m (w)","NA","NA","NA","","Unsigned divide AX by r/m8, with result stored in AL ↠Quotient, AH ↠Remainder."
"DIV r/m16","F7 /6","Valid","Valid","Valid","","ModRM:r/m (w)","NA","NA","NA","","Unsigned divide DX:AX by r/m16, with result stored in AX ↠Quotient, DX ↠Remainder."
"DIV r/m32","F7 /6","Valid","Valid","Valid","","ModRM:r/m (w)","NA","NA","NA","","Unsigned divide EDX:EAX by r/m32, with result stored in EAX ↠Quotient, EDX ↠Remainder."
"DIV r/m64","REX.W + F7 /6","Valid","Invalid","Invalid","","ModRM:r/m (w)","NA","NA","NA","","Unsigned divide RDX:RAX by r/m64, with result stored in RAX ↠Quotient, RDX ↠Remainder."
"DIVPD xmm1, xmm2/m128","66 0F 5E /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Divide packed double-precision floating-point values in xmm1 by packed double-precision floating-point values in xmm2/mem."
"VDIVPD xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG 5E /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Divide packed double-precision floating-point values in xmm2 by packed double-precision floating-point values in xmm3/mem."
"VDIVPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG 5E /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Divide packed double-precision floating-point values in ymm2 by packed double-precision floating-point values in ymm3/mem."
"VDIVPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst","EVEX.NDS.128.66.0F.W1 5E /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Divide packed double-precision floating-point values in xmm2 by packed double-precision floating-point values in xmm3/m128/m64bcst and write results to xmm1 subject to writemask k1."
"VDIVPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst","EVEX.NDS.256.66.0F.W1 5E /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Divide packed double-precision floating-point values in ymm2 by packed double-precision floating-point values in ymm3/m256/m64bcst and write results to ymm1 subject to writemask k1."
"VDIVPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}","EVEX.NDS.512.66.0F.W1 5E /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Divide packed double-precision floating-point values in zmm2 by packed double-precision FP values in zmm3/m512/m64bcst and write results to zmm1 subject to writemask k1."
"DIVPS xmm1, xmm2/m128","NP 0F 5E /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Divide packed single-precision floating-point values in xmm1 by packed single-precision floating-point values in xmm2/mem."
"VDIVPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.0F.WIG 5E /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Divide packed single-precision floating-point values in xmm2 by packed single-precision floating-point values in xmm3/mem."
"VDIVPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.0F.WIG 5E /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Divide packed single-precision floating-point values in ymm2 by packed single-precision floating-point values in ymm3/mem."
"VDIVPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst","EVEX.NDS.128.0F.W0 5E /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Divide packed single-precision floating-point values in xmm2 by packed single-precision floating-point values in xmm3/m128/m32bcst and write results to xmm1 subject to writemask k1."
"VDIVPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst","EVEX.NDS.256.0F.W0 5E /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Divide packed single-precision floating-point values in ymm2 by packed single-precision floating-point values in ymm3/m256/m32bcst and write results to ymm1 subject to writemask k1."
"VDIVPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}","EVEX.NDS.512.0F.W0 5E /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Divide packed single-precision floating-point values in zmm2 by packed single-precision floating-point values in zmm3/m512/m32bcst and write results to zmm1 subject to writemask k1."
"DIVSD xmm1, xmm2/m64","F2 0F 5E /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Divide low double-precision floating-point value in xmm1 by low double-precision floating-point value in xmm2/m64."
"VDIVSD xmm1, xmm2, xmm3/m64","VEX.NDS.LIG.F2.0F.WIG 5E /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Divide low double-precision floating-point value in xmm2 by low double-precision floating-point value in xmm3/m64."
"VDIVSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}","EVEX.NDS.LIG.F2.0F.W1 5E /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Divide low double-precision floating-point value in xmm2 by low double-precision floating-point value in xmm3/m64."
"DIVSS xmm1, xmm2/m32","F3 0F 5E /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2/m32."
"VDIVSS xmm1, xmm2, xmm3/m32","VEX.NDS.LIG.F3.0F.WIG 5E /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Divide low single-precision floating-point value in xmm2 by low single-precision floating-point value in xmm3/m32."
"VDIVSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}","EVEX.NDS.LIG.F3.0F.W0 5E /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Divide low single-precision floating-point value in xmm2 by low single-precision floating-point value in xmm3/m32."
"DPPD xmm1, xmm2/m128, imm8","66 0F 3A 41 /r ib","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","imm8","NA","","Selectively multiply packed DP floating-point values from xmm1 with packed DP floating-point values from xmm2, add and selectively store the packed DP floating-point values to xmm1."
"VDPPD xmm1,xmm2, xmm3/m128, imm8","VEX.NDS.128.66.0F3A.WIG 41 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8","","Selectively multiply packed DP floating-point values from xmm2 with packed DP floating-point values from xmm3, add and selectively store the packed DP floating-point values to xmm1."
"DPPS xmm1, xmm2/m128, imm8","66 0F 3A 40 /r ib","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","imm8","NA","","Selectively multiply packed SP floating-point values from xmm1 with packed SP floating-point values from xmm2, add and selectively store the packed SP floating-point values or zero values to xmm1."
"VDPPS xmm1,xmm2, xmm3/m128, imm8","VEX.NDS.128.66.0F3A.WIG 40 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8","","Multiply packed SP floating point values from xmm1 with packed SP floating point values from xmm2/mem selectively add and store to xmm1."
"VDPPS ymm1, ymm2, ymm3/m256, imm8","VEX.NDS.256.66.0F3A.WIG 40 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","imm8","","Multiply packed single-precision floating-point values from ymm2 with packed SP floating point values from ymm3/mem, selectively add pairs of elements and store to ymm1."
"EMMS","NP 0F 77","Valid","Valid","Valid","","NA","NA","NA","NA","","Set the x87 FPU tag word to empty."
"ENTER imm16, 0","C8 iw 00","Valid","Valid","Valid","","iw","imm8","NA","NA","","Create a stack frame for a procedure."
"ENTER imm16,1","C8 iw 01","Valid","Valid","Valid","","iw","imm8","NA","NA","","Create a stack frame with a nested pointer for a procedure."
"ENTER imm16, imm8","C8 iw ib","Valid","Valid","Valid","","iw","imm8","NA","NA","","Create a stack frame with nested pointers for a procedure."
"EXTRACTPS reg/m32, xmm1, imm8","66 0F 3A 17 /r ib","Valid","Valid","Invalid","SSE4_1","ModRM:r/m (w)","ModRM:reg (r)","Imm8","NA","NA","Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable."
"VEXTRACTPS reg/m32, xmm1, imm8","VEX.128.66.0F3A.WIG 17 /r ib","Valid","Valid","Invalid","AVX","ModRM:r/m (w)","ModRM:reg (r)","Imm8","NA","NA","Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable."
"VEXTRACTPS reg/m32, xmm1, imm8","EVEX.128.66.0F3A.WIG 17 /r ib","Valid","Valid","Invalid","AVX512F","ModRM:r/m (w)","ModRM:reg (r)","Imm8","NA","Tuple1 Scalar","Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable."
"F2XM1","D9 F0","Valid","Valid","Valid","","","","","","","Replace ST(0) with (2 ST(0) – 1)."
"FABS","D9 E1","Valid","Valid","Valid","","","","","","","Replace ST with its absolute value."
"FADD m32fp","D8 /0","Valid","Valid","Valid","","","","","","","Add m32fp to ST(0) and store result in ST(0)."
"FADD m64fp","DC /0","Valid","Valid","Valid","","","","","","","Add m64fp to ST(0) and store result in ST(0)."
"FADD ST(0), ST(i)","D8 C0+i","Valid","Valid","Valid","","","","","","","Add ST(0) to ST(i) and store result in ST(0)."
"FADD ST(i), ST(0)","DC C0+i","Valid","Valid","Valid","","","","","","","Add ST(i) to ST(0) and store result in ST(i)."
"FADDP ST(i), ST(0)","DE C0+i","Valid","Valid","Valid","","","","","","","Add ST(0) to ST(i), store result in ST(i), and pop the register stack."
"FADDP","DE C1","Valid","Valid","Valid","","","","","","","Add ST(0) to ST(1), store result in ST(1), and pop the register stack."
"FIADD m32int","DA /0","Valid","Valid","Valid","","","","","","","Add m32int to ST(0) and store result in ST(0)."
"FIADD m16int","DE /0","Valid","Valid","Valid","","","","","","","Add m16int to ST(0) and store result in ST(0).FADD/FADDP/FIADD—Add This instruction’s operation is the same in non-64-bit modes and 64-bit mode."
FBLD m80dec,DF /4,Valid,Valid,Valid,,,,,,,Convert BCD value to floating-point and push onto the FPU stack.
"FBSTP m80bcd","DF /6","Valid","Valid","Valid","","","","","","","Store ST(0) in m80bcd and pop ST(0)."
"FCHS","D9 E0","Valid","Valid","Valid","","","","","","","Complements sign of ST(0)."
"FCLEX","9B DB E2","Valid","Valid","Valid","","","","","","","Clear floating-point exception flags after checking for pending unmasked floating-point exceptions."
"FNCLEX","DB E2","Valid","Valid","Valid","","","","","","","Clear floating-point exception flags without checking for pending unmasked floating-point exceptions."
"FCMOVB ST(0), ST(i)","DA C0+i","Valid","Valid","Valid","","","","","","","Move if below (CF=1)."
"FCMOVE ST(0), ST(i)","DA C8+i","Valid","Valid","Valid","","","","","","","Move if equal (ZF=1)."
"FCMOVBE ST(0), ST(i)","DA D0+i","Valid","Valid","Valid","","","","","","","Move if below or equal (CF=1 or ZF=1)."
"FCMOVU ST(0), ST(i)","DA D8+i","Valid","Valid","Valid","","","","","","","Move if unordered (PF=1)."
"FCMOVNB ST(0), ST(i)","DB C0+i","Valid","Valid","Valid","","","","","","","Move if not below (CF=0)."
"FCMOVNE ST(0), ST(i)","DB C8+i","Valid","Valid","Valid","","","","","","","Move if not equal (ZF=0)."
"FCMOVNBE ST(0), ST(i)","DB D0+i","Valid","Valid","Valid","","","","","","","Move if not below or equal (CF=0 and ZF=0)."
"FCMOVNU ST(0), ST(i)","DB D8+i","Valid","Valid","Valid","","","","","","","Move if not unordered (PF=0)."
"FCOM m32fp","D8 /2","Valid","Valid","Valid","","","","","","","Compare ST(0) with m32fp."
"FCOM m64fp","DC /2","Valid","Valid","Valid","","","","","","","Compare ST(0) with m64fp."
"FCOM ST(i)","D8 D0+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i)."
"FCOM","D8 D1","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(1)."
"FCOMP m32fp","D8 /3","Valid","Valid","Valid","","","","","","","Compare ST(0) with m32fp and pop register stack."
"FCOMP m64fp","DC /3","Valid","Valid","Valid","","","","","","","Compare ST(0) with m64fp and pop register stack."
"FCOMP ST(i)","D8 D8+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i) and pop register stack."
"FCOMP","D8 D9","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(1) and pop register stack."
"FCOMPP","DE D9","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(1) and pop register stack twice."
"FCOMI ST, ST(i)","DB F0+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i) and set status flags accordingly."
"FCOMIP ST, ST(i)","DF F0+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i), set status flags accordingly, and pop register stack."
"FUCOMI ST, ST(i)","DB E8+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly."
"FUCOMIP ST, ST(i)","DF E8+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack."
"FCOS","D9 FF","Valid","Valid","Valid","","","","","","","Replace ST(0) with its approximate cosine."
"FDECSTP","D9 F6","Valid","Valid","Valid","","","","","","","Decrement TOP field in FPU status word."
"FDIV m32fp","D8 /6","Valid","Valid","Valid","","","","","","","Divide ST(0) by m32fp and store result in ST(0)."
"FDIV m64fp","DC /6","Valid","Valid","Valid","","","","","","","Divide ST(0) by m64fp and store result in ST(0)."
"FDIV ST(0), ST(i)","D8 F0+i","Valid","Valid","Valid","","","","","","","Divide ST(0) by ST(i) and store result in ST(0)."
"FDIV ST(i), ST(0)","DC F8+i","Valid","Valid","Valid","","","","","","","Divide ST(i) by ST(0) and store result in ST(i)."
"FDIVP ST(i), ST(0)","DE F8+i","Valid","Valid","Valid","","","","","","","Divide ST(i) by ST(0), store result in ST(i), and pop the register stack."
"FDIVP","DE F9","Valid","Valid","Valid","","","","","","","Divide ST(1) by ST(0), store result in ST(1), and pop the register stack."
"FIDIV m32int","DA /6","Valid","Valid","Valid","","","","","","","Divide ST(0) by m32int and store result in ST(0)."
"FIDIV m16int","DE /6","Valid","Valid","Valid","","","","","","","Divide ST(0) by m16int and store result in ST(0).FDIV/FDIVP/FIDIV—Divide This instruction’s operation is the same in non-64-bit modes and 64-bit mode."
"FDIVR m32fp","D8 /7","Valid","Valid","Valid","","","","","","","Divide m32fp by ST(0) and store result in ST(0)."
"FDIVR m64fp","DC /7","Valid","Valid","Valid","","","","","","","Divide m64fp by ST(0) and store result in ST(0)."
"FDIVR ST(0), ST(i)","D8 F8+i","Valid","Valid","Valid","","","","","","","Divide ST(i) by ST(0) and store result in ST(0)."
"FDIVR ST(i), ST(0)","DC F0+i","Valid","Valid","Valid","","","","","","","Divide ST(0) by ST(i) and store result in ST(i)."
"FDIVRP ST(i), ST(0)","DE F0+i","Valid","Valid","Valid","","","","","","","Divide ST(0) by ST(i), store result in ST(i), and pop the register stack."
"FDIVRP","DE F1","Valid","Valid","Valid","","","","","","","Divide ST(0) by ST(1), store result in ST(1), and pop the register stack."
"FIDIVR m32int","DA /7","Valid","Valid","Valid","","","","","","","Divide m32int by ST(0) and store result in ST(0)."
"FIDIVR m16int","DE /7","Valid","Valid","Valid","","","","","","","Divide m16int by ST(0) and store result in ST(0).FDIVR/FDIVRP/FIDIVR—Reverse Divide When the source operand is an integer 0, it is treated as a +0. This instruction’s operation is the same in non-64-bit modes and 64-bit mode."
"FFREE ST(i)","DD C0+i","Valid","Valid","Valid","","","","","","","Sets tag for ST(i) to empty."
"FICOM m16int","DE /2","Valid","Valid","Valid","","","","","","","Compare ST(0) with m16int."
"FICOM m32int","DA /2","Valid","Valid","Valid","","","","","","","Compare ST(0) with m32int."
"FICOMP m16int","DE /3","Valid","Valid","Valid","","","","","","","Compare ST(0) with m16int and pop stack register."
"FICOMP m32int","DA /3","Valid","Valid","Valid","","","","","","","Compare ST(0) with m32int and pop stack register."
"FILD m16int","DF /0","Valid","Valid","Valid","","","","","","","Push m16int onto the FPU register stack."
"FILD m32int","DB /0","Valid","Valid","Valid","","","","","","","Push m32int onto the FPU register stack."
"FILD m64int","DF /5","Valid","Valid","Valid","","","","","","","Push m64int onto the FPU register stack.FILD—Load Integer Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used."
"FINCSTP","D9 F7","Valid","Valid","Valid","","","","","","","Increment the TOP field in the FPU status register."
"FINIT","9B DB E3","Valid","Valid","Valid","","","","","","","Initialize FPU after checking for pending unmasked floating-point exceptions."
"FNINIT","DB E3","Valid","Valid","Valid","","","","","","","Initialize FPU without checking for pending unmasked floating-point exceptions."
"FIST m16int","DF /2","Valid","Valid","Valid","","","","","","","Store ST(0) in m16int."
"FIST m32int","DB /2","Valid","Valid","Valid","","","","","","","Store ST(0) in m32int."
"FISTP m16int","DF /3","Valid","Valid","Valid","","","","","","","Store ST(0) in m16int and pop register stack."
"FISTP m32int","DB /3","Valid","Valid","Valid","","","","","","","Store ST(0) in m32int and pop register stack."
"FISTP m64int","DF /7","Valid","Valid","Valid","","","","","","","Store ST(0) in m64int and pop register stack."
"FISTTP m16int","DF /1","Valid","Valid","Valid","","","","","","","Store ST(0) in m16int with truncation."
"FISTTP m32int","DB /1","Valid","Valid","Valid","","","","","","","Store ST(0) in m32int with truncation."
"FISTTP m64int","DD /1","Valid","Valid","Valid","","","","","","","Store ST(0) in m64int with truncation."
"FLD m32fp","D9 /0","Valid","Valid","Valid","","","","","","","Push m32fp onto the FPU register stack."
"FLD m64fp","DD /0","Valid","Valid","Valid","","","","","","","Push m64fp onto the FPU register stack."
"FLD m80fp","DB /5","Valid","Valid","Valid","","","","","","","Push m80fp onto the FPU register stack."
"FLD ST(i)","D9 C0+i","Valid","Valid","Valid","","","","","","","Push ST(i) onto the FPU register stack.FLD—Load Floating Point Value Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used."
"FLD1","D9 E8","Valid","Valid","Valid","","","","","","","Push +1.0 onto the FPU register stack."
"FLDL2T","D9 E9","Valid","Valid","Valid","","","","","","","Push log 10 onto the FPU register stack."
"FLDL2E","D9 EA","Valid","Valid","Valid","","","","","","","Push log e onto the FPU register stack."
"FLDPI","D9 EB","Valid","Valid","Valid","","","","","","","Push π onto the FPU register stack."
"FLDLG2","D9 EC","Valid","Valid","Valid","","","","","","","Push log 10 2 onto the FPU register stack."
"FLDLN2","D9 ED","Valid","Valid","Valid","","","","","","","Push log 2 onto the FPU register stack."
"FLDZ","D9 EE","Valid","Valid","Valid","","","","","","","Push +0.0 onto the FPU register stack."
"FLDCW m2byte","D9 /5","Valid","Valid","Valid","","","","","","","Load FPU control word from m2byte.FLDCW—Load x87 FPU Control Word Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used."
"FLDENV m14/28byte","D9 /4","Valid","Valid","Valid","","","","","","","Load FPU environment from m14byte or m28byte.FLDENV—Load x87 FPU Environment Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used."
"FMUL m32fp","D8 /1","Valid","Valid","Valid","","","","","","","Multiply ST(0) by m32fp and store result in ST(0)."
"FMUL m64fp","DC /1","Valid","Valid","Valid","","","","","","","Multiply ST(0) by m64fp and store result in ST(0)."
"FMUL ST(0), ST(i)","D8 C8+i","Valid","Valid","Valid","","","","","","","Multiply ST(0) by ST(i) and store result in ST(0)."
"FMUL ST(i), ST(0)","DC C8+i","Valid","Valid","Valid","","","","","","","Multiply ST(i) by ST(0) and store result in ST(i)."
"FMULP ST(i), ST(0)","DE C8+i","Valid","Valid","Valid","","","","","","","Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack."
"FMULP","DE C9","Valid","Valid","Valid","","","","","","","Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack."
"FIMUL m32int","DA /1","Valid","Valid","Valid","","","","","","","Multiply ST(0) by m32int and store result in ST(0)."
"FIMUL m16int","DE /1","Valid","Valid","Valid","","","","","","","Multiply ST(0) by m16int and store result in ST(0).FMUL/FMULP/FIMUL—Multiply This instruction’s operation is the same in non-64-bit modes and 64-bit mode."
"FNOP","D9 D0","Valid","Valid","Valid","","","","","","","No operation is performed."
"FPATAN","D9 F3","Valid","Valid","Valid","","","","","","","Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack."
"FPREM","D9 F8","Valid","Valid","Valid","","","","","","","Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1)."
"FPREM1","D9 F5","Valid","Valid","Valid","","","","","","","Replace ST(0) with the IEEE remainder obtained from dividing ST(0) by ST(1)."
"FPTAN","D9 F2","Valid","Valid","Valid","","","","","","","Replace ST(0) with its approximate tangent and push 1 onto the FPU stack."
"FRNDINT","D9 FC","Valid","Valid","Valid","","","","","","","Round ST(0) to an integer."
"FRSTOR m94/108byte","DD /4","Valid","Valid","Valid","","","","","","","Load FPU state from m94byte or m108byte.FRSTOR—Restore x87 FPU State Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used."
"FSAVE m94/108byte","9B DD /6","Valid","Valid","Valid","","","","","","","Store FPU state to m94byte or m108byte after checking for pending unmasked floating-point exceptions. Then re-initialize the FPU."
"FNSAVE m94/108byte","DD /6","Valid","Valid","Valid","","","","","","","Store FPU environment to m94byte or m108byte without checking for pending unmasked floating- point exceptions. Then re-initialize the FPU."
"FSCALE","D9 FD","Valid","Valid","Valid","","","","","","","Scale ST(0) by ST(1)."
"FSIN","D9 FE","Valid","Valid","Valid","","","","","","","Replace ST(0) with the approximate of its sine."
"FSINCOS","D9 FB","Valid","Valid","Valid","","","","","","","Compute the sine and cosine of ST(0); replace ST(0) with the approximate sine, and push the approximate cosine onto the register stack."
"FSQRT","D9 FA","Valid","Valid","Valid","","","","","","","Computes square root of ST(0) and stores the result in ST(0)."
"FST m32fp","D9 /2","Valid","Valid","Valid","","","","","","","Copy ST(0) to m32fp."
"FST m64fp","DD /2","Valid","Valid","Valid","","","","","","","Copy ST(0) to m64fp."
"FST ST(i)","DD D0+i","Valid","Valid","Valid","","","","","","","Copy ST(0) to ST(i)."
"FSTP m32fp","D9 /3","Valid","Valid","Valid","","","","","","","Copy ST(0) to m32fp and pop register stack."
"FSTP m64fp","DD /3","Valid","Valid","Valid","","","","","","","Copy ST(0) to m64fp and pop register stack."
"FSTP m80fp","DB /7","Valid","Valid","Valid","","","","","","","Copy ST(0) to m80fp and pop register stack."
"FSTP ST(i)","DD D8+i","Valid","Valid","Valid","","","","","","","Copy ST(0) to ST(i) and pop register stack.FST/FSTP—Store Floating Point Value Floating-Point Exceptions #IS Stack underflow occurred. #IA If destination result is an SNaN value or unsupported format, except when the destination format is in double extended-precision floating-point format. #U Result is too small for the destination format. #O Result is too large for the destination format. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used."
"FSTCW m2byte","9B D9 /7","Valid","Valid","Valid","","","","","","","Store FPU control word to m2byte after checking for pending unmasked floating-point exceptions."
"FNSTCW m2byte","D9 /7","Valid","Valid","Valid","","","","","","","Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions."
"FSTENV m14/28byte","9B D9 /6","Valid","Valid","Valid","","","","","","","Store FPU environment to m14byte or m28byte after checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions."
"FNSTENV m14/28byte","D9 /6","Valid","Valid","Valid","","","","","","","Store FPU environment to m14byte or m28byte without checking for pending unmasked floating- point exceptions. Then mask all floating- point exceptions."
"FSTSW m2byte","9B DD /7","Valid","Valid","Valid","","","","","","","Store FPU status word at m2byte after checking for pending unmasked floating-point exceptions."
"FSTSW AX","9B DF E0","Valid","Valid","Valid","","","","","","","Store FPU status word in AX register after checking for pending unmasked floating-point exceptions."
"FNSTSW m2byte","DD /7","Valid","Valid","Valid","","","","","","","Store FPU status word at m2byte without checking for pending unmasked floating-point exceptions."
"FNSTSW AX","DF E0","Valid","Valid","Valid","","","","","","","Store FPU status word in AX register without checking for pending unmasked floating-point exceptions."
"FSUB m32fp","D8 /4","Valid","Valid","Valid","","","","","","","Subtract m32fp from ST(0) and store result in ST(0)."
"FSUB m64fp","DC /4","Valid","Valid","Valid","","","","","","","Subtract m64fp from ST(0) and store result in ST(0)."
"FSUB ST(0), ST(i)","D8 E0+i","Valid","Valid","Valid","","","","","","","Subtract ST(i) from ST(0) and store result in ST(0)."
"FSUB ST(i), ST(0)","DC E8+i","Valid","Valid","Valid","","","","","","","Subtract ST(0) from ST(i) and store result in ST(i)."
"FSUBP ST(i), ST(0)","DE E8+i","Valid","Valid","Valid","","","","","","","Subtract ST(0) from ST(i), store result in ST(i), and pop register stack."
"FSUBP","DE E9","Valid","Valid","Valid","","","","","","","Subtract ST(0) from ST(1), store result in ST(1), and pop register stack."
"FISUB m32int","DA /4","Valid","Valid","Valid","","","","","","","Subtract m32int from ST(0) and store result in ST(0)."
"FISUB m16int","DE /4","Valid","Valid","Valid","","","","","","","Subtract m16int from ST(0) and store result in ST(0).FSUB/FSUBP/FISUB—Subtract This instruction’s operation is the same in non-64-bit modes and 64-bit mode."
"FSUBR m32fp","D8 /5","Valid","Valid","Valid","","","","","","","Subtract ST(0) from m32fp and store result in ST(0)."
"FSUBR m64fp","DC /5","Valid","Valid","Valid","","","","","","","Subtract ST(0) from m64fp and store result in ST(0)."
"FSUBR ST(0), ST(i)","D8 E8+i","Valid","Valid","Valid","","","","","","","Subtract ST(0) from ST(i) and store result in ST(0)."
"FSUBR ST(i), ST(0)","DC E0+i","Valid","Valid","Valid","","","","","","","Subtract ST(i) from ST(0) and store result in ST(i)."
"FSUBRP ST(i), ST(0)","DE E0+i","Valid","Valid","Valid","","","","","","","Subtract ST(i) from ST(0), store result in ST(i), and pop register stack."
"FSUBRP","DE E1","Valid","Valid","Valid","","","","","","","Subtract ST(1) from ST(0), store result in ST(1), and pop register stack."
"FISUBR m32int","DA /5","Valid","Valid","Valid","","","","","","","Subtract ST(0) from m32int and store result in ST(0)."
"FISUBR m16int","DE /5","Valid","Valid","Valid","","","","","","","Subtract ST(0) from m16int and store result in ST(0).FSUBR/FSUBRP/FISUBR—Reverse Subtract This instruction’s operation is the same in non-64-bit modes and 64-bit mode."
"FTST","D9 E4","Valid","Valid","Valid","","","","","","","Compare ST(0) with 0.0."
"FUCOM ST(i)","DD E0+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i)."
"FUCOM","DD E1","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(1)."
"FUCOMP ST(i)","DD E8+i","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(i) and pop register stack."
"FUCOMP","DD E9","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(1) and pop register stack."
"FUCOMPP","DA E9","Valid","Valid","Valid","","","","","","","Compare ST(0) with ST(1) and pop register stack twice."
"FXAM","D9 E5","Valid","Valid","Valid","","","","","","","Classify value or number in ST(0)."
"FXCH ST(i)","D9 C8+i","Valid","Valid","Valid","","","","","","","Exchange the contents of ST(0) and ST(i)."
"FXCH","D9 C9","Valid","Valid","Valid","","","","","","","Exchange the contents of ST(0) and ST(1).FXCH—Exchange Register Contents Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode."
"FXRSTOR m512byte","NP 0F AE /1","Valid","Valid","Valid","","ModRM:r/m (r)","NA","NA","NA","","Restore the x87 FPU, MMX, XMM, and MXCSR register state from m512byte."
"FXRSTOR64 m512byte","NP REX.W + 0F AE /1","Valid","Invalid","Invalid","","ModRM:r/m (r)","NA","NA","NA","","Restore the x87 FPU, MMX, XMM, and MXCSR register state from m512byte."
"FXSAVE m512byte","NP 0F AE /0","Valid","Valid","Valid","","","","","","","Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte."
"FXSAVE64 m512byte","NP REX.W + 0F AE /0","Valid","Invalid","Invalid","","","","","","","Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte."
FXTRACT,D9 F4,Valid,Valid,Valid,,,,,,,"Separate value in ST(0) into exponent and significand, store exponent in ST(0), and push the significand onto the register stack."
"FYL2X","D9 F1","Valid","Valid","Valid","","","","","","","Replace ST(1) with (ST(1) ∗ log ST(0)) and pop the register stack."
"FYL2XP1","D9 F9","Valid","Valid","Valid","","","","","","","Replace ST(1) with ST(1) ∗ log (ST(0) + 1.0) and pop the register stack."
"HADDPD xmm1, xmm2/m128","66 0F 7C /r","Valid","Valid","Invalid","SSE3","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Horizontal add packed double-precision floating-point values from xmm2/m128 to xmm1."
"VHADDPD xmm1,xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG 7C /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal add packed double-precision floating-point values from xmm2 and xmm3/mem."
"VHADDPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG 7C /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal add packed double-precision floating-point values from ymm2 and ymm3/mem."
"HADDPS xmm1, xmm2/m128","F2 0F 7C /r","Valid","Valid","Invalid","SSE3","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Horizontal add packed single-precision floating-point values from xmm2/m128 to xmm1."
"VHADDPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.F2.0F.WIG 7C /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal add packed single-precision floating-point values from xmm2 and xmm3/mem."
"VHADDPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.F2.0F.WIG 7C /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal add packed single-precision floating-point values from ymm2 and ymm3/mem."
"HLT","F4","Valid","Valid","Valid","","NA","NA","NA","NA","","Halt"
"HSUBPD xmm1, xmm2/m128","66 0F 7D /r","Valid","Valid","Invalid","SSE3","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Horizontal subtract packed double-precision floating-point values from xmm2/m128 to xmm1."
"VHSUBPD xmm1,xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG 7D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal subtract packed double-precision floating-point values from xmm2 and xmm3/mem."
"VHSUBPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG 7D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal subtract packed double-precision floating-point values from ymm2 and ymm3/mem."
"HSUBPS xmm1, xmm2/m128","F2 0F 7D /r","Valid","Valid","Invalid","SSE3","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Horizontal subtract packed single-precision floating-point values from xmm2/m128 to xmm1."
"VHSUBPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.F2.0F.WIG 7D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal subtract packed single-precision floating-point values from xmm2 and xmm3/mem."
"VHSUBPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.F2.0F.WIG 7D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r)","NA","","Horizontal subtract packed single-precision floating-point values from ymm2 and ymm3/mem."
"IDIV r/m8","F6 /7","Valid","Valid","Valid","","ModRM:r/m (r)","NA","NA","NA","","Signed divide AX by r/m8, with result stored in: AL ↠Quotient, AH ↠Remainder."
"IDIV r/m8","REX + F6 /7","Valid","Invalid","Invalid","","ModRM:r/m (r)","NA","NA","NA","","Signed divide AX by r/m8, with result stored in AL ↠Quotient, AH ↠Remainder."
"IDIV r/m16","F7 /7","Valid","Valid","Valid","","ModRM:r/m (r)","NA","NA","NA","","Signed divide DX:AX by r/m16, with result stored in AX ↠Quotient, DX ↠Remainder."
"IDIV r/m32","F7 /7","Valid","Valid","Valid","","ModRM:r/m (r)","NA","NA","NA","","Signed divide EDX:EAX by r/m32, with result stored in EAX ↠Quotient, EDX ↠Remainder."
"IDIV r/m64","REX.W + F7 /7","Valid","Invalid","Invalid","","ModRM:r/m (r)","NA","NA","NA","","Signed divide RDX:RAX by r/m64, with result stored in RAX ↠Quotient, RDX ↠Remainder."
"IMUL r/m8","F6 /5","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","AX↠AL ∗ r/m byte."
"IMUL r/m16","F7 /5","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","DX:AX ↠AX ∗ r/m word."
"IMUL r/m32","F7 /5","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","EDX:EAX ↠EAX ∗ r/m32."
"IMUL r/m64","REX.W + F7 /5","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","NA","NA","NA","","RDX:RAX ↠RAX ∗ r/m64."
"IMUL r16, r/m16","0F AF /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","word register ↠word register ∗ r/m16."
"IMUL r32, r/m32","0F AF /r","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","doubleword register ↠doubleword register ∗ r/m32."
"IMUL r64, r/m64","REX.W + 0F AF /r","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","","Quadword register ↠Quadword register ∗ r/m64."
"IMUL r16, r/m16, imm8","6B /r ib","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","imm8/16/32","NA","","word register ↠r/m16 ∗ sign-extended immediate byte."
"IMUL r32, r/m32, imm8","6B /r ib","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","imm8/16/32","NA","","doubleword register ↠r/m32 ∗ sign- extended immediate byte."
"IMUL r64, r/m64, imm8","REX.W + 6B /r ib","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","imm8/16/32","NA","","Quadword register ↠r/m64 ∗ sign-extended immediate byte."
"IMUL r16, r/m16, imm16","69 /r iw","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","imm8/16/32","NA","","word register ↠r/m16 ∗ immediate word."
"IMUL r32, r/m32, imm32","69 /r id","Valid","Valid","Valid","","ModRM:reg (r, w)","ModRM:r/m (r)","imm8/16/32","NA","","doubleword register ↠r/m32 ∗ immediate doubleword."
"IMUL r64, r/m64, imm32","REX.W + 69 /r id","Valid","Invalid","Invalid","","ModRM:reg (r, w)","ModRM:r/m (r)","imm8/16/32","NA","","Quadword register ↠r/m64 ∗ immediate doubleword."
"IN AL, imm8","E4 ib","Valid","Valid","Valid","","","","","","","Input byte from imm8 I/O port address into AL."
"IN AX, imm8","E5 ib","Valid","Valid","Valid","","","","","","","Input word from imm8 I/O port address into AX."
"IN EAX, imm8","E5 ib","Valid","Valid","Valid","","","","","","","Input dword from imm8 I/O port address into EAX."
"IN AL,DX","EC","Valid","Valid","Valid","","","","","","","Input byte from I/O port in DX into AL."
"IN AX,DX","ED","Valid","Valid","Valid","","","","","","","Input word from I/O port in DX into AX."
"IN EAX,DX","ED","Valid","Valid","Valid","","","","","","","Input doubleword from I/O port in DX into EAX."
"INC r/m8","FE /0","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Increment r/m byte by 1."
"INC r/m8","REX + FE /0","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","NA","NA","NA","","Increment r/m byte by 1."
"INC r/m16","FF /0","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Increment r/m word by 1."
"INC r/m32","FF /0","Valid","Valid","Valid","","ModRM:r/m (r, w)","NA","NA","NA","","Increment r/m doubleword by 1."
"INC r/m64","REX.W + FF /0","Valid","Invalid","Invalid","","ModRM:r/m (r, w)","NA","NA","NA","","Increment r/m quadword by 1."
"INC r16","40 +rw","Invalid","Valid","Valid","","opcode +rd (r, w)","NA","NA","NA","","Increment word register by 1."
"INC r32","40 +rd","Invalid","Valid","Valid","","opcode +rd (r, w)","NA","NA","NA","","Increment doubleword register by 1."
"INS m8, DX","6C","Valid","Valid","Valid","","NA","NA","NA","NA","","Input byte from I/O port specified in DX into memory location specified in ES:(E)DI or RDI."
"INS m16, DX","6D","Valid","Valid","Valid","","NA","NA","NA","NA","","Input word from I/O port specified in DX into memory location specified in ES:(E)DI or RDI."
"INS m32, DX","6D","Valid","Valid","Valid","","NA","NA","NA","NA","","Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI or RDI."
"INSB","6C","Valid","Valid","Valid","","NA","NA","NA","NA","","Input byte from I/O port specified in DX into memory location specified with ES:(E)DI or RDI."
"INSW","6D","Valid","Valid","Valid","","NA","NA","NA","NA","","Input word from I/O port specified in DX into memory location specified in ES:(E)DI or RDI."
"INSD","6D","Valid","Valid","Valid","","NA","NA","NA","NA","","Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI or RDI."
"INSERTPS xmm1, xmm2/m32, imm8","66 0F 3A 21 /r ib","Valid","Valid","Invalid","SSE4_1","ModRM:reg (r, w)","ModRM:r/m (r)","Imm8","NA","NA","Insert a single-precision floating-point value selected by imm8 from xmm2/m32 into xmm1 at the specified destination element specified by imm8 and zero out destination elements in xmm1 as indicated in imm8."
"VINSERTPS xmm1, xmm2, xmm3/m32, imm8","VEX.NDS.128.66.0F3A.WIG 21 /r ib","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","Imm8","NA","Insert a single-precision floating-point value selected by imm8 from xmm3/m32 and merge with values in xmm2 at the specified destination element specified by imm8 and write out the result and zero out destination elements in xmm1 as indicated in imm8."
"VINSERTPS xmm1, xmm2, xmm3/m32, imm8","EVEX.NDS.128.66.0F3A.W0 21 /r ib","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","Imm8","Tuple1 Scalar","Insert a single-precision floating-point value selected by imm8 from xmm3/m32 and merge with values in xmm2 at the specified destination element specified by imm8 and write out the result and zero out destination elements in xmm1 as indicated in imm8."
"INT 3","CC","Valid","Valid","Valid","","NA","NA","NA","NA","","Interrupt 3—trap to debugger. CD ib INT imm8 I Valid Valid Interrupt vector specified by immediate byte."
"INTO","CE","Invalid","Valid","Valid","","NA","NA","NA","NA","","Interrupt 4—if overflow flag is 1."
"INVD","0F 08","Valid","Valid","Valid","","NA","NA","NA","NA","","Flush internal caches; initiate flushing of external caches."
"INVLPG m","0F 01/7","Valid","Valid","Valid","","ModRM:r/m (r)","NA","NA","NA","","Invalidate TLB entries for page containing m."
"INVPCID r32, m128","66 0F 38 82 /r","Invalid","Valid","Invalid","INVPCID","ModRM:reg (R)","ModRM:r/m (R)","NA","NA","","Invalidates entries in the TLBs and paging-structure caches based on invalidation type in r32 and descrip-tor in m128."
"INVPCID r64, m128","66 0F 38 82 /r","Valid","Invalid","Invalid","INVPCID","ModRM:reg (R)","ModRM:r/m (R)","NA","NA","","Invalidates entries in the TLBs and paging-structure caches based on invalidation type in r64 and descrip-tor in m128."
"IRET","CF","Valid","Valid","Valid","","NA","NA","NA","NA","","Interrupt return (16-bit operand size)."
"IRETD","CF","Valid","Valid","Valid","","NA","NA","NA","NA","","Interrupt return (32-bit operand size)."
"IRETQ","REX.W + CF","Valid","Invalid","Invalid","","NA","NA","NA","NA","","Interrupt return (64-bit operand size)."
"JA rel8","77 cb","Valid","Valid","Valid","","","","","","","Jump short if above (CF=0 and ZF=0)."
"JAE rel8","73 cb","Valid","Valid","Valid","","","","","","","Jump short if above or equal (CF=0)."
"JB rel8","72 cb","Valid","Valid","Valid","","","","","","","Jump short if below (CF=1)."
"JBE rel8","76 cb","Valid","Valid","Valid","","","","","","","Jump short if below or equal (CF=1 or ZF=1)."
"JC rel8","72 cb","Valid","Valid","Valid","","","","","","","Jump short if carry (CF=1)."
"JCXZ rel8","E3 cb","Invalid","Valid","Valid","","","","","","","Jump short if CX register is 0."
"JECXZ rel8","E3 cb","Valid","Valid","Valid","","","","","","","Jump short if ECX register is 0."
"JRCXZ rel8","E3 cb","Valid","Invalid","Invalid","","","","","","","Jump short if RCX register is 0."
"JE rel8","74 cb","Valid","Valid","Valid","","","","","","","Jump short if equal (ZF=1)."
"JG rel8","7F cb","Valid","Valid","Valid","","","","","","","Jump short if greater (ZF=0 and SF=OF)."
"JGE rel8","7D cb","Valid","Valid","Valid","","","","","","","Jump short if greater or equal (SF=OF)."
"JL rel8","7C cb","Valid","Valid","Valid","","","","","","","Jump short if less (SF≠OF)."
"JLE rel8","7E cb","Valid","Valid","Valid","","","","","","","Jump short if less or equal (ZF=1 or SF≠OF)."
"JNA rel8","76 cb","Valid","Valid","Valid","","","","","","","Jump short if not above (CF=1 or ZF=1)."
"JNAE rel8","72 cb","Valid","Valid","Valid","","","","","","","Jump short if not above or equal (CF=1)."
"JNB rel8","73 cb","Valid","Valid","Valid","","","","","","","Jump short if not below (CF=0)."
"JNBE rel8","77 cb","Valid","Valid","Valid","","","","","","","Jump short if not below or equal (CF=0 and ZF=0)."
"JNC rel8","73 cb","Valid","Valid","Valid","","","","","","","Jump short if not carry (CF=0)."
"JNE rel8","75 cb","Valid","Valid","Valid","","","","","","","Jump short if not equal (ZF=0)."
"JNG rel8","7E cb","Valid","Valid","Valid","","","","","","","Jump short if not greater (ZF=1 or SF≠OF)."
"JNGE rel8","7C cb","Valid","Valid","Valid","","","","","","","Jump short if not greater or equal (SF≠OF)."
"JNL rel8","7D cb","Valid","Valid","Valid","","","","","","","Jump short if not less (SF=OF)."
"JNLE rel8","7F cb","Valid","Valid","Valid","","","","","","","Jump short if not less or equal (ZF=0 and SF=OF)."
"JNO rel8","71 cb","Valid","Valid","Valid","","","","","","","Jump short if not overflow (OF=0)."
"JNP rel8","7B cb","Valid","Valid","Valid","","","","","","","Jump short if not parity (PF=0)."
"JNS rel8","79 cb","Valid","Valid","Valid","","","","","","","Jump short if not sign (SF=0)."
"JNZ rel8","75 cb","Valid","Valid","Valid","","","","","","","Jump short if not zero (ZF=0)."
"JO rel8","70 cb","Valid","Valid","Valid","","","","","","","Jump short if overflow (OF=1)."
"JP rel8","7A cb","Valid","Valid","Valid","","","","","","","Jump short if parity (PF=1)."
"JPE rel8","7A cb","Valid","Valid","Valid","","","","","","","Jump short if parity even (PF=1)."
"JPO rel8","7B cb","Valid","Valid","Valid","","","","","","","Jump short if parity odd (PF=0)."
"JS rel8","78 cb","Valid","Valid","Valid","","","","","","","Jump short if sign (SF=1)."
"JZ rel8","74 cb","Valid","Valid","Valid","","","","","","","Jump short if zero (ZF = 1)."
"JA rel16","0F 87 cw","Invalid","Valid","Valid","","","","","","","Jump near if above (CF=0 and ZF=0). Not supported in 64-bit mode."
"JA rel32","0F 87 cd","Valid","Valid","Valid","","","","","","","Jump near if above (CF=0 and ZF=0)."
"JAE rel16","0F 83 cw","Invalid","Valid","Valid","","","","","","","Jump near if above or equal (CF=0). Not supported in 64-bit mode.Jcc—Jump if Condition Is Met"
"JAE rel32","0F 83 cd","Valid","Valid","Valid","","","","","","","Jump near if above or equal (CF=0)."
"JB rel16","0F 82 cw","Invalid","Valid","Valid","","","","","","","Jump near if below (CF=1). Not supported in 64-bit mode."
"JB rel32","0F 82 cd","Valid","Valid","Valid","","","","","","","Jump near if below (CF=1)."
"JBE rel16","0F 86 cw","Invalid","Valid","Valid","","","","","","","Jump near if below or equal (CF=1 or ZF=1). Not supported in 64-bit mode."
"JBE rel32","0F 86 cd","Valid","Valid","Valid","","","","","","","Jump near if below or equal (CF=1 or ZF=1)."
"JC rel16","0F 82 cw","Invalid","Valid","Valid","","","","","","","Jump near if carry (CF=1). Not supported in 64-bit mode."
"JC rel32","0F 82 cd","Valid","Valid","Valid","","","","","","","Jump near if carry (CF=1)."
"JE rel16","0F 84 cw","Invalid","Valid","Valid","","","","","","","Jump near if equal (ZF=1). Not supported in 64-bit mode."
"JE rel32","0F 84 cd","Valid","Valid","Valid","","","","","","","Jump near if equal (ZF=1)."
"JZ rel16","0F 84 cw","Invalid","Valid","Valid","","","","","","","Jump near if 0 (ZF=1). Not supported in 64-bit mode."
"JZ rel32","0F 84 cd","Valid","Valid","Valid","","","","","","","Jump near if 0 (ZF=1)."
"JG rel16","0F 8F cw","Invalid","Valid","Valid","","","","","","","Jump near if greater (ZF=0 and SF=OF). Not supported in 64-bit mode."
"JG rel32","0F 8F cd","Valid","Valid","Valid","","","","","","","Jump near if greater (ZF=0 and SF=OF)."
"JGE rel16","0F 8D cw","Invalid","Valid","Valid","","","","","","","Jump near if greater or equal (SF=OF). Not supported in 64-bit mode."
"JGE rel32","0F 8D cd","Valid","Valid","Valid","","","","","","","Jump near if greater or equal (SF=OF)."
"JL rel16","0F 8C cw","Invalid","Valid","Valid","","","","","","","Jump near if less (SF≠OF). Not supported in 64-bit mode."
"JL rel32","0F 8C cd","Valid","Valid","Valid","","","","","","","Jump near if less (SF≠OF)."
"JLE rel16","0F 8E cw","Invalid","Valid","Valid","","","","","","","Jump near if less or equal (ZF=1 or SF≠OF). Not supported in 64-bit mode."
"JLE rel32","0F 8E cd","Valid","Valid","Valid","","","","","","","Jump near if less or equal (ZF=1 or SF≠OF)."
"JNA rel16","0F 86 cw","Invalid","Valid","Valid","","","","","","","Jump near if not above (CF=1 or ZF=1). Not supported in 64-bit mode."
"JNA rel32","0F 86 cd","Valid","Valid","Valid","","","","","","","Jump near if not above (CF=1 or ZF=1)."
"JNAE rel16","0F 82 cw","Invalid","Valid","Valid","","","","","","","Jump near if not above or equal (CF=1). Not supported in 64-bit mode."
"JNAE rel32","0F 82 cd","Valid","Valid","Valid","","","","","","","Jump near if not above or equal (CF=1)."
"JNB rel16","0F 83 cw","Invalid","Valid","Valid","","","","","","","Jump near if not below (CF=0). Not supported in 64-bit mode."
"JNB rel32","0F 83 cd","Valid","Valid","Valid","","","","","","","Jump near if not below (CF=0)."
"JNBE rel16","0F 87 cw","Invalid","Valid","Valid","","","","","","","Jump near if not below or equal (CF=0 and ZF=0). Not supported in 64-bit mode."
"JNBE rel32","0F 87 cd","Valid","Valid","Valid","","","","","","","Jump near if not below or equal (CF=0 and ZF=0)."
"JNC rel16","0F 83 cw","Invalid","Valid","Valid","","","","","","","Jump near if not carry (CF=0). Not supported in 64-bit mode."
"JNC rel32","0F 83 cd","Valid","Valid","Valid","","","","","","","Jump near if not carry (CF=0)."
"JNE rel16","0F 85 cw","Invalid","Valid","Valid","","","","","","","Jump near if not equal (ZF=0). Not supported in 64-bit mode."
"JNE rel32","0F 85 cd","Valid","Valid","Valid","","","","","","","Jump near if not equal (ZF=0)."
"JNG rel16","0F 8E cw","Invalid","Valid","Valid","","","","","","","Jump near if not greater (ZF=1 or SF≠OF). Not supported in 64-bit mode."
"JNG rel32","0F 8E cd","Valid","Valid","Valid","","","","","","","Jump near if not greater (ZF=1 or SF≠OF)."
"JNGE rel16","0F 8C cw","Invalid","Valid","Valid","","","","","","","Jump near if not greater or equal (SF≠OF). Not supported in 64-bit mode."
"JNGE rel32","0F 8C cd","Valid","Valid","Valid","","","","","","","Jump near if not greater or equal (SF≠OF)."
"JNL rel16","0F 8D cw","Invalid","Valid","Valid","","","","","","","Jump near if not less (SF=OF). Not supported in 64-bit mode."
"JNL rel32","0F 8D cd","Valid","Valid","Valid","","","","","","","Jump near if not less (SF=OF)."
"JNLE rel16","0F 8F cw","Invalid","Valid","Valid","","","","","","","Jump near if not less or equal (ZF=0 and SF=OF). Not supported in 64-bit mode."
"JNLE rel32","0F 8F cd","Valid","Valid","Valid","","","","","","","Jump near if not less or equal (ZF=0 and SF=OF)."
"JNO rel16","0F 81 cw","Invalid","Valid","Valid","","","","","","","Jump near if not overflow (OF=0). Not supported in 64-bit mode."
"JNO rel32","0F 81 cd","Valid","Valid","Valid","","","","","","","Jump near if not overflow (OF=0)."
"JNP rel16","0F 8B cw","Invalid","Valid","Valid","","","","","","","Jump near if not parity (PF=0). Not supported in 64-bit mode."
"JNP rel32","0F 8B cd","Valid","Valid","Valid","","","","","","","Jump near if not parity (PF=0)."
"JNS rel16","0F 89 cw","Invalid","Valid","Valid","","","","","","","Jump near if not sign (SF=0). Not supported in 64-bit mode."
"JNS rel32","0F 89 cd","Valid","Valid","Valid","","","","","","","Jump near if not sign (SF=0)."
"JNZ rel16","0F 85 cw","Invalid","Valid","Valid","","","","","","","Jump near if not zero (ZF=0). Not supported in 64-bit mode."
"JNZ rel32","0F 85 cd","Valid","Valid","Valid","","","","","","","Jump near if not zero (ZF=0)."
"JO rel16","0F 80 cw","Invalid","Valid","Valid","","","","","","","Jump near if overflow (OF=1). Not supported in 64-bit mode."
"JO rel32","0F 80 cd","Valid","Valid","Valid","","","","","","","Jump near if overflow (OF=1)."
"JP rel16","0F 8A cw","Invalid","Valid","Valid","","","","","","","Jump near if parity (PF=1). Not supported in 64-bit mode."
"JP rel32","0F 8A cd","Valid","Valid","Valid","","","","","","","Jump near if parity (PF=1)."
"JPE rel16","0F 8A cw","Invalid","Valid","Valid","","","","","","","Jump near if parity even (PF=1). Not supported in 64-bit mode."
"JPE rel32","0F 8A cd","Valid","Valid","Valid","","","","","","","Jump near if parity even (PF=1)."
"JPO rel16","0F 8B cw","Invalid","Valid","Valid","","","","","","","Jump near if parity odd (PF=0). Not supported in 64-bit mode."
"JPO rel32","0F 8B cd","Valid","Valid","Valid","","","","","","","Jump near if parity odd (PF=0)."
"JS rel16","0F 88 cw","Invalid","Valid","Valid","","","","","","","Jump near if sign (SF=1). Not supported in 64- bit mode."
"JMP rel8","EB cb","Valid","Valid","Valid","","","","","","","Jump short, RIP = RIP + 8-bit displacement sign extended to 64-bits"
"JMP rel16","E9 cw","Invalid","Valid","Valid","","","","","","","Jump near, relative, displacement relative to next instruction. Not supported in 64-bit mode."
"JMP rel32","E9 cd","Valid","Valid","Invalid","","","","","","","Jump near, relative, RIP = RIP + 32-bit displacement sign extended to 64-bits"
"JMP r/m16","FF /4","Invalid","Valid","Valid","","","","","","","Jump near, absolute indirect, address = zero- extended r/m16. Not supported in 64-bit mode."
"JMP r/m32","FF /4","Invalid","Valid","Invalid","","","","","","","Jump near, absolute indirect, address given in r/m32. Not supported in 64-bit mode."
"JMP r/m64","FF /4","Valid","Invalid","Invalid","","","","","","","Jump near, absolute indirect, RIP = 64-Bit offset from register or memory"
"JMP ptr16:16","EA cd","Invalid","Valid","Valid","","","","","","","Jump far, absolute, address given in operand"
"JMP ptr16:32","EA cp","Invalid","Valid","Invalid","","","","","","","Jump far, absolute, address given in operand"
"JMP m16:16","FF /5","Valid","Valid","Valid","","","","","","","Jump far, absolute indirect, address given in m16:16"
"JMP m16:32","FF /5","Valid","Valid","Invalid","","","","","","","Jump far, absolute indirect, address given in m16:32."
"JMP m16:64","REX.W + FF /5","Valid","Invalid","Invalid","","","","","","","Jump far, absolute indirect, address given in m16:64."
"KADDW k1, k2, k3","VEX.L1.0F.W0 4A /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Add 16 bits masks in k2 and k3 and place result in k1."
"KADDB k1, k2, k3","VEX.L1.66.0F.W0 4A /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Add 8 bits masks in k2 and k3 and place result in k1."
"KADDQ k1, k2, k3","VEX.L1.0F.W1 4A /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Add 64 bits masks in k2 and k3 and place result in k1."
"KADDD k1, k2, k3","VEX.L1.66.0F.W1 4A /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Add 32 bits masks in k2 and k3 and place result in k1."
"KANDNW k1, k2, k3","VEX.NDS.L1.0F.W0 42 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND NOT 16 bits masks k2 and k3 and place result in k1."
"KANDNB k1, k2, k3","VEX.L1.66.0F.W0 42 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1."
"KANDNQ k1, k2, k3","VEX.L1.0F.W1 42 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND NOT 64 bits masks k2 and k3 and place result in k1."
"KANDND k1, k2, k3","VEX.L1.66.0F.W1 42 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND NOT 32 bits masks k2 and k3 and place result in k1."
"KANDW k1, k2, k3","VEX.NDS.L1.0F.W0 41 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND 16 bits masks k2 and k3 and place result in k1."
"KANDB k1, k2, k3","VEX.L1.66.0F.W0 41 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND 8 bits masks k2 and k3 and place result in k1."
"KANDQ k1, k2, k3","VEX.L1.0F.W1 41 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND 64 bits masks k2 and k3 and place result in k1."
"KANDD k1, k2, k3","VEX.L1.66.0F.W1 41 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise AND 32 bits masks k2 and k3 and place result in k1."
"KMOVW k1, k2/m16","VEX.L0.0F.W0 90 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r)","","","","Move 16 bits mask from k2/m16 and store the result in k1."
"KMOVB k1, k2/m8","VEX.L0.66.0F.W0 90 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r)","","","","Move 8 bits mask from k2/m8 and store the result in k1."
"KMOVQ k1, k2/m64","VEX.L0.0F.W1 90 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r)","","","","Move 64 bits mask from k2/m64 and store the result in k1."
"KMOVD k1, k2/m32","VEX.L0.66.0F.W1 90 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r)","","","","Move 32 bits mask from k2/m32 and store the result in k1."
"KMOVW m16, k1","VEX.L0.0F.W0 91 /r","Valid","Valid","Invalid","AVX512F","ModRM:r/m (w, ModRM:[7:6] must not be 11b)","ModRM:reg (r)","","","","Move 16 bits mask from k1 and store the result in m16."
"KMOVB m8, k1","VEX.L0.66.0F.W0 91 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:r/m (w, ModRM:[7:6] must not be 11b)","ModRM:reg (r)","","","","Move 8 bits mask from k1 and store the result in m8."
"KMOVQ m64, k1","VEX.L0.0F.W1 91 /r","Valid","Valid","Invalid","AVX512BW","ModRM:r/m (w, ModRM:[7:6] must not be 11b)","ModRM:reg (r)","","","","Move 64 bits mask from k1 and store the result in m64."
"KMOVD m32, k1","VEX.L0.66.0F.W1 91 /r","Valid","Valid","Invalid","AVX512BW","ModRM:r/m (w, ModRM:[7:6] must not be 11b)","ModRM:reg (r)","","","","Move 32 bits mask from k1 and store the result in m32."
"KMOVW k1, r32","VEX.L0.0F.W0 92 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 16 bits mask from r32 to k1."
"KMOVB k1, r32","VEX.L0.66.0F.W0 92 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 8 bits mask from r32 to k1."
"KMOVQ k1, r64","VEX.L0.F2.0F.W1 92 /r","Valid","Invalid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 64 bits mask from r64 to k1."
"KMOVD k1, r32","VEX.L0.F2.0F.W0 92 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 32 bits mask from r32 to k1."
"KMOVW r32, k1","VEX.L0.0F.W0 93 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 16 bits mask from k1 to r32."
"KMOVB r32, k1","VEX.L0.66.0F.W0 93 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 8 bits mask from k1 to r32."
"KMOVQ r64, k1","VEX.L0.F2.0F.W1 93 /r","Valid","Invalid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 64 bits mask from k1 to r64."
"KMOVD r32, k1","VEX.L0.F2.0F.W0 93 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Move 32 bits mask from k1 to r32."
"KNOTW k1, k2","VEX.L0.0F.W0 44 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise NOT of 16 bits mask k2."
"KNOTB k1, k2","VEX.L0.66.0F.W0 44 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise NOT of 8 bits mask k2."
"KNOTQ k1, k2","VEX.L0.0F.W1 44 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise NOT of 64 bits mask k2."
"KNOTD k1, k2","VEX.L0.66.0F.W1 44 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise NOT of 32 bits mask k2."
"KORTESTW k1, k2","VEX.L0.0F.W0 98 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly."
"KORTESTB k1, k2","VEX.L0.66.0F.W0 98 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly."
"KORTESTQ k1, k2","VEX.L0.0F.W1 98 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly."
"KORTESTD k1, k2","VEX.L0.66.0F.W1 98 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Bitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly."
"KORW k1, k2, k3","VEX.NDS.L1.0F.W0 45 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise OR 16 bits masks k2 and k3 and place result in k1."
"KORB k1, k2, k3","VEX.L1.66.0F.W0 45 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise OR 8 bits masks k2 and k3 and place result in k1."
"KORQ k1, k2, k3","VEX.L1.0F.W1 45 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise OR 64 bits masks k2 and k3 and place result in k1."
"KORD k1, k2, k3","VEX.L1.66.0F.W1 45 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise OR 32 bits masks k2 and k3 and place result in k1."
"KSHIFTLW k1, k2, imm8","VEX.L0.66.0F3A.W1 32 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift left 16 bits in k2 by immediate and write result in k1."
"KSHIFTLB k1, k2, imm8","VEX.L0.66.0F3A.W0 32 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift left 8 bits in k2 by immediate and write result in k1."
"KSHIFTLQ k1, k2, imm8","VEX.L0.66.0F3A.W1 33 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift left 64 bits in k2 by immediate and write result in k1."
"KSHIFTLD k1, k2, imm8","VEX.L0.66.0F3A.W0 33 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift left 32 bits in k2 by immediate and write result in k1."
"KSHIFTRW k1, k2, imm8","VEX.L0.66.0F3A.W1 30 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift right 16 bits in k2 by immediate and write result in k1."
"KSHIFTRB k1, k2, imm8","VEX.L0.66.0F3A.W0 30 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift right 8 bits in k2 by immediate and write result in k1."
"KSHIFTRQ k1, k2, imm8","VEX.L0.66.0F3A.W1 31 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift right 64 bits in k2 by immediate and write result in k1."
"KSHIFTRD k1, k2, imm8","VEX.L0.66.0F3A.W0 31 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","Imm8","","","Shift right 32 bits in k2 by immediate and write result in k1."
"KTESTW k1, k2","VEX.L0.0F.W0 99 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask register sources."
"KTESTB k1, k2","VEX.L0.66.0F.W0 99 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask register sources."
"KTESTQ k1, k2","VEX.L0.0F.W1 99 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask register sources."
"KTESTD k1, k2","VEX.L0.66.0F.W1 99 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","","Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask register sources."
"KUNPCKBW k1, k2, k3","VEX.NDS.L1.66.0F.W0 4B /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Unpack and interleave 8 bits masks in k2 and k3 and write word result in k1."
"KUNPCKWD k1, k2, k3","VEX.NDS.L1.0F.W0 4B /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Unpack and interleave 16 bits in k2 and k3 and write double-word result in k1."
"KUNPCKDQ k1, k2, k3","VEX.NDS.L1.0F.W1 4B /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Unpack and interleave 32 bits masks in k2 and k3 and write quadword result in k1."
"KXNORW k1, k2, k3","VEX.NDS.L1.0F.W0 46 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XNOR 16 bits masks k2 and k3 and place result in k1."
"KXNORB k1, k2, k3","VEX.L1.66.0F.W0 46 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XNOR 8 bits masks k2 and k3 and place result in k1."
"KXNORQ k1, k2, k3","VEX.L1.0F.W1 46 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XNOR 64 bits masks k2 and k3 and place result in k1."
"KXNORD k1, k2, k3","VEX.L1.66.0F.W1 46 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XNOR 32 bits masks k2 and k3 and place result in k1."
"KXORW k1, k2, k3","VEX.NDS.L1.0F.W0 47 /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XOR 16 bits masks k2 and k3 and place result in k1."
"KXORB k1, k2, k3","VEX.L1.66.0F.W0 47 /r","Valid","Valid","Invalid","AVX512DQ","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XOR 8 bits masks k2 and k3 and place result in k1."
"KXORQ k1, k2, k3","VEX.L1.0F.W1 47 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XOR 64 bits masks k2 and k3 and place result in k1."
"KXORD k1, k2, k3","VEX.L1.66.0F.W1 47 /r","Valid","Valid","Invalid","AVX512BW","ModRM:reg (w)","VEX.vvvv (r)","ModRM:r/m (r, ModRM:[7:6] must be 11b)","","","Bitwise XOR 32 bits masks k2 and k3 and place result in k1."
"LAHF","9F","Invalid","Valid","Valid","","NA","NA","NA","NA","","Load: AH ↠EFLAGS(SF:ZF:0:AF:0:PF:1:CF)."
"LAR r16, r16/m16","0F 02 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","r16 ↠access rights referenced by r16/m16"
"LAR reg, r32/m16","0F 02 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","reg ↠access rights referenced by r32/m16"
"LDDQU xmm1, mem","F2 0F F0 /r","Valid","Valid","Invalid","SSE3","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load unaligned data from mem and return double quadword in xmm1."
"VLDDQU xmm1, m128","VEX.128.F2.0F.WIG F0 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load unaligned packed integer values from mem to xmm1."
"VLDDQU ymm1, m256","VEX.256.F2.0F.WIG F0 /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load unaligned packed integer values from mem to ymm1."
"LDMXCSR m32","NP 0F AE /2","Valid","Valid","Invalid","SSE","ModRM:r/m (r)","NA","NA","NA","","Load MXCSR register from m32."
"VLDMXCSR m32","VEX.LZ.0F.WIG AE /2","Valid","Valid","Invalid","AVX","ModRM:r/m (r)","NA","NA","NA","","Load MXCSR register from m32."
"LDS r16,m16:16","C5 /r","Invalid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load DS:r16 with far pointer from memory."
"LDS r32,m16:32","C5 /r","Invalid","Valid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load DS:r32 with far pointer from memory."
"LSS r16,m16:16","0F B2 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load SS:r16 with far pointer from memory."
"LSS r32,m16:32","0F B2 /r","Valid","Valid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load SS:r32 with far pointer from memory."
"LSS r64,m16:64","REX + 0F B2 /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load SS:r64 with far pointer from memory."
"LES r16,m16:16","C4 /r","Invalid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load ES:r16 with far pointer from memory."
"LES r32,m16:32","C4 /r","Invalid","Valid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load ES:r32 with far pointer from memory."
"LFS r16,m16:16","0F B4 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load FS:r16 with far pointer from memory."
"LFS r32,m16:32","0F B4 /r","Valid","Valid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load FS:r32 with far pointer from memory."
"LFS r64,m16:64","REX + 0F B4 /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load FS:r64 with far pointer from memory."
"LGS r16,m16:16","0F B5 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load GS:r16 with far pointer from memory."
"LGS r32,m16:32","0F B5 /r","Valid","Valid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load GS:r32 with far pointer from memory."
"LGS r64,m16:64","REX + 0F B5 /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load GS:r64 with far pointer from memory."
"LEA r16,m","8D /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Store effective address for m in register r16."
"LEA r32,m","8D /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Store effective address for m in register r32."
"LEA r64,m","REX.W + 8D /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Store effective address for m in register r64."
"LEAVE","C9","Valid","Valid","Valid","","NA","NA","NA","NA","","Set SP to BP, then pop BP."
"LEAVE","C9","Invalid","Valid","Valid","","NA","NA","NA","NA","","Set ESP to EBP, then pop EBP."
"LEAVE","C9","Valid","Invalid","Invalid","","NA","NA","NA","NA","","Set RSP to RBP, then pop RBP."
"LFENCE","NP 0F AE E8","Valid","Valid","Valid","","NA","NA","NA","NA","","Serializes load operations."
"LGDT m16&32","0F 01 /2","Invalid","Valid","Valid","","","","","","","Load m into GDTR."
"LIDT m16&32","0F 01 /3","Invalid","Valid","Valid","","","","","","","Load m into IDTR."
"LGDT m16&64","0F 01 /2","Valid","Invalid","Invalid","","","","","","","Load m into GDTR."
"LIDT m16&64","0F 01 /3","Valid","Invalid","Invalid","","","","","","","Load m into IDTR."
"LLDT r/m16","0F 00 /2","Valid","Valid","Valid","","","","","","","Load segment selector r/m16 into LDTR."
"LMSW r/m16","0F 01 /6","Valid","Valid","Valid","","","","","","","Loads r/m16 in machine status word of CR0."
"LOCK","F0","Valid","Valid","Valid","","NA","NA","NA","NA","","Asserts LOCK# signal for duration of the accompanying instruction."
"LODS m8","AC","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, Load byte at address DS:(E)SI into AL. For 64-bit mode load byte at address (R)SI into AL."
"LODS m16","AD","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, Load word at address DS:(E)SI into AX. For 64-bit mode load word at address (R)SI into AX."
"LODS m32","AD","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, Load dword at address DS:(E)SI into EAX. For 64-bit mode load dword at address (R)SI into EAX."
"LODS m64","REX.W + AD","Valid","Invalid","Invalid","","NA","NA","NA","NA","","Load qword at address (R)SI into RAX."
"LODSB","AC","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, Load byte at address DS:(E)SI into AL. For 64-bit mode load byte at address (R)SI into AL."
"LODSW","AD","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, Load word at address DS:(E)SI into AX. For 64-bit mode load word at address (R)SI into AX."
"LODSD","AD","Valid","Valid","Valid","","NA","NA","NA","NA","","For legacy mode, Load dword at address DS:(E)SI into EAX. For 64-bit mode load dword at address (R)SI into EAX."
"LODSQ","REX.W + AD","Valid","Invalid","Invalid","","NA","NA","NA","NA","","Load qword at address (R)SI into RAX."
"LOOP rel8","E2 cb","Valid","Valid","Valid","","","","","","","Decrement count; jump short if count ≠0."
"LOOPE rel8","E1 cb","Valid","Valid","Valid","","","","","","","Decrement count; jump short if count ≠0 and ZF = 1."
"LOOPNE rel8","E0 cb","Valid","Valid","Valid","","","","","","","Decrement count; jump short if count ≠0 and ZF = 0."
"LSL r16, r16/m16","0F 03 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load: r16 ↠segment limit, selector r16/m16."
"LSL r32, r32/m16","0F 03 /r","Valid","Valid","Valid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load: r32 ↠segment limit, selector r32/m16."
"LSL r64, r32/m16","REX.W + 0F 03 /r","Valid","Invalid","Invalid","","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Load: r64 ↠segment limit, selector r32/m16"
"LTR r/m16","0F 00 /3","Valid","Valid","Valid","","ModRM:r/m (r)","NA","NA","NA","","Load r/m16 into task register."
"LZCNT r16, r/m16","F3 0F BD /r","Valid","Valid","Valid","LZCNT","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Count the number of leading zero bits in r/m16, return result in r16."
"LZCNT r32, r/m32","F3 0F BD /r","Valid","Valid","Valid","LZCNT","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Count the number of leading zero bits in r/m32, return result in r32."
"LZCNT r64, r/m64","F3 REX.W 0F BD /r","Valid","Invalid","Invalid","LZCNT","ModRM:reg (w)","ModRM:r/m (r)","NA","NA","","Count the number of leading zero bits in r/m64, return result in r64."
"MASKMOVDQU xmm1, xmm2","66 0F F7 /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Selectively write bytes from xmm1 to memory location using the byte mask in xmm2. The default memory location is specified by DS:DI/EDI/RDI."
"VMASKMOVDQU xmm1, xmm2","VEX.128.66.0F.WIG F7 /r","Valid","Valid","Invalid","AVX","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Selectively write bytes from xmm1 to memory location using the byte mask in xmm2. The default memory location is specified by DS:DI/EDI/RDI."
"MASKMOVQ mm1, mm2","NP 0F F7 /r","Valid","Valid","Valid","","ModRM:reg (r)","ModRM:r/m (r)","NA","NA","","Selectively write bytes from mm1 to memory location using the byte mask in mm2. The default memory location is specified by DS:DI/EDI/RDI."
"MAXPD xmm1, xmm2/m128","66 0F 5F /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the maximum double-precision floating-point values between xmm1 and xmm2/m128."
"VMAXPD xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG 5F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the maximum double-precision floating-point values between xmm2 and xmm3/m128."
"VMAXPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG 5F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the maximum packed double-precision floating-point values between ymm2 and ymm3/m256."
"VMAXPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst","EVEX.NDS.128.66.0F.W1 5F /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the maximum packed double-precision floating-point values between xmm2 and xmm3/m128/m64bcst and store result in xmm1 subject to writemask k1."
"VMAXPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst","EVEX.NDS.256.66.0F.W1 5F /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the maximum packed double-precision floating-point values between ymm2 and ymm3/m256/m64bcst and store result in ymm1 subject to writemask k1."
"VMAXPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{sae}","EVEX.NDS.512.66.0F.W1 5F /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the maximum packed double-precision floating-point values between zmm2 and zmm3/m512/m64bcst and store result in zmm1 subject to writemask k1."
"MAXPS xmm1, xmm2/m128","NP 0F 5F /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the maximum single-precision floating-point values between xmm1 and xmm2/mem."
"VMAXPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.0F.WIG 5F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the maximum single-precision floating-point values between xmm2 and xmm3/mem."
"VMAXPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.0F.WIG 5F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the maximum single-precision floating-point values between ymm2 and ymm3/mem."
"VMAXPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst","EVEX.NDS.128.0F.W0 5F /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the maximum packed single-precision floating-point values between xmm2 and xmm3/m128/m32bcst and store result in xmm1 subject to writemask k1."
"VMAXPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst","EVEX.NDS.256.0F.W0 5F /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the maximum packed single-precision floating-point values between ymm2 and ymm3/m256/m32bcst and store result in ymm1 subject to writemask k1."
"VMAXPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{sae}","EVEX.NDS.512.0F.W0 5F /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the maximum packed single-precision floating-point values between zmm2 and zmm3/m512/m32bcst and store result in zmm1 subject to writemask k1."
"MAXSD xmm1, xmm2/m64","F2 0F 5F /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the maximum scalar double-precision floating-point value between xmm2/m64 and xmm1."
"VMAXSD xmm1, xmm2, xmm3/m64","VEX.NDS.LIG.F2.0F.WIG 5F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the maximum scalar double-precision floating-point value between xmm3/m64 and xmm2."
"VMAXSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}","EVEX.NDS.LIG.F2.0F.W1 5F /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Return the maximum scalar double-precision floating-point value between xmm3/m64 and xmm2."
"MAXSS xmm1, xmm2/m32","F3 0F 5F /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the maximum scalar single-precision floating-point value between xmm2/m32 and xmm1."
"VMAXSS xmm1, xmm2, xmm3/m32","VEX.NDS.LIG.F3.0F.WIG 5F /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the maximum scalar single-precision floating-point value between xmm3/m32 and xmm2."
"VMAXSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}","EVEX.NDS.LIG.F3.0F.W0 5F /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Return the maximum scalar single-precision floating-point value between xmm3/m32 and xmm2."
"MFENCE","NP 0F AE F0","Valid","Valid","Valid","","NA","NA","NA","NA","","Serializes load and store operations."
"MINPD xmm1, xmm2/m128","66 0F 5D /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the minimum double-precision floating-point values between xmm1 and xmm2/mem"
"VMINPD xmm1, xmm2, xmm3/m128","VEX.NDS.128.66.0F.WIG 5D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the minimum double-precision floating-point values between xmm2 and xmm3/mem."
"VMINPD ymm1, ymm2, ymm3/m256","VEX.NDS.256.66.0F.WIG 5D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the minimum packed double-precision floating-point values between ymm2 and ymm3/mem."
"VMINPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst","EVEX.NDS.128.66.0F.W1 5D /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the minimum packed double-precision floating-point values between xmm2 and xmm3/m128/m64bcst and store result in xmm1 subject to writemask k1."
"VMINPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst","EVEX.NDS.256.66.0F.W1 5D /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the minimum packed double-precision floating-point values between ymm2 and ymm3/m256/m64bcst and store result in ymm1 subject to writemask k1."
"VMINPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{sae}","EVEX.NDS.512.66.0F.W1 5D /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the minimum packed double-precision floating-point values between zmm2 and zmm3/m512/m64bcst and store result in zmm1 subject to writemask k1."
"MINPS xmm1, xmm2/m128","NP 0F 5D /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the minimum single-precision floating-point values between xmm1 and xmm2/mem."
"VMINPS xmm1, xmm2, xmm3/m128","VEX.NDS.128.0F.WIG 5D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the minimum single-precision floating-point values between xmm2 and xmm3/mem."
"VMINPS ymm1, ymm2, ymm3/m256","VEX.NDS.256.0F.WIG 5D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the minimum single double-precision floating-point values between ymm2 and ymm3/mem."
"VMINPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst","EVEX.NDS.128.0F.W0 5D /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the minimum packed single-precision floating-point values between xmm2 and xmm3/m128/m32bcst and store result in xmm1 subject to writemask k1."
"VMINPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst","EVEX.NDS.256.0F.W0 5D /r","Valid","Valid","Invalid","AVX512VL AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the minimum packed single-precision floating-point values between ymm2 and ymm3/m256/m32bcst and store result in ymm1 subject to writemask k1."
"VMINPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{sae}","EVEX.NDS.512.0F.W0 5D /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Full Vector","Return the minimum packed single-precision floating-point values between zmm2 and zmm3/m512/m32bcst and store result in zmm1 subject to writemask k1."
"MINSD xmm1, xmm2/m64","F2 0F 5D /r","Valid","Valid","Invalid","SSE2","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the minimum scalar double-precision floating-point value between xmm2/m64 and xmm1."
"VMINSD xmm1, xmm2, xmm3/m64","VEX.NDS.LIG.F2.0F.WIG 5D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the minimum scalar double-precision floating-point value between xmm3/m64 and xmm2."
"VMINSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}","EVEX.NDS.LIG.F2.0F.W1 5D /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Return the minimum scalar double-precision floating-point value between xmm3/m64 and xmm2."
"MINSS xmm1,xmm2/m32","F3 0F 5D /r","Valid","Valid","Invalid","SSE","ModRM:reg (r, w)","ModRM:r/m (r)","NA","NA","NA","Return the minimum scalar single-precision floating-point value between xmm2/m32 and xmm1."
"VMINSS xmm1,xmm2, xmm3/m32","VEX.NDS.LIG.F3.0F.WIG 5D /r","Valid","Valid","Invalid","AVX","ModRM:reg (w)","VEX.vvvv","ModRM:r/m (r)","NA","NA","Return the minimum scalar single-precision floating-point value between xmm3/m32 and xmm2."
"VMINSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}","EVEX.NDS.LIG.F3.0F.W0 5D /r","Valid","Valid","Invalid","AVX512F","ModRM:reg (w)","EVEX.vvvv","ModRM:r/m (r)","NA","Tuple1 Scalar","Return the minimum scalar single-precision floating-point value between xmm3/m32 and xmm2."
"MONITOR","0F 01 C8","Valid","Valid","Valid","","NA","NA","NA","NA","","Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a write- back memory caching type. The address is DS:RAX/EAX/AX."