From 7cd409c9fcdc236d62bbcc5ff78ab921712a1848 Mon Sep 17 00:00:00 2001
From: AUDIY <96096729+AUDIY@users.noreply.github.com>
Date: Mon, 16 Dec 2024 02:53:04 +0900
Subject: [PATCH] Update README.md

Add the link to AUDIY_SV_IP
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 650704b..4b8a394 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,6 @@ Code reviews are welcome!
 The author made a decision to shift HDL from Verilog to SystemVerilog.  
 So it means that the author doesn't maintain and use modules in this repository.
 
-When the author is ready to upload new system verilog IPs, this repository will be archived.
+The new IP repository written in SystemVerilog is [AUDIY_SV_IP](https://github.com/AUDIY/AUDIY_SV_IP)
 
 Thanks.