From 373f3633fe4e6301dc0c4d06adbcad108c7c4355 Mon Sep 17 00:00:00 2001
From: AUDIY <96096729+AUDIY@users.noreply.github.com>
Date: Mon, 16 Dec 2024 20:33:59 +0900
Subject: [PATCH] Update README.md

---
 README.md | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/README.md b/README.md
index 4b8a394..5b9cead 100644
--- a/README.md
+++ b/README.md
@@ -2,11 +2,3 @@
 Verilog IP that AUDIY originally designed.
 
 Code reviews are welcome!
-
-## Notice: This repository is no longer maintained.
-The author made a decision to shift HDL from Verilog to SystemVerilog.  
-So it means that the author doesn't maintain and use modules in this repository.
-
-The new IP repository written in SystemVerilog is [AUDIY_SV_IP](https://github.com/AUDIY/AUDIY_SV_IP)
-
-Thanks.